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/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <debug.h>
#include <events.h>
#include <mm_svc.h>
#include <plat_topology.h>
#include <platform.h>
#include <power_management.h>
#include <secure_partition.h>
#include <smc.h>
#include <spm_svc.h>
#include <test_helpers.h>
#include <tftf_lib.h>
#define MM_COMMUNICATE_DUMMY_ID 42
static event_t cpu_has_finished_test;
/* Test routine for test_secure_partition_secondary_cores_seq() */
static test_result_t test_secure_partition_secondary_cores_seq_fn(void)
{
secure_partition_request_info_t *sps_request
= create_sps_request(MM_COMMUNICATE_DUMMY_ID, NULL, 0);
INFO("Sending MM_COMMUNICATE_AARCH64 from CPU %u\n",
platform_get_core_pos(read_mpidr_el1() & MPID_MASK));
smc_args mm_communicate_smc = {
MM_COMMUNICATE_AARCH64,
0,
(u_register_t) sps_request,
0
};
smc_ret_values smc_ret = tftf_smc(&mm_communicate_smc);
if ((uint32_t)smc_ret.ret0 != 0) {
tftf_testcase_printf("Cactus returned: 0x%x\n",
(uint32_t)smc_ret.ret0);
tftf_send_event(&cpu_has_finished_test);
return TEST_RESULT_FAIL;
}
tftf_send_event(&cpu_has_finished_test);
return TEST_RESULT_SUCCESS;
}
/*
* @Test_Aim@ This tests that secondary CPUs can access SPM services
* sequentially.
*/
test_result_t test_secure_partition_secondary_cores_seq(void)
{
int psci_ret;
u_register_t lead_mpid, cpu_mpid;
unsigned int cpu_node, core_pos;
SKIP_TEST_IF_LESS_THAN_N_CPUS(2);
SKIP_TEST_IF_MM_VERSION_LESS_THAN(1, 0);
lead_mpid = read_mpidr_el1() & MPID_MASK;
INFO("Lead CPU is CPU %u\n", platform_get_core_pos(lead_mpid));
if (test_secure_partition_secondary_cores_seq_fn() != TEST_RESULT_SUCCESS) {
return TEST_RESULT_FAIL;
}
for_each_cpu(cpu_node) {
cpu_mpid = tftf_get_mpidr_from_node(cpu_node);
/* Skip lead CPU, we have already tested it */
if (cpu_mpid == lead_mpid) {
continue;
}
core_pos = platform_get_core_pos(cpu_mpid);
tftf_init_event(&cpu_has_finished_test);
VERBOSE("Powering on CPU %u\n", core_pos);
psci_ret = tftf_cpu_on(cpu_mpid,
(uintptr_t)test_secure_partition_secondary_cores_seq_fn, 0);
if (psci_ret != PSCI_E_SUCCESS) {
tftf_testcase_printf(
"Failed to power on CPU %d (rc = %d)\n",
core_pos, psci_ret);
return TEST_RESULT_FAIL;
}
tftf_wait_for_event(&cpu_has_finished_test);
}
return TEST_RESULT_SUCCESS;
}
/******************************************************************************/
static event_t cpu_can_start_test[PLATFORM_CORE_COUNT];
/* Test routine for test_secure_partition_secondary_core() */
static test_result_t test_secure_partition_secondary_cores_sim_fn(void)
{
u_register_t cpu_mpid = read_mpidr_el1() & MPID_MASK;
unsigned int core_pos = platform_get_core_pos(cpu_mpid);
secure_partition_request_info_t *sps_request
= create_sps_request(MM_COMMUNICATE_DUMMY_ID, NULL, 0);
smc_args mm_communicate_smc = {
MM_COMMUNICATE_AARCH64,
0,
(u_register_t) sps_request,
0
};
tftf_wait_for_event(&cpu_can_start_test[core_pos]);
/*
* Invoke SMCs for some time to make sure that all CPUs are doing it at
* the same time during the test.
*/
for (int i = 0; i < 100; i++) {
smc_ret_values smc_ret = tftf_smc(&mm_communicate_smc);
if ((uint32_t)smc_ret.ret0 != 0) {
tftf_testcase_printf("Cactus returned 0x%x at CPU %d\n",
(uint32_t)smc_ret.ret0, core_pos);
tftf_send_event(&cpu_has_finished_test);
return TEST_RESULT_FAIL;
}
}
return TEST_RESULT_SUCCESS;
}
/*
* @Test_Aim@ This tests that secondary CPUs can access SPM services
* simultaneously.
*/
test_result_t test_secure_partition_secondary_cores_sim(void)
{
int psci_ret;
u_register_t lead_mpid, cpu_mpid;
unsigned int cpu_node, core_pos;
SKIP_TEST_IF_LESS_THAN_N_CPUS(2);
SKIP_TEST_IF_MM_VERSION_LESS_THAN(1, 0);
lead_mpid = read_mpidr_el1() & MPID_MASK;
INFO("Lead CPU is CPU %u\n", platform_get_core_pos(lead_mpid));
for_each_cpu(cpu_node) {
cpu_mpid = tftf_get_mpidr_from_node(cpu_node);
core_pos = platform_get_core_pos(cpu_mpid);
tftf_init_event(&cpu_can_start_test[core_pos]);
}
for_each_cpu(cpu_node) {
cpu_mpid = tftf_get_mpidr_from_node(cpu_node);
/* Skip lead CPU as it is already powered on */
if (cpu_mpid == lead_mpid) {
continue;
}
core_pos = platform_get_core_pos(cpu_mpid);
VERBOSE("Powering on CPU %u\n", core_pos);
psci_ret = tftf_cpu_on(cpu_mpid,
(uintptr_t)test_secure_partition_secondary_cores_sim_fn, 0);
if (psci_ret != PSCI_E_SUCCESS) {
tftf_testcase_printf(
"Failed to power on CPU %d (rc = %d)\n",
core_pos, psci_ret);
return TEST_RESULT_FAIL;
}
}
for_each_cpu(cpu_node) {
cpu_mpid = tftf_get_mpidr_from_node(cpu_node);
core_pos = platform_get_core_pos(cpu_mpid);
tftf_send_event(&cpu_can_start_test[core_pos]);
}
return test_secure_partition_secondary_cores_sim_fn();
}
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