diff options
Diffstat (limited to 'arch')
33 files changed, 2258 insertions, 139 deletions
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 0c49caa0997..17c5e26f4b6 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -30,10 +30,12 @@ }; sdhci@12530000 { - samsung,sdhci-bus-width = <4>; - linux,mmc_cap_4_bit_data; + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12530000 0x100>; + interrupts = <0 75 0>; + bus-width = <4>; samsung,sdhci-cd-internal; - gpio-cd = <&gpk2 2 2 3 3>; + cd-gpios = <&gpk2 2 2 3 3>; gpios = <&gpk2 0 2 0 3>, <&gpk2 1 2 0 3>, <&gpk2 3 2 3 3>, @@ -43,10 +45,12 @@ }; sdhci@12510000 { - samsung,sdhci-bus-width = <4>; - linux,mmc_cap_4_bit_data; + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12510000 0x100>; + interrupts = <0 73 0>; + bus-width = <4>; samsung,sdhci-cd-internal; - gpio-cd = <&gpk0 2 2 3 3>; + cd-gpios = <&gpk0 2 2 3 3>; gpios = <&gpk0 0 2 0 3>, <&gpk0 1 2 0 3>, <&gpk0 3 2 3 3>, @@ -55,6 +59,66 @@ <&gpk0 6 2 3 3>; }; + lcd_fimd0: lcd_panel0 { + compatible = "lcd-powercontrol"; + vcc-lcd-supply = <&buck7_reg>; + lcd-reset-gpio = <&gpe3 4 1 0 0>; + lcd-htiming = <64 16 48 1024>; + lcd-vtiming = <64 16 3 600>; + }; + + fimd@11C00000 { + samsung,fimd-display = <&lcd_fimd0>; + samsung,fimd-vidout-rgb; + samsung,fimd-inv-hsync; + samsung,fimd-inv-vsync; + samsung,fimd-inv-vclk; + samsung,fimd-frame-rate = <60>; + + gpios = <&gpf0 0 2 0 0>, + <&gpf0 1 2 0 0>, + <&gpf0 2 2 0 0>, + <&gpf0 3 2 0 0>, + <&gpf0 4 2 0 0>, + <&gpf0 5 2 0 0>, + <&gpf0 6 2 0 0>, + <&gpf0 7 2 0 0>, + <&gpf1 0 2 0 0>, + <&gpf1 1 2 0 0>, + <&gpf1 2 2 0 0>, + <&gpf1 3 2 0 0>, + <&gpf1 4 2 0 0>, + <&gpf1 5 2 0 0>, + <&gpf1 6 2 0 0>, + <&gpf1 7 2 0 0>, + <&gpf2 0 2 0 0>, + <&gpf2 1 2 0 0>, + <&gpf2 2 2 0 0>, + <&gpf2 3 2 0 0>, + <&gpf2 4 2 0 0>, + <&gpf2 5 2 0 0>, + <&gpf2 6 2 0 0>, + <&gpf2 7 2 0 0>, + <&gpf3 0 2 0 0>, + <&gpf3 1 2 0 0>, + <&gpf3 2 2 0 0>, + <&gpf3 3 2 0 0>; + + window0 { + samsung,fimd-win-id = <0>; + samsung,fimd-win-bpp = <32 24>; + samsung,fimd-win-res = <1024 600>; + samsung,fimd-win-vres = <1024 600>; + }; + + window1 { + samsung,fimd-win-id = <1>; + samsung,fimd-win-bpp = <32 24>; + samsung,fimd-win-res = <1024 600>; + samsung,fimd-win-vres = <1024 600>; + }; + }; + gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -64,30 +128,35 @@ label = "Up"; gpios = <&gpx2 0 0 0 2>; linux,code = <103>; + gpio-key,wakeup; }; down { label = "Down"; gpios = <&gpx2 1 0 0 2>; linux,code = <108>; + gpio-key,wakeup; }; back { label = "Back"; gpios = <&gpx1 7 0 0 2>; linux,code = <158>; + gpio-key,wakeup; }; home { label = "Home"; gpios = <&gpx1 6 0 0 2>; linux,code = <102>; + gpio-key,wakeup; }; menu { label = "Menu"; gpios = <&gpx1 5 0 0 2>; linux,code = <139>; + gpio-key,wakeup; }; }; @@ -104,11 +173,126 @@ }; i2c@13860000 { - status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + gpios = <&gpd1 0 2 3 0>, + <&gpd1 1 2 3 0>; + + max8997_pmic@66 { + compatible = "maxim,max8997-pmic"; + interrupt-parent = <&wakeup_eint>; + reg = <0x66>; + interrupts = <4 0>, <3 0>; + + max8997,pmic-buck1-uses-gpio-dvs; + max8997,pmic-buck2-uses-gpio-dvs; + max8997,pmic-buck5-uses-gpio-dvs; + max8997,pmic-ignore-gpiodvs-side-effect; + max8997,pmic-buck125-default-dvs-idx = <0>; + max8997,pmic-buck125-dvs-gpios = <&gpx0 0 1 0 0>, /* SET1 */ + <&gpx0 1 1 0 0>, /* SET2 */ + <&gpx0 2 1 0 0>; /* SET3 */ + max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + max8997,pmic-buck2-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1000000>, <1000000>, + <1000000>, <1000000>; + max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ABB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_ALIVE_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VMIPI_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_RTC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_AUD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_AUD_3V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "VDD_LCD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + + unidisplay_ts@41 { + compatible = "pixcir,unidisplay-ts"; + interrupt-parent = <&wakeup_eint>; + reg = <0x41>; + interrupts = <25 0>; + }; }; i2c@13870000 { - status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + gpios = <&gpd1 2 2 3 0>, + <&gpd1 3 2 3 0>; + + codec: alc5625@1e { + compatible = "realtek,alc5625"; + reg = <0x1e>; + }; + }; i2c@13880000 { @@ -146,4 +330,65 @@ spi_2: spi@13940000 { status = "disabled"; }; + + pd_cam: pd-cam { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C00 0x10>; + }; + + pd_tv: pd-tv { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C20 0x10>; + }; + + pd_mfc: pd-mfc { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C40 0x10>; + }; + + pd_g3d: pd-g3d { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C60 0x10>; + }; + + pd_lcd0: pd-lcd0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C80 0x10>; + }; + + pd_lcd1: pd-lcd1 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CA0 0x10>; + }; + + pd_gps: pd-gps { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CE0 0x10>; + samsung,exynos4210-pd_off; + }; + + usb@12480000 { + vusb_a-supply = <&ldo3_reg>; + vusb_d-supply = <&ldo3_reg>; + }; + + i2s_0: i2s@03830000 { + gpios = <&gpz 0 2 0 0>, + <&gpz 1 2 0 0>, + <&gpz 2 2 0 0>, + <&gpz 3 2 0 0>, + <&gpz 4 2 0 0>, + <&gpz 5 2 0 0>, + <&gpz 6 2 0 0>; + idma-addr = <0x03000000>; + }; + + asoc_dma { + compatible = "samsung,audio-dma"; + }; + + origen_audio { + compatible = "samsung,origen_audio"; + }; + }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 02891fe876e..f1d91935c61 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -29,6 +29,7 @@ spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; + i2s0 = &i2s_0; }; gic:interrupt-controller@10490000 { @@ -50,6 +51,30 @@ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; }; + wakeup_eint: interrupt-controller-wakeup-eint { + compatible = "samsung,exynos4210-wakeup-eint"; + reg = <0x11000000 0x1000>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>, + <0 32 0>; + }; + + power-domain-lcd0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C00 0x10>; + }; + + fimd@11C00000 { + compatible = "samsung,exynos4210-fimd"; + interrupt-parent = <&combiner>; + reg = <0x11C00000 0x8000>; + interrupts = <11 1>, <11 0>, <11 2>; + }; + watchdog@10060000 { compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; @@ -442,4 +467,33 @@ #gpio-cells = <4>; }; }; + + usb@12580000 { + compatible = "samsung,exynos-ehci", "usb-ehci"; + reg = <0x12580000 0x100>; + interrupts = <0 70 0>; + }; + + usb@12590000 { + compatible = "samsung,exynos-ohci", "usb-ohci"; + reg = <0x12590000 0x100>; + interrupts = <0 70 0>; + }; + + usb@12480000 { + compatible = "samsung,exynos-hsotg"; + reg = <0x12480000 0x20000>; + interrupts = <0 71 0>; + }; + + i2s_0: i2s@03830000 { + compatible = "samsung,samsung-i2s"; + reg = <0x03830000 0x100>; + tx-dma-channel-secondary = <&pdma0 10>; + tx-dma-channel = <&pdma0 12>; + rx-dma-channel = <&pdma0 11>; + supports-6ch; + supports-rstclr; + supports-secdai; + }; }; diff --git a/arch/arm/configs/android_origen_defconfig b/arch/arm/configs/android_origen_defconfig new file mode 100644 index 00000000000..d04cf033d26 --- /dev/null +++ b/arch/arm/configs/android_origen_defconfig @@ -0,0 +1,210 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PERF_COUNTERS=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_GCOV_KERNEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_BSD_DISKLABEL=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_ARCH_EXYNOS=y +CONFIG_S3C_LOWLEVEL_UART_PORT=2 +CONFIG_S3C24XX_PWM=y +CONFIG_MACH_SMDKC210=y +CONFIG_MACH_ARMLEX4210=y +CONFIG_MACH_UNIVERSAL_C210=y +CONFIG_MACH_NURI=y +CONFIG_MACH_ORIGEN=y +CONFIG_MACH_SMDK4412=y +CONFIG_MACH_EXYNOS4_DT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_NR_CPUS=2 +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc mem=256M" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_NETLINK_ACCT=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_CFG80211=y +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_NETDEVICES=y +CONFIG_USB_PEGASUS=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_DM9601=y +CONFIG_USB_NET_MCS7830=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_ATH_COMMON=y +CONFIG_ATH_DEBUG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_PLATFORM_DATA=y +CONFIG_ATH6KL_POLL=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_UNIDISPLAY_TS=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_S3C2410=y +CONFIG_POWER_SUPPLY=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_SENSORS_EXYNOS4_TMU=y +CONFIG_MFD_MAX8997=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DUMMY=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MAX8997=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +# CONFIG_VIDEO_IR_I2C is not set +CONFIG_VIDEO_S5K4ECGX=y +CONFIG_VIDEO_S5K4ECGX_V_1_1=y +CONFIG_VIDEO_S5K4ECGX_SLSI_4EC=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_V4L_USB_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_FIMC=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_G2D=y +CONFIG_VIDEO_SAMSUNG_S5P_JPEG=y +CONFIG_VIDEO_SAMSUNG_S5P_MFC=y +CONFIG_DRM=y +CONFIG_ION=y +CONFIG_MALI400MP=y +CONFIG_USING_PMM=y +CONFIG_UMP=y +CONFIG_FB=y +CONFIG_FB_S3C=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_LCD_PWRCTRL=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_HID_KYE=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_S5P=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_S3C_HSOTG=y +CONFIG_USB_G_ANDROID=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_PERSISTENT_TRACER=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ANDROID_SWITCH=y +CONFIG_SND_SOC_ORIGEN_ALC5625=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_PSTORE=y +CONFIG_PSTORE_RAM=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_INFO=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_DEBUG_USER=y +CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig index bffe68e190a..acddcf3d251 100644 --- a/arch/arm/configs/exynos4_defconfig +++ b/arch/arm/configs/exynos4_defconfig @@ -5,43 +5,155 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_EXYNOS=y -CONFIG_S3C_LOWLEVEL_UART_PORT=1 +CONFIG_S3C_LOWLEVEL_UART_PORT=2 +CONFIG_S3C24XX_PWM=y CONFIG_MACH_SMDKC210=y CONFIG_MACH_ARMLEX4210=y CONFIG_MACH_UNIVERSAL_C210=y CONFIG_MACH_NURI=y CONFIG_MACH_ORIGEN=y CONFIG_MACH_SMDK4412=y +CONFIG_MACH_EXYNOS4_DT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y CONFIG_NR_CPUS=2 CONFIG_PREEMPT=y CONFIG_AEABI=y -CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" +CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc mem=256M" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y CONFIG_VFP=y CONFIG_NEON=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IPV6=y +CONFIG_CFG80211=y +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y +CONFIG_NETDEVICES=y +CONFIG_USB_PEGASUS=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_DM9601=y +CONFIG_USB_NET_MCS7830=y +CONFIG_ATH_COMMON=y +CONFIG_ATH_DEBUG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_PLATFORM_DATA=y +CONFIG_ATH6KL_POLL=y CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set +CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_UNIDISPLAY_TS=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_I2C=y +CONFIG_I2C_S3C2410=y +CONFIG_POWER_SUPPLY=y # CONFIG_HWMON is not set -# CONFIG_MFD_SUPPORT is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_MFD_MAX8997=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DUMMY=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MAX8997=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_FIMC=y +CONFIG_VIDEO_S5P_FIMC=y +CONFIG_VIDEO_SAMSUNG_S5P_TV=y +CONFIG_VIDEO_SAMSUNG_S5P_HDMI=y +CONFIG_VIDEO_SAMSUNG_S5P_SDO=y +CONFIG_VIDEO_SAMSUNG_S5P_MIXER=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_G2D=y +CONFIG_VIDEO_SAMSUNG_S5P_JPEG=y +CONFIG_VIDEO_SAMSUNG_S5P_MFC=y +CONFIG_FB=y +CONFIG_FB_S3C=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_LCD_PWRCTRL=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_S5P=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_S3C_HSOTG=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +CONFIG_USB_G_DBGP_PRINTK=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y +CONFIG_STAGING=y +CONFIG_SND_SOC_ORIGEN_ALC5625=y CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y @@ -54,7 +166,9 @@ CONFIG_SOLARIS_X86_PARTITION=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_RT_MUTEXES=y @@ -63,6 +177,4 @@ CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_INFO=y CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_EARLY_PRINTK=y CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/ubuntu_origen_defconfig b/arch/arm/configs/ubuntu_origen_defconfig new file mode 100644 index 00000000000..09ec48091b0 --- /dev/null +++ b/arch/arm/configs/ubuntu_origen_defconfig @@ -0,0 +1,242 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PERF_COUNTERS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_MODULES=y +CONFIG_ARCH_EXYNOS=y +CONFIG_S3C_LOWLEVEL_UART_PORT=2 +CONFIG_S3C24XX_PWM=y +CONFIG_MACH_SMDKC210=y +CONFIG_MACH_ARMLEX4210=y +CONFIG_MACH_UNIVERSAL_C210=y +CONFIG_MACH_NURI=y +CONFIG_MACH_ORIGEN=y +CONFIG_MACH_SMDK4412=y +CONFIG_MACH_EXYNOS4_DT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_NR_CPUS=2 +CONFIG_THUMB2_KERNEL=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_SECCOMP=y +CONFIG_CC_STACKPROTECTOR=y +CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc mem=256M" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETLABEL=y +CONFIG_NETFILTER=y +CONFIG_CFG80211=y +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_OOPS=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_NAND=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +CONFIG_USB_PEGASUS=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_DM9601=y +CONFIG_USB_NET_MCS7830=y +CONFIG_ATH_COMMON=y +CONFIG_ATH_DEBUG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_PLATFORM_DATA=y +CONFIG_ATH6KL_POLL=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_UNIDISPLAY_TS=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_S3C2410=y +CONFIG_POWER_SUPPLY=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_SENSORS_EXYNOS4_TMU=y +CONFIG_MFD_MAX8997=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DUMMY=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MAX8997=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_FIMC=y +CONFIG_VIDEO_S5P_FIMC=y +CONFIG_VIDEO_SAMSUNG_S5P_TV=y +CONFIG_VIDEO_SAMSUNG_S5P_HDMI=y +CONFIG_VIDEO_SAMSUNG_S5P_SDO=y +CONFIG_VIDEO_SAMSUNG_S5P_MIXER=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_G2D=y +CONFIG_VIDEO_SAMSUNG_S5P_JPEG=y +CONFIG_VIDEO_SAMSUNG_S5P_MFC=y +CONFIG_FB=y +CONFIG_FB_S3C=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_LCD_PWRCTRL=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_S5P=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_S3C_HSOTG=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE_TEST=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +CONFIG_USB_G_DBGP_PRINTK=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y +CONFIG_STAGING=y +CONFIG_SND_SOC_ORIGEN_ALC5625=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y +CONFIG_BTRFS_FS=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RUBIN=y +CONFIG_CRAMFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_INFO=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_DEBUG_USER=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +CONFIG_PROVE_LOCKING=y +CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_STRICT_DEVMEM=y +CONFIG_KEYS=y +CONFIG_SECURITY=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_DEFAULT_SECURITY_APPARMOR=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index b5b4c8c9db1..33c20f635e4 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -327,6 +327,8 @@ config MACH_ORIGEN select S3C_DEV_WDT select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 + select S3C_DEV_I2C1 select S3C_DEV_USB_HSOTG select S5P_DEV_FIMC0 select S5P_DEV_FIMC1 @@ -334,6 +336,7 @@ config MACH_ORIGEN select S5P_DEV_FIMC3 select S5P_DEV_FIMD0 select S5P_DEV_G2D + select S5P_DEV_G3D select S5P_DEV_I2C_HDMIPHY select S5P_DEV_JPEG select S5P_DEV_MFC @@ -346,6 +349,7 @@ config MACH_ORIGEN select EXYNOS_DEV_DMA select EXYNOS4_DEV_USB_OHCI select EXYNOS4_SETUP_FIMD0 + select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_SDHCI select EXYNOS4_SETUP_USB_PHY help @@ -405,6 +409,8 @@ config MACH_EXYNOS4_DT select USE_OF select ARM_AMBA select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD + select SAMSUNG_DEV_BACKLIGHT + select SAMSUNG_DEV_PWM help Machine support for Samsung Exynos4 machine with device tree enabled. Select this if a fdt blob is available for the Exynos4 SoC based board. diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 9b58024f7d4..5088695f4a7 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o +obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += asv.o asv-4210.o obj-$(CONFIG_ARCH_EXYNOS) += pmu.o diff --git a/arch/arm/mach-exynos/asv-4210.c b/arch/arm/mach-exynos/asv-4210.c new file mode 100644 index 00000000000..8f08cb2898f --- /dev/null +++ b/arch/arm/mach-exynos/asv-4210.c @@ -0,0 +1,339 @@ +/* linux/arch/arm/mach-exynos/asv-4210.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS4210 - ASV(Adaptive Support Voltage) driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <plat/clock.h> + +#include <mach/regs-iem.h> +#include <mach/regs-clock.h> +#include <mach/asv.h> + +/* + * exynos_result_of_asv is result of ASV group. + * Using by this value, other driver can adjust voltage. + */ +unsigned int exynos_result_of_asv; + +enum target_asv { + EXYNOS4210_1200, + EXYNOS4210_1400, + EXYNOS4210_SINGLE_1200, +}; + +struct asv_judge_table exynos4210_1200_limit[] = { + /* HPM , IDS */ + {8 , 4}, + {11 , 8}, + {14 , 12}, + {18 , 17}, + {21 , 27}, + {23 , 45}, + {25 , 55}, +}; + +static struct asv_judge_table exynos4210_1400_limit[] = { + /* HPM , IDS */ + {13 , 8}, + {17 , 12}, + {22 , 32}, + {26 , 52}, +}; + +static struct asv_judge_table exynos4210_single_1200_limit[] = { + /* HPM , IDS */ + {8 , 4}, + {14 , 12}, + {21 , 27}, + {25 , 55}, +}; + +static int exynos4210_asv_pre_clock_init(void) +{ + struct clk *clk_hpm; + struct clk *clk_copy; + struct clk *clk_parent; + + /* PWI clock setting */ + clk_copy = clk_get(NULL, "sclk_pwi"); + if (IS_ERR(clk_copy)) + goto clock_fail; + else { + clk_parent = clk_get(NULL, "xusbxti"); + + if (IS_ERR(clk_parent)) { + clk_put(clk_copy); + + goto clock_fail; + } + if (clk_set_parent(clk_copy, clk_parent)) + goto clock_fail; + + clk_put(clk_parent); + } + clk_set_rate(clk_copy, (48 * MHZ)); + + clk_put(clk_copy); + + /* HPM clock setting */ + clk_copy = clk_get(NULL, "dout_copy"); + if (IS_ERR(clk_copy)) + goto clock_fail; + else { + clk_parent = clk_get(NULL, "mout_mpll"); + if (IS_ERR(clk_parent)) { + clk_put(clk_copy); + + goto clock_fail; + } + if (clk_set_parent(clk_copy, clk_parent)) + goto clock_fail; + + clk_put(clk_parent); + } + + clk_set_rate(clk_copy, (400 * MHZ)); + + clk_put(clk_copy); + + clk_hpm = clk_get(NULL, "sclk_hpm"); + if (IS_ERR(clk_hpm)) + goto clock_fail; + + clk_set_rate(clk_hpm, (200 * MHZ)); + + clk_put(clk_hpm); + + return 0; + +clock_fail: + pr_err("EXYNOS4210: ASV: Clock init fail\n"); + + return -EBUSY; +} + +static int exynos4210_asv_pre_clock_setup(void) +{ + /* APLL_CON0 level register */ + __raw_writel(0x80FA0601, EXYNOS4_APLL_CON0L8); + __raw_writel(0x80C80601, EXYNOS4_APLL_CON0L7); + __raw_writel(0x80C80602, EXYNOS4_APLL_CON0L6); + __raw_writel(0x80C80604, EXYNOS4_APLL_CON0L5); + __raw_writel(0x80C80601, EXYNOS4_APLL_CON0L4); + __raw_writel(0x80C80601, EXYNOS4_APLL_CON0L3); + __raw_writel(0x80C80601, EXYNOS4_APLL_CON0L2); + __raw_writel(0x80C80601, EXYNOS4_APLL_CON0L1); + + /* IEM Divider register */ + __raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L8); + __raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L7); + __raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L6); + __raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L5); + __raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L4); + __raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L3); + __raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L2); + __raw_writel(0x00500000, EXYNOS4_CLKDIV_IEM_L1); + + return 0; +} + +static int exynos4210_find_group(struct samsung_asv *asv_info, + enum target_asv exynos4_target) +{ + unsigned int ret = 0; + unsigned int i; + + if (exynos4_target == EXYNOS4210_1200) { + ret = ARRAY_SIZE(exynos4210_1200_limit); + + for (i = 0; i < ARRAY_SIZE(exynos4210_1200_limit); i++) { + if (asv_info->hpm_result <= exynos4210_1200_limit[i].hpm_limit || + asv_info->ids_result <= exynos4210_1200_limit[i].ids_limit) { + ret = i; + break; + } + } + } else if (exynos4_target == EXYNOS4210_1400) { + ret = ARRAY_SIZE(exynos4210_1400_limit); + + for (i = 0; i < ARRAY_SIZE(exynos4210_1400_limit); i++) { + if (asv_info->hpm_result <= exynos4210_1400_limit[i].hpm_limit || + asv_info->ids_result <= exynos4210_1400_limit[i].ids_limit) { + ret = i; + break; + } + } + } else if (exynos4_target == EXYNOS4210_SINGLE_1200) { + ret = ARRAY_SIZE(exynos4210_single_1200_limit); + + for (i = 0; i < ARRAY_SIZE(exynos4210_single_1200_limit); i++) { + if (asv_info->hpm_result <= exynos4210_single_1200_limit[i].hpm_limit || + asv_info->ids_result <= exynos4210_single_1200_limit[i].ids_limit) { + ret = i; + break; + } + } + } + + return ret; +} + +#define PACK_ID 8 +#define PACK_MASK 0x3 + +#define SUPPORT_1400MHZ (1 << 31) +#define SUPPORT_1200MHZ (1 << 30) +#define SUPPORT_1000MHZ (1 << 29) + +static int exynos4210_get_hpm(struct samsung_asv *asv_info) +{ + unsigned int i; + unsigned int tmp; + unsigned int hpm_delay = 0; + void __iomem *iem_base; + + iem_base = ioremap(EXYNOS4_PA_IEM, SZ_128K); + + if (!iem_base) { + pr_err("EXYNOS4210: ASV: ioremap fail\n"); + return -EPERM; + } + + /* Clock setting to get asv value */ + if (!asv_info->pre_clock_init) + goto err; + else { + if (asv_info->pre_clock_init()) + goto err; + else { + /* HPM enable */ + tmp = __raw_readl(iem_base + EXYNOS4_APC_CONTROL); + tmp |= APC_HPM_EN; + __raw_writel(tmp, (iem_base + EXYNOS4_APC_CONTROL)); + + asv_info->pre_clock_setup(); + + /* IEM enable */ + tmp = __raw_readl(iem_base + EXYNOS4_IECDPCCR); + tmp |= IEC_EN; + __raw_writel(tmp, (iem_base + EXYNOS4_IECDPCCR)); + } + } + + /* Get HPM Delay value */ + for (i = 0; i < EXYNOS4_LOOP_CNT; i++) { + tmp = __raw_readb(iem_base + EXYNOS4_APC_DBG_DLYCODE); + hpm_delay += tmp; + } + + hpm_delay /= EXYNOS4_LOOP_CNT; + + /* Store result of hpm value */ + asv_info->hpm_result = hpm_delay; + + return 0; + +err: + pr_err("EXYNOS4210: ASV: Failt to get hpm function\n"); + + iounmap(iem_base); + + return -EPERM; +} + +static int exynos4210_get_ids(struct samsung_asv *asv_info) +{ + unsigned int pkg_id_val; + + if (!asv_info->ids_offset || !asv_info->ids_mask) { + pr_err("EXYNOS4210: ASV: No ids_offset or No ids_mask\n"); + + return -EPERM; + } + + pkg_id_val = __raw_readl(S5P_VA_CHIPID + 0x4); + asv_info->pkg_id = pkg_id_val; + asv_info->ids_result = ((pkg_id_val >> asv_info->ids_offset) & + asv_info->ids_mask); + + return 0; +} + +static int exynos4210_asv_store_result(struct samsung_asv *asv_info) +{ + unsigned int result_grp; + char *support_freq; + unsigned int exynos_idcode = 0x0; + + exynos_result_of_asv = 0; + + exynos_idcode = __raw_readl(S5P_VA_CHIPID); + + /* Single chip is only support 1.2GHz */ + if (!((exynos_idcode >> PACK_ID) & PACK_MASK)) { + result_grp = exynos4210_find_group(asv_info, EXYNOS4210_SINGLE_1200); + result_grp |= SUPPORT_1200MHZ; + support_freq = "1.2GHz"; + + goto set_reg; + } + + /* Check support freq */ + switch (asv_info->pkg_id & 0x7) { + /* Support 1.2GHz */ + case 1: + case 7: + result_grp = exynos4210_find_group(asv_info, EXYNOS4210_1200); + result_grp |= SUPPORT_1200MHZ; + support_freq = "1.2GHz"; + break; + /* Support 1.4GHz */ + case 5: + result_grp = exynos4210_find_group(asv_info, EXYNOS4210_1400); + result_grp |= SUPPORT_1200MHZ; + support_freq = "1.4GHz"; + break; + /* Defalut support 1.0GHz */ + default: + result_grp = exynos4210_find_group(asv_info, EXYNOS4210_1200); + result_grp |= SUPPORT_1000MHZ; + support_freq = "1.0GHz"; + break; + } + +set_reg: + exynos_result_of_asv = result_grp; + + pr_info("EXYNOS4: ASV: Support %s and Group is 0x%x\n", + support_freq, result_grp); + + return 0; +} + +void exynos4210_asv_init(struct samsung_asv *asv_info) +{ + pr_info("EXYNOS4210: Adaptive Support Voltage init\n"); + + asv_info->ids_offset = 24; + asv_info->ids_mask = 0xFF; + + asv_info->get_ids = exynos4210_get_ids; + asv_info->get_hpm = exynos4210_get_hpm; + asv_info->pre_clock_init = exynos4210_asv_pre_clock_init; + asv_info->pre_clock_setup = exynos4210_asv_pre_clock_setup; + asv_info->store_result = exynos4210_asv_store_result; +} diff --git a/arch/arm/mach-exynos/asv.c b/arch/arm/mach-exynos/asv.c new file mode 100644 index 00000000000..d0a33d3cecf --- /dev/null +++ b/arch/arm/mach-exynos/asv.c @@ -0,0 +1,71 @@ +/* linux/arch/arm/mach-exynos/asv.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS4 - ASV(Adaptive Support Voltage) driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> + +#include <plat/cpu.h> + +#include <mach/map.h> +#include <mach/asv.h> + +static struct samsung_asv *exynos_asv; + +static int __init exynos_asv_init(void) +{ + exynos_asv = kzalloc(sizeof(struct samsung_asv), GFP_KERNEL); + if (!exynos_asv) + goto out; + + if (soc_is_exynos4210()) + exynos4210_asv_init(exynos_asv); + else + goto out; + + if (exynos_asv->check_vdd_arm) { + if (exynos_asv->check_vdd_arm()) + goto out; + } + + /* Get HPM Delay value */ + if (exynos_asv->get_hpm) { + if (exynos_asv->get_hpm(exynos_asv)) + goto out; + } else + goto out; + + /* Get IDS ARM Value */ + if (exynos_asv->get_ids) { + if (exynos_asv->get_ids(exynos_asv)) + goto out; + } else + goto out; + + if (exynos_asv->store_result) { + if (exynos_asv->store_result(exynos_asv)) + goto out; + } else + goto out; + + return 0; +out: + pr_err("EXYNOS : Fail to initialize ASV\n"); + + kfree(exynos_asv); + + return -EINVAL; +} +device_initcall_sync(exynos_asv_init); diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index af51a5fd638..35bf3ba6e18 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -25,12 +25,14 @@ #include <mach-exynos/map.h> #include <mach-exynos/regs-clock.h> #include <mach-exynos/sysmmu.h> +#include <mach-exynos/regs-audss.h> #include "common.h" #include "clock-exynos4.h" #ifdef CONFIG_PM_SLEEP static struct sleep_save exynos4_clock_save[] = { + SAVE_ITEM(EXYNOS4_CLKSRC_AUDSS), SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS), SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS), SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS), @@ -118,6 +120,10 @@ static struct clk dummy_apb_pclk = { .id = -1, }; +static struct clk exynos4_clk_xxti = { + .name = "xxti", +}; + static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable); @@ -313,6 +319,25 @@ static struct clksrc_clk exynos4_clk_periphclk = { .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 }, }; +static struct clk *exynos4_clkset_mout_hpm_list[] = { + [0] = &exynos4_clk_mout_apll.clk, + [1] = &exynos4_clk_mout_mpll.clk, +}; + +static struct clksrc_sources exynos4_clkset_sclk_hpm = { + .sources = exynos4_clkset_mout_hpm_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_hpm_list), +}; + +static struct clksrc_clk exynos4_clk_dout_copy = { + .clk = { + .name = "dout_copy", + }, + .sources = &exynos4_clkset_sclk_hpm, + .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 20, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU1, .shift = 0, .size = 3 }, +}; + /* Core list of CMU_CORE side */ static struct clk *exynos4_clkset_corebus_list[] = { @@ -793,6 +818,24 @@ static struct clk exynos4_clk_fimd0 = { .ctrlbit = (1 << 0), }; +static struct clk *exynos4_clkset_mout_audss_list[] = { + &exynos4_clk_xxti, + &clk_fout_epll, +}; + +static struct clksrc_sources exynos4_clkset_mout_audss = { + .sources = exynos4_clkset_mout_audss_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_audss_list), +}; + +static struct clksrc_clk exynos4_clk_mout_audss = { + .clk = { + .name = "busclk", + }, + .sources = &exynos4_clkset_mout_audss, + .reg_src = { .reg = EXYNOS4_CLKSRC_AUDSS, .shift = 0, .size = 1 }, +}; + struct clk *exynos4_clkset_group_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_xusbxti, @@ -1110,7 +1153,20 @@ static struct clksrc_clk exynos4_clksrcs[] = { .ctrlbit = (1 << 16), }, .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 }, - } + }, { + .clk = { + .name = "sclk_hpm", + .parent = &exynos4_clk_dout_copy.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU1, .shift = 4, .size = 3 }, + }, { + .clk = { + .name = "sclk_pwi", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 8, .size = 4 }, + }, }; static struct clksrc_clk exynos4_clk_sclk_uart0 = { @@ -1279,6 +1335,7 @@ static struct clksrc_clk *exynos4_sysclks[] = { &exynos4_clk_armclk, &exynos4_clk_aclk_corem0, &exynos4_clk_aclk_cores, + &exynos4_clk_dout_copy, &exynos4_clk_aclk_corem1, &exynos4_clk_periphclk, &exynos4_clk_mout_corebus, @@ -1293,6 +1350,7 @@ static struct clksrc_clk *exynos4_sysclks[] = { &exynos4_clk_aclk_100, &exynos4_clk_aclk_160, &exynos4_clk_aclk_133, + &exynos4_clk_mout_audss, &exynos4_clk_dout_mmc0, &exynos4_clk_dout_mmc1, &exynos4_clk_dout_mmc2, @@ -1342,6 +1400,7 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), + CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &exynos4_clk_mout_audss.clk), }; static int xtal_rate; @@ -1357,6 +1416,78 @@ static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) return 0; } +static u32 exynos4_epll_div[][6] = { + { 48000000, 0, 48, 3, 3, 0 }, + { 96000000, 0, 48, 3, 2, 0 }, + { 144000000, 1, 72, 3, 2, 0 }, + { 192000000, 0, 48, 3, 1, 0 }, + { 288000000, 1, 72, 3, 1, 0 }, + { 84000000, 0, 42, 3, 2, 0 }, + { 50000000, 0, 50, 3, 3, 0 }, + { 80000000, 1, 80, 3, 3, 0 }, + { 32750000, 1, 65, 3, 4, 35127 }, + { 32768000, 1, 65, 3, 4, 35127 }, + { 49152000, 0, 49, 3, 3, 9961 }, + { 67737600, 1, 67, 3, 3, 48366 }, + { 73728000, 1, 73, 3, 3, 47710 }, + { 45158400, 0, 45, 3, 3, 10381 }, + { 45000000, 0, 45, 3, 3, 10355 }, + { 45158000, 0, 45, 3, 3, 10355 }, + { 49125000, 0, 49, 3, 3, 9961 }, + { 67738000, 1, 67, 3, 3, 48366 }, + { 73800000, 1, 73, 3, 3, 47710 }, + { 36000000, 1, 32, 3, 4, 0 }, + { 60000000, 1, 60, 3, 3, 0 }, + { 72000000, 1, 72, 3, 3, 0 }, + { 191923200, 0, 47, 3, 1, 64278 }, + { 180633600, 0, 45, 3, 1, 10381 }, +}; + +static int exynos4_epll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int epll_con, epll_con_k; + unsigned int i; + + /* Return if nothing changed */ + if (clk->rate == rate) + return 0; + + epll_con = __raw_readl(EXYNOS4_EPLL_CON0); + epll_con &= ~(0x1 << 27 | \ + PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ + PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ + PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(exynos4_epll_div); i++) { + if (exynos4_epll_div[i][0] == rate) { + epll_con_k = exynos4_epll_div[i][5] << 0; + epll_con |= exynos4_epll_div[i][1] << 27; + epll_con |= exynos4_epll_div[i][2] << PLL46XX_MDIV_SHIFT; + epll_con |= exynos4_epll_div[i][3] << PLL46XX_PDIV_SHIFT; + epll_con |= exynos4_epll_div[i][4] << PLL46XX_SDIV_SHIFT; + break; + } + } + + if (i == ARRAY_SIZE(exynos4_epll_div)) { + printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", + __func__); + return -EINVAL; + } + + __raw_writel(epll_con, EXYNOS4_EPLL_CON0); + __raw_writel(epll_con_k, EXYNOS4_EPLL_CON1); + + clk->rate = rate; + + return 0; +} + +static struct clk_ops exynos4_epll_ops = { + .get_rate = s5p_epll_get_rate, + .set_rate = exynos4_epll_set_rate, +}; + static struct clk_ops exynos4_fout_apll_ops = { .get_rate = exynos4_fout_apll_get_rate, }; @@ -1486,6 +1617,10 @@ void __init_or_cpufreq exynos4_setup_clocks(void) clk_fout_vpll.ops = &exynos4_vpll_ops; clk_fout_vpll.rate = vpll; + clk_fout_epll.enable = s5p_epll_enable; + clk_fout_epll.ops = &exynos4_epll_ops; + clk_set_parent(&exynos4_clk_mout_audss.clk, &clk_fout_epll); + printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", apll, mpll, epll, vpll); diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 5fd3af4d4a3..3f9d89d77b2 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -53,6 +53,12 @@ #define L2_AUX_VAL 0x7C470001 #define L2_AUX_MASK 0xC200ffff +#ifdef CONFIG_PM +extern int s3c_irq_wake(struct irq_data *data, unsigned int state); +#else +#define s3c_irq_wake NULL +#endif + static const char name_exynos4210[] = "EXYNOS4210"; static const char name_exynos4212[] = "EXYNOS4212"; static const char name_exynos4412[] = "EXYNOS4412"; @@ -64,6 +70,8 @@ static void exynos4_init_clocks(int xtal); static void exynos5_init_clocks(int xtal); static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no); static int exynos_init(void); +static int exynos_init_irq_eint(struct device_node *np, + struct device_node *parent); static struct cpu_table cpu_ids[] __initdata = { { @@ -189,6 +197,11 @@ static struct map_desc exynos4_iodesc[] __initdata = { .length = SZ_64K, .type = MT_DEVICE, }, { + .virtual = (unsigned long)S5P_VA_AUDSS, + .pfn = __phys_to_pfn(EXYNOS4_PA_AUDSS), + .length = SZ_4K, + .type = MT_DEVICE, + }, { .virtual = (unsigned long)S3C_VA_USB_HSPHY, .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), .length = SZ_4K, @@ -603,6 +616,8 @@ static const struct of_device_id exynos4_dt_irq_match[] = { { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, { .compatible = "samsung,exynos4210-combiner", .data = combiner_of_init, }, + { .compatible = "samsung,exynos4210-wakeup-eint", + .data = exynos_init_irq_eint, }, {}, }; #endif @@ -620,8 +635,10 @@ void __init exynos4_init_irq(void) of_irq_init(exynos4_dt_irq_match); #endif - if (!of_have_populated_dt()) + if (!of_have_populated_dt()) { combiner_init(S5P_VA_COMBINER_BASE, NULL); + exynos_init_irq_eint(NULL, NULL); + } /* * The parameters of s5p_init_irq() are for VIC init. @@ -629,14 +646,38 @@ void __init exynos4_init_irq(void) * uses GIC instead of VIC. */ s5p_init_irq(NULL, 0); +#ifdef CONFIG_PM + irq_get_chip(IRQ_RTC_ALARM)->irq_set_wake = s3c_irq_wake; +#endif } void __init exynos5_init_irq(void) { + int irq; + struct device_node *np; + #ifdef CONFIG_OF of_irq_init(exynos4_dt_irq_match); #endif /* + * The Exynos5 wakeup interrupt controller has two-interrupt parents, + * gic and combiner. Hence, a interrupt nexus node is used to translate + * interrupt specifers for the interrupts which wakeup interrupt + * controller deliver to the gic and combiner. + * + * When using a interrupt nexus node (which is child node of the wakeup + * controller node), the interrupt parent of the wakeup controller node + * is set as the nexus node and the nexus node does not have a + * 'interrupt-controller' property. Hence, the of_irq_init function + * will not be able to invoke the intializer function for wakeup + * interrupt controller. So call the initiazer explicitly here. + */ + np = of_find_compatible_node(NULL, NULL, + "samsung,exynos5210-wakeup-eint"); + if (np) + exynos_init_irq_eint(np, NULL); + + /* * The parameters of s5p_init_irq() are for VIC init. * Theses parameters should be NULL and 0 because EXYNOS4 * uses GIC instead of VIC. @@ -742,6 +783,9 @@ static DEFINE_SPINLOCK(eint_lock); static unsigned int eint0_15_data[16]; +#define EXYNOS_EINT_NR 32 +static struct irq_domain *irq_domain; + static inline int exynos4_irq_to_gpio(unsigned int irq) { if (irq < IRQ_EINT(0)) @@ -832,9 +876,9 @@ static inline void exynos_irq_eint_mask(struct irq_data *data) u32 mask; spin_lock(&eint_lock); - mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq)); - mask |= EINT_OFFSET_BIT(data->irq); - __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq)); + mask = __raw_readl(EINT_MASK(exynos_eint_base, data->hwirq)); + mask |= EINT_OFFSET_BIT(data->hwirq); + __raw_writel(mask, EINT_MASK(exynos_eint_base, data->hwirq)); spin_unlock(&eint_lock); } @@ -843,16 +887,16 @@ static void exynos_irq_eint_unmask(struct irq_data *data) u32 mask; spin_lock(&eint_lock); - mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq)); - mask &= ~(EINT_OFFSET_BIT(data->irq)); - __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq)); + mask = __raw_readl(EINT_MASK(exynos_eint_base, data->hwirq)); + mask &= ~(EINT_OFFSET_BIT(data->hwirq)); + __raw_writel(mask, EINT_MASK(exynos_eint_base, data->hwirq)); spin_unlock(&eint_lock); } static inline void exynos_irq_eint_ack(struct irq_data *data) { - __raw_writel(EINT_OFFSET_BIT(data->irq), - EINT_PEND(exynos_eint_base, data->irq)); + __raw_writel(EINT_OFFSET_BIT(data->hwirq), + EINT_PEND(exynos_eint_base, data->hwirq)); } static void exynos_irq_eint_maskack(struct irq_data *data) @@ -863,7 +907,7 @@ static void exynos_irq_eint_maskack(struct irq_data *data) static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type) { - int offs = EINT_OFFSET(data->irq); + int offs = data->hwirq; int shift; u32 ctrl, mask; u32 newvalue = 0; @@ -898,10 +942,10 @@ static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type) mask = 0x7 << shift; spin_lock(&eint_lock); - ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq)); + ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->hwirq)); ctrl &= ~mask; ctrl |= newvalue << shift; - __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq)); + __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->hwirq)); spin_unlock(&eint_lock); if (soc_is_exynos5250()) @@ -945,7 +989,7 @@ static inline void exynos_irq_demux_eint(unsigned int start) while (status) { irq = fls(status) - 1; - generic_handle_irq(irq + start); + generic_handle_irq(irq_find_mapping(irq_domain, irq + start)); status &= ~(1 << irq); } } @@ -954,8 +998,8 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) { struct irq_chip *chip = irq_get_chip(irq); chained_irq_enter(chip, desc); - exynos_irq_demux_eint(IRQ_EINT(16)); - exynos_irq_demux_eint(IRQ_EINT(24)); + exynos_irq_demux_eint(16); + exynos_irq_demux_eint(24); chained_irq_exit(chip, desc); } @@ -963,6 +1007,7 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) { u32 *irq_data = irq_get_handler_data(irq); struct irq_chip *chip = irq_get_chip(irq); + int eint_irq; chained_irq_enter(chip, desc); chip->irq_mask(&desc->irq_data); @@ -970,50 +1015,94 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) if (chip->irq_ack) chip->irq_ack(&desc->irq_data); - generic_handle_irq(*irq_data); + eint_irq = irq_find_mapping(irq_domain, *irq_data); + generic_handle_irq(eint_irq); chip->irq_unmask(&desc->irq_data); chained_irq_exit(chip, desc); } -static int __init exynos_init_irq_eint(void) +static int exynos_eint_irq_domain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) { - int irq; + irq_set_chip_and_handler(irq, &exynos_irq_eint, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + return 0; +} - if (soc_is_exynos5250()) - exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K); - else - exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K); +static struct irq_domain_ops exynos_eint_irq_domain_ops = { + .map = exynos_eint_irq_domain_map, +}; + +static int __init exynos_init_irq_eint(struct device_node *np, + struct device_node *parent) +{ + int irq, *src_int, irq_base, irq_eint; + unsigned int paddr; + +#ifdef CONFIG_PINCTRL_SAMSUNG + /* + * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf + * functionality along with support for external gpio and wakeup + * interrupts. If the samsung pinctrl driver is enabled and includes + * the wakeup interrupt support, then the setting up external wakeup + * interrupts here can be skipped. This check here is temporary to + * allow exynos4 platforms that do not use Samsung pinctrl driver to + * co-exist with platforms that do. When all of the Samsung Exynos4 + * platforms switch over to using the pinctrl driver, the wakeup + * interrupt support code here can be completely removed. + */ + struct device_node *pctrl_np, *wkup_np; + const char *pctrl_compat = "samsung,pinctrl-exynos4210"; + const char *wkup_compat = "samsung,exynos4210-wakeup-eint"; + + for_each_compatible_node(pctrl_np, NULL, pctrl_compat) { + if (of_device_is_available(pctrl_np)) { + wkup_np = of_find_compatible_node(pctrl_np, NULL, + wkup_compat); + if (wkup_np) + return -ENODEV; + } + } +#endif - if (exynos_eint_base == NULL) { + if (!np) { + paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 : + EXYNOS4_PA_GPIO2; + exynos_eint_base = ioremap(paddr, SZ_4K); + } else { + exynos_eint_base = of_iomap(np, 0); + } + if (!exynos_eint_base) { pr_err("unable to ioremap for EINT base address\n"); - return -ENOMEM; + return -ENXIO; } - for (irq = 0 ; irq <= 31 ; irq++) { - irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint, - handle_level_irq); - set_irq_flags(IRQ_EINT(irq), IRQF_VALID); + irq_base = irq_alloc_descs(IRQ_EINT(0), 1, EXYNOS_EINT_NR, 0); + if (IS_ERR_VALUE(irq_base)) { + irq_base = IRQ_EINT(0); + pr_warning("%s: irq desc alloc failed. Continuing with %d as " + "linux irq base\n", __func__, irq_base); } - irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31); - - for (irq = 0 ; irq <= 15 ; irq++) { - eint0_15_data[irq] = IRQ_EINT(irq); - - if (soc_is_exynos5250()) { - irq_set_handler_data(exynos5_eint0_15_src_int[irq], - &eint0_15_data[irq]); - irq_set_chained_handler(exynos5_eint0_15_src_int[irq], - exynos_irq_eint0_15); - } else { - irq_set_handler_data(exynos4_eint0_15_src_int[irq], - &eint0_15_data[irq]); - irq_set_chained_handler(exynos4_eint0_15_src_int[irq], - exynos_irq_eint0_15); - } + irq_domain = irq_domain_add_legacy(np, EXYNOS_EINT_NR, irq_base, 0, + &exynos_eint_irq_domain_ops, NULL); + if (WARN_ON(!irq_domain)) { + pr_warning("%s: irq domain init failed\n", __func__); + return 0; + } + + irq_eint = np ? irq_of_parse_and_map(np, 16) : EXYNOS_IRQ_EINT16_31; + irq_set_chained_handler(irq_eint, exynos_irq_demux_eint16_31); + + for (irq = 0 ; irq <= 15; irq++) { + eint0_15_data[irq] = irq; + src_int = soc_is_exynos5250() ? exynos5_eint0_15_src_int : + exynos4_eint0_15_src_int; + irq_eint = np ? irq_of_parse_and_map(np, irq) : src_int[irq]; + irq_set_handler_data(irq_eint, &eint0_15_data[irq]); + irq_set_chained_handler(irq_eint, exynos_irq_eint0_15); } return 0; } -arch_initcall(exynos_init_irq_eint); diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c index 3538532265e..5ed7da5ded4 100644 --- a/arch/arm/mach-exynos/dma.c +++ b/arch/arm/mach-exynos/dma.c @@ -303,10 +303,12 @@ static int __init exynos_dma_init(void) dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask); dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask); + dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask); amba_device_register(&exynos_pdma0_device, &iomem_resource); dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask); dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask); + dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask); amba_device_register(&exynos_pdma1_device, &iomem_resource); dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask); diff --git a/arch/arm/mach-exynos/include/mach-exynos/asv.h b/arch/arm/mach-exynos/include/mach-exynos/asv.h new file mode 100644 index 00000000000..5b48b74811e --- /dev/null +++ b/arch/arm/mach-exynos/include/mach-exynos/asv.h @@ -0,0 +1,43 @@ +/* linux/arch/arm/mach-exynos/include/mach/asv.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS4 - Adaptive Support Voltage Header file + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_ASV_H +#define __ASM_ARCH_ASV_H __FILE__ + +#define JUDGE_TABLE_END NULL +#define EXYNOS4_LOOP_CNT 10 + +struct asv_judge_table { + unsigned int hpm_limit; /* HPM value to decide group of target */ + unsigned int ids_limit; /* IDS value to decide group of target */ +}; + +struct samsung_asv { + unsigned int pkg_id; /* fused value for chip */ + unsigned int ids_offset; /* ids_offset of chip */ + unsigned int ids_mask; /* ids_mask of chip */ + unsigned int hpm_result; /* hpm value of chip */ + unsigned int ids_result; /* ids value of chip */ + int (*check_vdd_arm)(void); /* check vdd_arm value, this function is selectable */ + int (*pre_clock_init)(void); /* clock init function to get hpm */ + int (*pre_clock_setup)(void); /* clock setup function to get hpm */ + /* specific get ids function */ + int (*get_ids)(struct samsung_asv *asv_info); + /* specific get hpm function */ + int (*get_hpm)(struct samsung_asv *asv_info); + /* store into some repository to send result of asv */ + int (*store_result)(struct samsung_asv *asv_info); +}; + +extern void exynos4210_asv_init(struct samsung_asv *asv_info); + +#endif /* __ASM_ARCH_ASV_H */ diff --git a/arch/arm/mach-exynos/include/mach-exynos/cpufreq.h b/arch/arm/mach-exynos/include/mach-exynos/cpufreq.h index 7517c3f417a..be80017eace 100644 --- a/arch/arm/mach-exynos/include/mach-exynos/cpufreq.h +++ b/arch/arm/mach-exynos/include/mach-exynos/cpufreq.h @@ -10,6 +10,8 @@ * published by the Free Software Foundation. */ +extern unsigned int exynos_result_of_asv; + enum cpufreq_level_index { L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, diff --git a/arch/arm/mach-exynos/include/mach-exynos/irqs.h b/arch/arm/mach-exynos/include/mach-exynos/irqs.h index 15beb1623b0..bb9f48e1221 100644 --- a/arch/arm/mach-exynos/include/mach-exynos/irqs.h +++ b/arch/arm/mach-exynos/include/mach-exynos/irqs.h @@ -461,6 +461,7 @@ #define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32) #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) #define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) +#define IRQ_TS (S5P_EINT_BASE1 + 25) /* Set the default NR_IRQS */ diff --git a/arch/arm/mach-exynos/include/mach-exynos/mali/config.h b/arch/arm/mach-exynos/include/mach-exynos/mali/config.h new file mode 100644 index 00000000000..ccd3cf7d245 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach-exynos/mali/config.h @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence. + * + * A copy of the licence is included with the program, and can also be obtained from Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ARCH_CONFIG_H__ +#define __ARCH_CONFIG_H__ + +/* Configuration for the EB platform with ZBT memory enabled */ +/*zepplin added 2010.08.17 for orion configuration*/ +#define MALI_BASE_ADDR 0x13000000 +#define GP_ADDR MALI_BASE_ADDR +#define L2_ADDR MALI_BASE_ADDR+0x1000 +#define PMU_ADDR MALI_BASE_ADDR+0x2000 +#define GP_MMU_ADDR MALI_BASE_ADDR+0x3000 +#define PP0_MMU_ADDR MALI_BASE_ADDR+0x4000 +#define PP1_MMU_ADDR MALI_BASE_ADDR+0x5000 +#define PP2_MMU_ADDR MALI_BASE_ADDR+0x6000 +#define PP3_MMU_ADDR MALI_BASE_ADDR+0x7000 +#define PP0_ADDR MALI_BASE_ADDR+0x8000 +#define PP1_ADDR MALI_BASE_ADDR+0xA000 +#define PP2_ADDR MALI_BASE_ADDR+0xC000 +#define PP3_ADDR MALI_BASE_ADDR+0xE000 + +/*for mmu and os memory*/ +#define MEM_BASE_ADDR 0x40000000 +#define MEM_TOTAL_SIZE 0x40000000 +#define MEM_MALI_OS_SIZE 0x18000000 + +/*for dedicated memory*/ +//#define MEM_MALI_BASE 0x58000000 +//#define MEM_MALI_SIZE 0x08000000 +#define MEM_MALI_SIZE CONFIG_MALI_MEM_SIZE*1024*1024 +#define MEM_MALI_BASE 0x60000000 - MEM_MALI_SIZE + +//#define S5P_IRQ(x) (x+32) +//#define IRQ_SPI(x) S5P_IRQ(x+32) +#define MAX_IRQ_IN_COMBINER 8 +//#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64)) +#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) + +#define IRQ_PPMMU0_3D COMBINER_IRQ(13, 0) +#define IRQ_PPMMU1_3D COMBINER_IRQ(13, 1) +#define IRQ_PPMMU2_3D COMBINER_IRQ(13, 2) +#define IRQ_PPMMU3_3D COMBINER_IRQ(13, 3) +#define IRQ_GPMMU_3D COMBINER_IRQ(13, 4) + +#define IRQ_PP0_3D COMBINER_IRQ(14, 0) +#define IRQ_PP1_3D COMBINER_IRQ(14, 1) +#define IRQ_PP2_3D COMBINER_IRQ(14, 2) +#define IRQ_PP3_3D COMBINER_IRQ(14, 3) +#define IRQ_GP_3D COMBINER_IRQ(14, 4) +#define IRQ_PMU_3D COMBINER_IRQ(14, 5) + +static _mali_osk_resource_t arch_configuration [] = +{ + { + .type = MALI400GP, + .description = "Mali-400 GP", + .base = GP_ADDR, + .irq = IRQ_GP_3D, + .mmu_id = 1 + }, + { + .type = MALI400PP, + .base = PP0_ADDR, + .irq = IRQ_PP0_3D, + .description = "Mali-400 PP 0", + .mmu_id = 2 + }, + { + .type = MALI400PP, + .base = PP1_ADDR, + .irq = IRQ_PP1_3D, + .description = "Mali-400 PP 1", + .mmu_id = 3 + }, + { + .type = MALI400PP, + .base = PP2_ADDR, + .irq = IRQ_PP2_3D, + .description = "Mali-400 PP 2", + .mmu_id = 4 + }, + { + .type = MALI400PP, + .base = PP3_ADDR, + .irq = IRQ_PP3_3D, + .description = "Mali-400 PP 3", + .mmu_id = 5 + }, +#if USING_MMU + { + .type = MMU, + .base = GP_MMU_ADDR, + .irq = IRQ_GPMMU_3D, + .description = "Mali-400 MMU for GP", + .mmu_id = 1 + }, + { + .type = MMU, + .base = PP0_MMU_ADDR, + .irq = IRQ_PPMMU0_3D, + .description = "Mali-400 MMU for PP 0", + .mmu_id = 2 + }, + { + .type = MMU, + .base = PP1_MMU_ADDR, + .irq = IRQ_PPMMU1_3D, + .description = "Mali-400 MMU for PP 1", + .mmu_id = 3 + }, + { + .type = MMU, + .base = PP2_MMU_ADDR, + .irq = IRQ_PPMMU2_3D, + .description = "Mali-400 MMU for PP 2", + .mmu_id = 4 + }, + { + .type = MMU, + .base = PP3_MMU_ADDR, + .irq = IRQ_PPMMU3_3D, + .description = "Mali-400 MMU for PP 3", + .mmu_id = 5 + }, +#if USING_OS_MEMORY + { + .type = OS_MEMORY, + .description = "System Memory", + .size = MEM_MALI_OS_SIZE, + .flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE | _MALI_GP_READABLE | _MALI_GP_WRITEABLE + }, +#endif +#if USING_DED /* Dedicated Memory */ + { + .type = MEMORY, + .description = "Dedicated Memory", + .base = MEM_MALI_BASE, + .size = MEM_MALI_SIZE, + .flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE | _MALI_GP_READABLE | _MALI_GP_WRITEABLE | _MALI_MMU_READABLE | _MALI_MMU_WRITEABLE + }, +#endif/* if USING_OS_MEMORY*/ + { + .type = MEM_VALIDATION, + .description = "memory validation", + .base = MEM_BASE_ADDR, + .size = MEM_TOTAL_SIZE, + .flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE | _MALI_GP_READABLE | _MALI_GP_WRITEABLE | _MALI_MMU_READABLE | _MALI_MMU_WRITEABLE + }, +#else /* Not using MMU */ + { + .type = MEMORY, + .description = "Dedicated Memory", + .base = MEM_MALI_BASE, + .size = MEM_MALI_SIZE, + .flags = _MALI_CPU_WRITEABLE | _MALI_CPU_READABLE | _MALI_PP_READABLE | _MALI_PP_WRITEABLE | _MALI_GP_READABLE | _MALI_GP_WRITEABLE | _MALI_MMU_READABLE | _MALI_MMU_WRITEABLE + }, +#endif + { + .type = MALI400L2, + .base = L2_ADDR, + .description = "Mali-400 L2 cache" + }, +}; + +#endif /* __ARCH_CONFIG_H__ */ diff --git a/arch/arm/mach-exynos/include/mach-exynos/map.h b/arch/arm/mach-exynos/include/mach-exynos/map.h index 9df5e30a69f..a79aade9070 100644 --- a/arch/arm/mach-exynos/include/mach-exynos/map.h +++ b/arch/arm/mach-exynos/include/mach-exynos/map.h @@ -39,6 +39,8 @@ #define EXYNOS4_PA_G2D 0x12800000 +#define EXYNOS4_PA_G3D 0x13000000 + #define EXYNOS4_PA_I2S0 0x03830000 #define EXYNOS4_PA_I2S1 0xE3100000 #define EXYNOS4_PA_I2S2 0xE2A00000 @@ -79,6 +81,8 @@ #define EXYNOS4_PA_COMBINER 0x10440000 #define EXYNOS5_PA_COMBINER 0x10440000 +#define EXYNOS4_PA_IEM 0x10460000 + #define EXYNOS4_PA_GIC_CPU 0x10480000 #define EXYNOS4_PA_GIC_DIST 0x10490000 #define EXYNOS5_PA_GIC_CPU 0x10482000 @@ -204,6 +208,8 @@ #define EXYNOS4_PA_ADC 0x13910000 #define EXYNOS4_PA_ADC1 0x13911000 +#define EXYNOS4_PA_AUDSS 0x03810000 + #define EXYNOS4_PA_AC97 0x139A0000 #define EXYNOS4_PA_SPDIF 0x139B0000 @@ -242,6 +248,7 @@ #define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 #define S5P_PA_JPEG EXYNOS4_PA_JPEG #define S5P_PA_G2D EXYNOS4_PA_G2D +#define S5P_PA_G3D EXYNOS4_PA_G3D #define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0 #define S5P_PA_HDMI EXYNOS4_PA_HDMI #define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY diff --git a/arch/arm/mach-exynos/include/mach-exynos/regs-audss.h b/arch/arm/mach-exynos/include/mach-exynos/regs-audss.h index ca5a8b64218..04494f0da4e 100644 --- a/arch/arm/mach-exynos/include/mach-exynos/regs-audss.h +++ b/arch/arm/mach-exynos/include/mach-exynos/regs-audss.h @@ -15,4 +15,12 @@ #define EXYNOS4_AUDSS_INT_MEM (0x03000000) +#define EXYNOS_AUDSSREG(x) (S5P_VA_AUDSS + (x)) + +#define EXYNOS4_CLKSRC_AUDSS EXYNOS_AUDSSREG(0x0) +#define EXYNOS4_CLKDIV_AUDSS EXYNOS_AUDSSREG(0x4) +#define EXYNOS4_CLKGATE_AUDSS EXYNOS_AUDSSREG(0x8) + +#define EXYNOS4_AUDSS_CLKGATE_I2SBUS (1<<2) + #endif /* _PLAT_REGS_AUDSS_H */ diff --git a/arch/arm/mach-exynos/include/mach-exynos/regs-clock.h b/arch/arm/mach-exynos/include/mach-exynos/regs-clock.h index 920939b68a5..17235d68ba4 100644 --- a/arch/arm/mach-exynos/include/mach-exynos/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach-exynos/regs-clock.h @@ -135,6 +135,24 @@ #define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800) #define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900) +#define EXYNOS4_APLL_CON0L8 EXYNOS_CLKREG(0x15100) +#define EXYNOS4_APLL_CON0L7 EXYNOS_CLKREG(0x15104) +#define EXYNOS4_APLL_CON0L6 EXYNOS_CLKREG(0x15108) +#define EXYNOS4_APLL_CON0L5 EXYNOS_CLKREG(0x1510C) +#define EXYNOS4_APLL_CON0L4 EXYNOS_CLKREG(0x15110) +#define EXYNOS4_APLL_CON0L3 EXYNOS_CLKREG(0x15114) +#define EXYNOS4_APLL_CON0L2 EXYNOS_CLKREG(0x15118) +#define EXYNOS4_APLL_CON0L1 EXYNOS_CLKREG(0x1511C) + +#define EXYNOS4_CLKDIV_IEM_L8 EXYNOS_CLKREG(0x15300) +#define EXYNOS4_CLKDIV_IEM_L7 EXYNOS_CLKREG(0x15304) +#define EXYNOS4_CLKDIV_IEM_L6 EXYNOS_CLKREG(0x15308) +#define EXYNOS4_CLKDIV_IEM_L5 EXYNOS_CLKREG(0x1530C) +#define EXYNOS4_CLKDIV_IEM_L4 EXYNOS_CLKREG(0x15310) +#define EXYNOS4_CLKDIV_IEM_L3 EXYNOS_CLKREG(0x15314) +#define EXYNOS4_CLKDIV_IEM_L2 EXYNOS_CLKREG(0x15318) +#define EXYNOS4_CLKDIV_IEM_L1 EXYNOS_CLKREG(0x1531C) + #define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800) #define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804) diff --git a/arch/arm/mach-exynos/include/mach-exynos/regs-gpio.h b/arch/arm/mach-exynos/include/mach-exynos/regs-gpio.h index 077ebfd55f6..31178953df1 100644 --- a/arch/arm/mach-exynos/include/mach-exynos/regs-gpio.h +++ b/arch/arm/mach-exynos/include/mach-exynos/regs-gpio.h @@ -16,13 +16,13 @@ #include <mach-exynos/map.h> #include <mach-exynos/irqs.h> -#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) +#define EINT_REG_NR(x) ((x) >> 3) #define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4)) #define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4)) #define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4)) #define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4)) -#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7)) +#define EINT_OFFSET_BIT(x) (1 << ((x) & 0x7)) /* compatibility for plat-s5p/irq-pm.c */ #define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00) diff --git a/arch/arm/mach-exynos/include/mach-exynos/regs-iem.h b/arch/arm/mach-exynos/include/mach-exynos/regs-iem.h new file mode 100644 index 00000000000..d9bf1777858 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach-exynos/regs-iem.h @@ -0,0 +1,27 @@ +/* linux/arch/arm/mach-exynos/include/mach/regs-iem.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS4 - IEM(INTELLIGENT ENERGY MANAGEMENT) register discription + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_IEM_H +#define __ASM_ARCH_REGS_IEM_H __FILE__ + +/* Register for IEC */ +#define EXYNOS4_IECDPCCR (0x00000) + +/* Register for APC */ +#define EXYNOS4_APC_CONTROL (0x10010) +#define EXYNOS4_APC_PREDLYSEL (0x10024) +#define EXYNOS4_APC_DBG_DLYCODE (0x100E0) + +#define APC_HPM_EN (1 << 4) +#define IEC_EN (1 << 0) + +#endif /* __ASM_ARCH_REGS_IEM_H */ diff --git a/arch/arm/mach-exynos/include/mach-exynos/ump/config.h b/arch/arm/mach-exynos/include/mach-exynos/ump/config.h new file mode 100644 index 00000000000..a82934f2799 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach-exynos/ump/config.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence. + * + * A copy of the licence is included with the program, and can also be obtained from Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ARCH_CONFIG_H__ +#define __ARCH_CONFIG_H__ + +#define ARCH_UMP_BACKEND_DEFAULT UMP_MEMORY_TYPE +#define ARCH_UMP_MEMORY_ADDRESS_DEFAULT 0 +#define ARCH_UMP_MEMORY_SIZE_DEFAULT CONFIG_UMP_MEM_SIZE * 1024UL * 1024UL + +#endif /* __ARCH_CONFIG_H__ */ diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index 0c4fc418da9..ea0bcc9f955 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -14,15 +14,55 @@ #include <linux/of_platform.h> #include <linux/serial_core.h> +#include <linux/pwm_backlight.h> +#include <plat/backlight.h> +#include <plat/gpio-cfg.h> +#include <linux/gpio.h> +#include <plat/regs-fb-v4.h> +#include <linux/fb.h> +#include <plat/fb.h> +#include <linux/lcd.h> +#include <plat/devs.h> +#include <linux/platform_data/s3c-hsotg.h> + #include <asm/mach/arch.h> #include <asm/hardware/gic.h> #include <mach-exynos/map.h> +#include <mach-exynos/ohci.h> #include <plat-samsung/cpu.h> #include <plat-samsung/regs-serial.h> +#include <plat-samsung/ehci.h> +#include <plat-samsung/usb-phy.h> #include "common.h" +static struct s5p_ehci_platdata origen_ehci_pdata = { + .phy_init = s5p_usb_phy_init, + .phy_exit = s5p_usb_phy_exit, +}; + +static struct exynos4_ohci_platdata origen_ohci_pdata = { + .phy_init = s5p_usb_phy_init, + .phy_exit = s5p_usb_phy_exit, +}; + +static struct s3c_hsotg_plat origen_hsotg_pdata = { + .phy_init = s5p_usb_phy_init, + .phy_exit = s5p_usb_phy_exit, +}; + +/* LCD Backlight data */ +static struct samsung_bl_gpio_info origen_bl_gpio_info = { + .no = EXYNOS4_GPD0(0), + .func = S3C_GPIO_SFN(2), +}; + +static struct platform_pwm_backlight_data origen_bl_data = { + .pwm_id = 0, + .pwm_period_ns = 1000, +}; + /* * The following lookup table is used to override device names when devices * are registered from device tree. This is temporarily added to enable @@ -55,6 +95,8 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { "exynos4-sdhci.3", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0), "s3c2440-i2c.0", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1), + "s3c2440-i2c.1", NULL), OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0, "exynos4210-spi.0", NULL), OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1, @@ -63,6 +105,17 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { "exynos4210-spi.2", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), + OF_DEV_AUXDATA("samsung,exynos-ehci", EXYNOS4_PA_EHCI, "s5p-ehci", + &origen_ehci_pdata), + OF_DEV_AUXDATA("samsung,exynos-ohci", EXYNOS4_PA_OHCI, "exynos-ohci", + &origen_ohci_pdata), + OF_DEV_AUXDATA("samsung,exynos-hsotg", EXYNOS4_PA_HSOTG, "s3c-hsotg", + &origen_hsotg_pdata), + OF_DEV_AUXDATA("samsung,exynos4210-fimd", EXYNOS4_PA_FIMD0, + "exynos4-fb.0", NULL), + OF_DEV_AUXDATA("samsung,samsung-i2s", EXYNOS4_PA_I2S0, + "samsung-i2s.0", NULL), + OF_DEV_AUXDATA("samsung,audio-dma", 0, "samsung-audio", NULL), {}, }; @@ -72,10 +125,21 @@ static void __init exynos4210_dt_map_io(void) s3c24xx_init_clocks(24000000); } +static void __init exynos4_setup_fimd(void) +{ + unsigned int reg; + + reg = __raw_readl(S3C_VA_SYS + 0x0210); + reg |= (1 << 1); + __raw_writel(reg, S3C_VA_SYS + 0x0210); +} + static void __init exynos4210_dt_machine_init(void) { of_platform_populate(NULL, of_default_bus_match_table, exynos4210_auxdata_lookup, NULL); + samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data); + exynos4_setup_fimd(); } static char const *exynos4210_dt_compat[] __initdata = { diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 55ae986ffe6..8704544d0c1 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -15,6 +15,7 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/input.h> +#include <linux/pwm.h> #include <linux/pwm_backlight.h> #include <linux/gpio_keys.h> #include <linux/i2c.h> @@ -23,12 +24,19 @@ #include <linux/lcd.h> #include <linux/rfkill-gpio.h> #include <linux/platform_data/s3c-hsotg.h> +#include <linux/ath6kl.h> +#include <linux/delay.h> +#include <linux/videodev2.h> + +#include <media/s5k4ecgx.h> +#include <media/s5p_fimc.h> +#include <media/v4l2-mediabus.h> #include <asm/mach/arch.h> #include <asm/hardware/gic.h> #include <asm/mach-types.h> -#include <video/platform_lcd.h> +#include <video/lcd_pwrctrl.h> #include <plat-samsung/regs-serial.h> #include <plat-samsung/regs-fb-v4.h> @@ -43,6 +51,7 @@ #include <plat-samsung/fb.h> #include <plat-samsung/mfc.h> #include <plat-samsung/hdmi.h> +#include <plat-samsung/camport.h> #include <mach-exynos/ohci.h> #include <mach-exynos/map.h> @@ -99,6 +108,8 @@ static struct regulator_consumer_supply __initdata ldo3_consumer[] = { REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */ REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */ REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */ + REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* OTG */ + REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* OTG */ }; static struct regulator_consumer_supply __initdata ldo6_consumer[] = { REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */ @@ -121,6 +132,7 @@ static struct regulator_consumer_supply __initdata ldo14_consumer[] = { }; static struct regulator_consumer_supply __initdata ldo17_consumer[] = { REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ + REGULATOR_SUPPLY("vmmc", NULL), }; static struct regulator_consumer_supply __initdata buck1_consumer[] = { REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */ @@ -132,7 +144,7 @@ static struct regulator_consumer_supply __initdata buck3_consumer[] = { REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */ }; static struct regulator_consumer_supply __initdata buck7_consumer[] = { - REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */ + REGULATOR_SUPPLY("vcc-lcd", "lcd-pwrctrl.0"), /* LCD */ }; static struct regulator_init_data __initdata max8997_ldo1_data = { @@ -166,6 +178,7 @@ static struct regulator_init_data __initdata max8997_ldo3_data = { .min_uV = 1100000, .max_uV = 1100000, .apply_uV = 1, + .always_on = 1, .valid_ops_mask = REGULATOR_CHANGE_STATUS, .state_mem = { .disabled = 1, @@ -209,6 +222,7 @@ static struct regulator_init_data __initdata max8997_ldo7_data = { .min_uV = 1800000, .max_uV = 1800000, .apply_uV = 1, + .always_on = 1, .valid_ops_mask = REGULATOR_CHANGE_STATUS, .state_mem = { .disabled = 1, @@ -268,6 +282,7 @@ static struct regulator_init_data __initdata max8997_ldo11_data = { .min_uV = 3000000, .max_uV = 3000000, .apply_uV = 1, + .always_on = 1, .valid_ops_mask = REGULATOR_CHANGE_STATUS, .state_mem = { .disabled = 1, @@ -358,7 +373,9 @@ static struct regulator_init_data __initdata max8997_buck3_data = { .constraints = { .name = "VDD_G3D_1.1V", .min_uV = 900000, - .max_uV = 1100000, + .max_uV = 1200000, + .always_on = 1, + .boot_on = 1, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, .state_mem = { @@ -387,7 +404,7 @@ static struct regulator_init_data __initdata max8997_buck7_data = { .name = "VDD_LCD_3.3V", .min_uV = 3300000, .max_uV = 3300000, - .boot_on = 1, + .boot_on = 0, .apply_uV = 1, .valid_ops_mask = REGULATOR_CHANGE_STATUS, .state_mem = { @@ -470,6 +487,19 @@ static struct i2c_board_info i2c0_devs[] __initdata = { .platform_data = &origen_max8997_pdata, .irq = IRQ_EINT(4), }, +#ifdef CONFIG_TOUCHSCREEN_UNIDISPLAY_TS + { + I2C_BOARD_INFO("unidisplay_ts", 0x41), + .irq = IRQ_TS, + }, +#endif +}; + +/* I2C1 */ +static struct i2c_board_info i2c1_devs[] __initdata = { + { + I2C_BOARD_INFO("alc5625", 0x1E), + }, }; static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = { @@ -480,6 +510,127 @@ static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { .cd_type = S3C_SDHCI_CD_INTERNAL, }; + +/* + * WLAN: SDIO Host will call this func at booting time + */ +static int origen_wifi_status_register(void (*notify_func) + (struct platform_device *, int state)); + +/* WLAN: MMC3-SDIO */ +static struct s3c_sdhci_platdata origen_hsmmc3_pdata __initdata = { + .max_width = 4, + .host_caps = MMC_CAP_4_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + .pm_caps = MMC_PM_KEEP_POWER, + .cd_type = S3C_SDHCI_CD_EXTERNAL, + .ext_cd_init = origen_wifi_status_register, +}; + +/* + * WLAN: Save SDIO Card detect func into this pointer + */ +static void (*wifi_status_cb)(struct platform_device *, int state); + +static int origen_wifi_status_register(void (*notify_func) + (struct platform_device *, int state)) +{ + /* Assign sdhci_s3c_notify_change to wifi_status_cb */ + if (!notify_func) + return -EAGAIN; + else + wifi_status_cb = notify_func; + + return 0; +} + +#define ORIGEN_WLAN_WOW EXYNOS4_GPX2(3) +#define ORIGEN_WLAN_RESET EXYNOS4_GPX2(4) + + +static void origen_wlan_setup_power(bool val) +{ + int err; + + if (val) { + err = gpio_request_one(ORIGEN_WLAN_RESET, + GPIOF_OUT_INIT_LOW, "GPX2_4"); + if (err) { + pr_warning("ORIGEN: Not obtain WIFI gpios\n"); + return; + } + s3c_gpio_cfgpin(ORIGEN_WLAN_RESET, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(ORIGEN_WLAN_RESET, + S3C_GPIO_PULL_NONE); + /* VDD33,I/O Supply must be done */ + gpio_set_value(ORIGEN_WLAN_RESET, 0); + udelay(30); /*Tb */ + gpio_direction_output(ORIGEN_WLAN_RESET, 1); + } else { + gpio_direction_output(ORIGEN_WLAN_RESET, 0); + gpio_free(ORIGEN_WLAN_RESET); + } + + mdelay(100); + + return; +} + +/* + * This will be called at init time of WLAN driver + */ +static int origen_wifi_set_detect(bool val) +{ + + if (!wifi_status_cb) { + pr_warning("ORIGEN: WLAN: No callback \n" + "ORIGEN: WLAN: MMC should boot earlier than net \n"); + + return -EAGAIN; + } + if (true == val) { + origen_wlan_setup_power(true); + wifi_status_cb(&s3c_device_hsmmc3, 1); + } else { + origen_wlan_setup_power(false); + wifi_status_cb(&s3c_device_hsmmc3, 0); + } + + return 0; +} + +struct ath6kl_platform_data origen_wlan_data __initdata = { + .setup_power = origen_wifi_set_detect, +}; + +#ifdef CONFIG_VIDEO_S5K4ECGX +static int origen_camera_power(int enable); +static struct s5k4ecgx_platform_data s5k4ecgx_plat = { + .set_power = origen_camera_power, +}; + +static struct i2c_board_info s5k4ecgx_board_info = { + I2C_BOARD_INFO("S5K4ECGX", 0x5A >> 1), + .platform_data = &s5k4ecgx_plat, +}; + +static struct s5p_fimc_isp_info s5k4ecgx_camera_sensors[] = { + { + .flags = V4L2_MBUS_PCLK_SAMPLE_RISING | + V4L2_MBUS_VSYNC_ACTIVE_LOW, + .bus_type = FIMC_ITU_601, + .board_info = &s5k4ecgx_board_info, + .clk_frequency = 24000000UL, + .i2c_bus_num = 0, + }, +}; + +static struct s5p_platform_fimc fimc_md_platdata = { + .isp_info = s5k4ecgx_camera_sensors, + .num_clients = ARRAY_SIZE(s5k4ecgx_camera_sensors), +}; +#endif + /* USB EHCI */ static struct s5p_ehci_platdata origen_ehci_pdata; @@ -587,33 +738,20 @@ static struct platform_device origen_device_gpiokeys = { }, }; -static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power) -{ - int ret; - - if (power) - ret = gpio_request_one(EXYNOS4_GPE3(4), - GPIOF_OUT_INIT_HIGH, "GPE3_4"); - else - ret = gpio_request_one(EXYNOS4_GPE3(4), - GPIOF_OUT_INIT_LOW, "GPE3_4"); - - gpio_free(EXYNOS4_GPE3(4)); - - if (ret) - pr_err("failed to request gpio for LCD power: %d\n", ret); -} - -static struct plat_lcd_data origen_lcd_hv070wsa_data = { - .set_power = lcd_hv070wsa_set_power, +static struct lcd_pwrctrl_data origen_lcd_hv070wsa_data = { + .gpio = EXYNOS4_GPE3(4), }; static struct platform_device origen_lcd_hv070wsa = { - .name = "platform-lcd", + .name = "lcd-pwrctrl", .dev.parent = &s5p_device_fimd0.dev, .dev.platform_data = &origen_lcd_hv070wsa_data, }; +static struct pwm_lookup origen_pwm_lookup[] = { + PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL), +}; + #ifdef CONFIG_DRM_EXYNOS static struct exynos_drm_fimd_pdata drm_fimd_pdata = { .panel = { @@ -639,7 +777,25 @@ static struct s3c_fb_pd_win origen_fb_win0 = { .xres = 1024, .yres = 600, .max_bpp = 32, - .default_bpp = 24, + .default_bpp = 32, + .virtual_x = 1024, + .virtual_y = 2 * 600, +}; + +static struct s3c_fb_pd_win origen_fb_win1 = { + .xres = 1024, + .yres = 600, + .max_bpp = 32, + .default_bpp = 32, + .virtual_x = 1024, + .virtual_y = 2 * 600, +}; + +static struct s3c_fb_pd_win origen_fb_win2 = { + .xres = 1024, + .yres = 600, + .max_bpp = 32, + .default_bpp = 32, .virtual_x = 1024, .virtual_y = 2 * 600, }; @@ -657,6 +813,8 @@ static struct fb_videomode origen_lcd_timing = { static struct s3c_fb_platdata origen_lcd_pdata __initdata = { .win[0] = &origen_fb_win0, + .win[1] = &origen_fb_win1, + .win[2] = &origen_fb_win2, .vtiming = &origen_lcd_timing, .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | @@ -682,10 +840,18 @@ static struct platform_device origen_device_bluetooth = { }, }; +/* Audio device */ +static struct platform_device origen_device_audio = { + .name = "origen-audio", + .id = -1, +}; + static struct platform_device *origen_devices[] __initdata = { &s3c_device_hsmmc2, &s3c_device_hsmmc0, + &s3c_device_hsmmc3, &s3c_device_i2c0, + &s3c_device_i2c1, &s3c_device_rtc, &s3c_device_usb_hsotg, &s3c_device_wdt, @@ -697,6 +863,7 @@ static struct platform_device *origen_devices[] __initdata = { &s5p_device_fimc_md, &s5p_device_fimd0, &s5p_device_g2d, + &s5p_device_g3d, &s5p_device_hdmi, &s5p_device_i2c_hdmiphy, &s5p_device_jpeg, @@ -704,6 +871,8 @@ static struct platform_device *origen_devices[] __initdata = { &s5p_device_mfc_l, &s5p_device_mfc_r, &s5p_device_mixer, + &samsung_asoc_dma, + &exynos4_device_i2s0, #ifdef CONFIG_DRM_EXYNOS &exynos_device_drm, #endif @@ -711,6 +880,7 @@ static struct platform_device *origen_devices[] __initdata = { &origen_device_gpiokeys, &origen_lcd_hv070wsa, &origen_leds_gpio, + &origen_device_audio, &origen_device_bluetooth, }; @@ -762,9 +932,64 @@ static void __init origen_power_init(void) s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE); } +#ifdef CONFIG_VIDEO_S5K4ECGX +#define ORIGEN_GPIO_CAM_RESET EXYNOS4_GPE1(4) +#define ORIGEN_GPIO_CAM_PWDN EXYNOS4_GPE1(0) +#define ORIGEN_GPIO_CAM_2V8 EXYNOS4_GPE1(1) +#define ORIGEN_GPIO_CAM_1V8 EXYNOS4_GPE1(2) +struct gpio cam_gpio[] = { + {ORIGEN_GPIO_CAM_RESET, GPIOF_DIR_OUT, "reset"}, + {ORIGEN_GPIO_CAM_PWDN, GPIOF_DIR_OUT, "power down"}, + {ORIGEN_GPIO_CAM_2V8, GPIOF_DIR_OUT, "2v8"}, + {ORIGEN_GPIO_CAM_1V8, GPIOF_DIR_OUT, "1v8"}, +}; + +static void __init origen_camera_init(void) +{ + int ret; + + ret = gpio_request_array(cam_gpio, + sizeof(cam_gpio) / sizeof(struct gpio)); + if (ret) { + pr_err("%s: Could not request the gpio for camera\n", __func__); + return; + } + + s3c_gpio_cfgpin(ORIGEN_GPIO_CAM_RESET, S3C_GPIO_OUTPUT); + s3c_gpio_cfgpin(ORIGEN_GPIO_CAM_PWDN, S3C_GPIO_OUTPUT); + s3c_gpio_cfgpin(ORIGEN_GPIO_CAM_2V8, S3C_GPIO_OUTPUT); + s3c_gpio_cfgpin(ORIGEN_GPIO_CAM_1V8, S3C_GPIO_OUTPUT); + + if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) { + pr_err("%s: Camera port A setup failed\n", __func__); + return; + } +} + +static int origen_camera_power(int enable) +{ + if (enable) { + gpio_set_value(ORIGEN_GPIO_CAM_2V8, 1); + gpio_set_value(ORIGEN_GPIO_CAM_1V8, 1); + udelay(10); + gpio_set_value(ORIGEN_GPIO_CAM_PWDN, 0); + udelay(15); + gpio_set_value(ORIGEN_GPIO_CAM_RESET, 1); + udelay(60); + } else { + gpio_set_value(ORIGEN_GPIO_CAM_RESET, 0); + udelay(50); + gpio_set_value(ORIGEN_GPIO_CAM_PWDN, 1); + gpio_set_value(ORIGEN_GPIO_CAM_2V8, 0); + gpio_set_value(ORIGEN_GPIO_CAM_1V8, 0); + } + return 0; +} +#endif + static void __init origen_reserve(void) { - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); + s5p_mfc_reserve_mem(0x43000000, 32 << 20, 0x51000000, 32 << 20); } static void __init origen_machine_init(void) @@ -774,12 +999,16 @@ static void __init origen_machine_init(void) s3c_i2c0_set_platdata(NULL); i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); + s3c_i2c1_set_platdata(NULL); + i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); + /* * Since sdhci instance 2 can contain a bootable media, * sdhci instance 0 is registered after instance 2. */ s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata); s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata); + s3c_sdhci3_set_platdata(&origen_hsmmc3_pdata); origen_ehci_init(); origen_ohci_init(); @@ -798,9 +1027,17 @@ static void __init origen_machine_init(void) platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); + pwm_add_table(origen_pwm_lookup, ARRAY_SIZE(origen_pwm_lookup)); samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data); origen_bt_setup(); + + ath6kl_set_platform_data(&origen_wlan_data); +#ifdef CONFIG_VIDEO_S5K4ECGX + s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata), + &s5p_device_fimc_md); + origen_camera_init(); +#endif } MACHINE_START(ORIGEN, "ORIGEN") diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index a9a1335d672..aed0dd84a7e 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -312,6 +312,9 @@ static void exynos_pm_resume(void) } early_wakeup: + /* Clear INFORM Register */ + __raw_writel(0, S5P_INFORM1); + return; } diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 3b3e6f6ed27..cfae825e933 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -191,6 +191,11 @@ static __init int exynos4_pm_init_power_domain(void) #ifdef CONFIG_S5P_DEV_G2D exynos_pm_add_dev_to_genpd(&s5p_device_g2d, &exynos4_pd_lcd0); #endif +#ifdef CONFIG_S5P_DEV_G3D + /* MALI requires the PD to be always on. */ + exynos4_pd_g3d.pd.power_off = NULL; + exynos_pm_add_dev_to_genpd(&s5p_device_g3d, &exynos4_pd_g3d); +#endif #ifdef CONFIG_S5P_DEV_JPEG exynos_pm_add_dev_to_genpd(&s5p_device_jpeg, &exynos4_pd_cam); #endif @@ -200,6 +205,7 @@ arch_initcall(exynos4_pm_init_power_domain); int __init exynos_pm_late_initcall(void) { - pm_genpd_poweroff_unused(); + if (!of_have_populated_dt()) + pm_genpd_poweroff_unused(); return 0; } diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 9c3b90c3538..9e7b40e2402 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -371,6 +371,11 @@ config S5P_DEV_G2D help Compile in platform device definitions for G2D device +config S5P_DEV_G3D + bool + help + Compile in platform device definitions for G3D device + config S5P_DEV_I2C_HDMIPHY bool help diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index a328736d16c..3803dc9e07f 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -144,6 +144,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) int clk_set_rate(struct clk *clk, unsigned long rate) { + unsigned long flags; int ret; if (IS_ERR(clk)) @@ -159,9 +160,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate) if (clk->ops == NULL || clk->ops->set_rate == NULL) return -EINVAL; - spin_lock(&clocks_lock); + spin_lock_irqsave(&clocks_lock, flags); ret = (clk->ops->set_rate)(clk, rate); - spin_unlock(&clocks_lock); + spin_unlock_irqrestore(&clocks_lock, flags); return ret; } @@ -173,17 +174,18 @@ struct clk *clk_get_parent(struct clk *clk) int clk_set_parent(struct clk *clk, struct clk *parent) { + unsigned long flags; int ret = 0; if (IS_ERR(clk)) return -EINVAL; - spin_lock(&clocks_lock); + spin_lock_irqsave(&clocks_lock, flags); if (clk->ops && clk->ops->set_parent) ret = (clk->ops->set_parent)(clk, parent); - spin_unlock(&clocks_lock); + spin_unlock_irqrestore(&clocks_lock, flags); return ret; } diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index de205e6fd9b..1f82fc23b0f 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -290,6 +290,25 @@ struct platform_device s5p_device_g2d = { }; #endif /* CONFIG_S5P_DEV_G2D */ +/* G3D */ + +#ifdef CONFIG_S5P_DEV_G3D +static struct resource s5p_g3d_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_G3D, SZ_256K), +}; + +struct platform_device s5p_device_g3d = { + .name = "s5p-g3d", + .id = 0, + .num_resources = ARRAY_SIZE(s5p_g3d_resource), + .resource = s5p_g3d_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; +#endif /* CONFIG_S5P_DEV_G3D */ + #ifdef CONFIG_S5P_DEV_JPEG static struct resource s5p_jpeg_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K), diff --git a/arch/arm/plat-samsung/include/plat-samsung/devs.h b/arch/arm/plat-samsung/include/plat-samsung/devs.h index 5da4b4f38f4..5037810463e 100644 --- a/arch/arm/plat-samsung/include/plat-samsung/devs.h +++ b/arch/arm/plat-samsung/include/plat-samsung/devs.h @@ -83,6 +83,7 @@ extern struct platform_device s5p_device_fimc3; extern struct platform_device s5p_device_fimc_md; extern struct platform_device s5p_device_jpeg; extern struct platform_device s5p_device_g2d; +extern struct platform_device s5p_device_g3d; extern struct platform_device s5p_device_fimd0; extern struct platform_device s5p_device_hdmi; extern struct platform_device s5p_device_i2c_hdmiphy; diff --git a/arch/arm/plat-samsung/include/plat-samsung/map-s5p.h b/arch/arm/plat-samsung/include/plat-samsung/map-s5p.h index 19398af7dbc..eba5574807a 100644 --- a/arch/arm/plat-samsung/include/plat-samsung/map-s5p.h +++ b/arch/arm/plat-samsung/include/plat-samsung/map-s5p.h @@ -40,6 +40,8 @@ #define S5P_VA_GIC_CPU S3C_ADDR(0x02810000) #define S5P_VA_GIC_DIST S3C_ADDR(0x02820000) +#define S5P_VA_AUDSS S3C_ADDR(0X02A00000) + #define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) #define VA_VIC0 VA_VIC(0) #define VA_VIC1 VA_VIC(1) diff --git a/arch/arm/plat-samsung/include/plat-samsung/regs-fb.h b/arch/arm/plat-samsung/include/plat-samsung/regs-fb.h index 9a78012d6f4..a053b9635ce 100644 --- a/arch/arm/plat-samsung/include/plat-samsung/regs-fb.h +++ b/arch/arm/plat-samsung/include/plat-samsung/regs-fb.h @@ -401,3 +401,17 @@ #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) +/* Blending control registers */ +#define S3C_WINCON_BLD_PIXEL (1 << 6) +#define S3C_WINCON_BLD_MASK (1 << 6) +#define S3C_WINCON_ALPHA1_SEL (1 << 1) +#define S3C_WINCON_ALPHA_SEL_MASK (1 << 1) +#define S3C_WINCON(x) (0x0020 + (x * 0x04)) +#define S3C_VIDOSD_C(x) (0x0048 + (x * 0x10)) +#define S3C_WINSHMAP (0x0034) +#define S3C_WINSHMAP_CH_ENABLE(x) (1 << (x)) +#define S3C_WINCON_BLD_PLANE (0 << 6) +#define S3C_WINCON_ALPHA0_SEL (0 << 1) +#define S3C_VIDOSD_ALPHA0_SHIFT (12) +#define S3C_VIDOSD_ALPHA1_SHIFT (0) + diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c index 0e6d7aca81b..6a42d70624d 100644 --- a/arch/arm/plat-samsung/s5p-dev-mfc.c +++ b/arch/arm/plat-samsung/s5p-dev-mfc.c @@ -12,6 +12,7 @@ #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/dma-contiguous.h> #include <linux/memblock.h> #include <linux/ioport.h> @@ -20,52 +21,14 @@ #include <plat-samsung/irqs.h> #include <plat-samsung/mfc.h> -struct s5p_mfc_reserved_mem { - phys_addr_t base; - unsigned long size; - struct device *dev; -}; - -static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata; - void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, phys_addr_t lbase, unsigned int lsize) { - int i; - - s5p_mfc_mem[0].dev = &s5p_device_mfc_r.dev; - s5p_mfc_mem[0].base = rbase; - s5p_mfc_mem[0].size = rsize; - - s5p_mfc_mem[1].dev = &s5p_device_mfc_l.dev; - s5p_mfc_mem[1].base = lbase; - s5p_mfc_mem[1].size = lsize; - - for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) { - struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i]; - if (memblock_remove(area->base, area->size)) { - printk(KERN_ERR "Failed to reserve memory for MFC device (%ld bytes at 0x%08lx)\n", - area->size, (unsigned long) area->base); - area->base = 0; - } - } -} - -static int __init s5p_mfc_memory_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) { - struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i]; - if (!area->base) - continue; + if (dma_declare_contiguous(&s5p_device_mfc_r.dev, rsize, rbase, 0)) + printk(KERN_ERR "Failed to reserve memory for MFC device (%u bytes at 0x%08lx)\n", + rsize, (unsigned long) rbase); - if (dma_declare_coherent_memory(area->dev, area->base, - area->base, area->size, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) - printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n", - area->size, (unsigned long) area->base); - } - return 0; + if (dma_declare_contiguous(&s5p_device_mfc_l.dev, lsize, lbase, 0)) + printk(KERN_ERR "Failed to reserve memory for MFC device (%u bytes at 0x%08lx)\n", + rsize, (unsigned long) rbase); } -device_initcall(s5p_mfc_memory_init); |