diff options
Diffstat (limited to 'ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c')
| -rw-r--r-- | ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c | 988 |
1 files changed, 631 insertions, 357 deletions
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c index 19afb0448..f539af960 100644 --- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c +++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f1xx_hal_can.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
@@ -27,12 +27,16 @@ (++) Connect and configure the involved CAN pins using the
following function HAL_GPIO_Init();
- (#) Initialise and configure the CAN using HAL_CAN_Init() function.
+ (#) Initialize and configure the CAN using HAL_CAN_Init() function.
(#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+
+ (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
(#) Receive a CAN frame using HAL_CAN_Receive() function.
+ (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+
*** Polling mode IO operation ***
=================================
[..]
@@ -73,7 +77,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,12 +106,7 @@ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
-
-#ifdef HAL_CAN_MODULE_ENABLED
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
- defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-
+
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
@@ -117,31 +116,34 @@ * @{
*/
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
-#define CAN_TIMEOUT_VALUE 10
-
-#define CAN_TI0R_STID_BIT_POSITION ((uint32_t)21) /* Position of LSB bits STID in register CAN_TI0R */
-#define CAN_TI0R_EXID_BIT_POSITION ((uint32_t) 3) /* Position of LSB bits EXID in register CAN_TI0R */
-#define CAN_TDL0R_DATA0_BIT_POSITION ((uint32_t) 0) /* Position of LSB bits DATA0 in register CAN_TDL0R */
-#define CAN_TDL0R_DATA1_BIT_POSITION ((uint32_t) 8) /* Position of LSB bits DATA1 in register CAN_TDL0R */
-#define CAN_TDL0R_DATA2_BIT_POSITION ((uint32_t)16) /* Position of LSB bits DATA2 in register CAN_TDL0R */
-#define CAN_TDL0R_DATA3_BIT_POSITION ((uint32_t)24) /* Position of LSB bits DATA3 in register CAN_TDL0R */
-
+#define CAN_TIMEOUT_VALUE 10U
/**
* @}
*/
-
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/* Exported functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
/** @defgroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
@@ -171,8 +173,8 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
{
uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
- uint32_t tickstart = 0;
- uint32_t tmp_mcr = 0;
+ uint32_t tickstart = 0U;
+ uint32_t tmp_mcr = 0U;
/* Check CAN handle */
if(hcan == NULL)
@@ -220,10 +222,8 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
-
/* Process unlocked */
__HAL_UNLOCK(hcan);
-
return HAL_TIMEOUT;
}
}
@@ -236,36 +236,58 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) {
SET_BIT(tmp_mcr, CAN_MCR_TTCM);
}
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_TTCM);
+ }
/* Set the automatic bus-off management */
if (hcan->Init.ABOM == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_ABOM);
}
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_ABOM);
+ }
/* Set the automatic wake-up mode */
if (hcan->Init.AWUM == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_AWUM);
}
-
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_AWUM);
+ }
/* Set the no automatic retransmission */
if (hcan->Init.NART == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_NART);
}
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_NART);
+ }
/* Set the receive FIFO locked mode */
if (hcan->Init.RFLM == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_RFLM);
}
-
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_RFLM);
+ }
/* Set the transmit FIFO priority */
if (hcan->Init.TXFP == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_TXFP);
}
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_TXFP);
+ }
/* Update register MCR */
MODIFY_REG(hcan->Instance->MCR,
@@ -282,7 +304,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) hcan->Init.SJW |
hcan->Init.BS1 |
hcan->Init.BS2 |
- (hcan->Init.Prescaler - 1) ));
+ (hcan->Init.Prescaler - 1U)));
/* Request leave initialisation */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
@@ -291,7 +313,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) tickstart = HAL_GetTick();
/* Wait the acknowledge */
- while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
+ while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
{
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
@@ -305,7 +327,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) }
/* Check acknowledged */
- if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
+ if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
{
status = CAN_INITSTATUS_SUCCESS;
}
@@ -326,7 +348,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) {
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
-
+
/* Return function status */
return HAL_ERROR;
}
@@ -343,8 +365,11 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) */
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
{
- uint32_t filternbrbitpos = 0;
+ uint32_t filternbrbitpos = 0U;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
/* Check the parameters */
assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
@@ -353,18 +378,18 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
- filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
+ filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
/* Initialisation mode for the filter */
/* Select the start slave bank */
MODIFY_REG(hcan->Instance->FMR ,
CAN_FMR_CAN2SB ,
CAN_FMR_FINIT |
- (uint32_t)(sFilterConfig->BankNumber << 8) );
-
+ (uint32_t)(sFilterConfig->BankNumber << 8U) );
+
/* Filter Deactivation */
CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
-
+
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
{
@@ -374,14 +399,14 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy /* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
@@ -390,12 +415,12 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
/* 32-bit identifier or First 32-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
/* 32-bit mask or Second 32-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
}
/* Filter Mode */
@@ -503,8 +528,8 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) */
/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
- * @brief I/O operation functions
- *
+ * @brief I/O operation functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -529,127 +554,133 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
/* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- }
-
- /* Select one empty transmit mailbox */
- if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
- {
- transmitmailbox = 0;
- }
- else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
- {
- transmitmailbox = 1;
- }
- else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2))
- {
- transmitmailbox = 2;
- }
- else
- {
- transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
- }
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Select one empty transmit mailbox */
+ if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
- if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
- {
/* Set up the Id */
hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
if (hcan->pTxMsg->IDE == CAN_ID_STD)
{
assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_BIT_POSITION) |
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) |
hcan->pTxMsg->RTR);
}
else
{
assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_BIT_POSITION) |
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) |
hcan->pTxMsg->IDE |
hcan->pTxMsg->RTR);
}
-
+
/* Set up the DLC */
hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_BIT_POSITION) );
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_BIT_POSITION) );
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Check End of transmission flag */
while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
-
+
+ /* Cancel transmission */
+ __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
-
return HAL_TIMEOUT;
}
}
}
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- }
- else
+ /* Change CAN state */
+ switch(hcan->State)
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
-
+
/* Return function status */
return HAL_OK;
}
else
{
/* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ hcan->State = HAL_CAN_STATE_ERROR;
/* Return function status */
return HAL_ERROR;
@@ -671,7 +702,9 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
- if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX))
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
/* Process Locked */
__HAL_LOCK(hcan);
@@ -679,94 +712,97 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) /* Select one empty transmit mailbox */
if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
{
- transmitmailbox = 0;
+ transmitmailbox = CAN_TXMAILBOX_0;
}
else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
{
- transmitmailbox = 1;
+ transmitmailbox = CAN_TXMAILBOX_1;
}
- else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2))
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
{
- transmitmailbox = 2;
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
+ hcan->pTxMsg->RTR);
}
else
{
- transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
+ hcan->pTxMsg->IDE |
+ hcan->pTxMsg->RTR);
}
- if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3U] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[2U] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[1U] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[0U] << CAN_TDL0R_DATA0_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7U] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[6U] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[5U] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[4U] << CAN_TDL0R_DATA0_Pos));
+
+ /* Change CAN state */
+ switch(hcan->State)
{
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if (hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_BIT_POSITION) |
- hcan->pTxMsg->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_BIT_POSITION) |
- hcan->pTxMsg->IDE |
- hcan->pTxMsg->RTR);
- }
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
- /* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_BIT_POSITION) );
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_BIT_POSITION) );
-
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- }
-
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Enable interrupts: */
- /* - Enable Error warning Interrupt */
- /* - Enable Error passive Interrupt */
- /* - Enable Bus-off Interrupt */
- /* - Enable Last error code Interrupt */
- /* - Enable Error Interrupt */
- /* - Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME );
-
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
}
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME );
}
else
{
- return HAL_BUSY;
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
}
-
+
return HAL_OK;
}
@@ -777,75 +813,129 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) * @param FIFONumber: FIFO Number value
* @param Timeout: Specify Timeout value
* @retval HAL status
- * @retval None
*/
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
+ uint32_t tickstart = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
-
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
/* Process locked */
__HAL_LOCK(hcan);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
}
- else
+ else /* FIFONumber == CAN_FIFO1 */
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
}
-
/* Get tick */
tickstart = HAL_GetTick();
/* Check pending message */
- while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
-
/* Process unlocked */
__HAL_UNLOCK(hcan);
-
return HAL_TIMEOUT;
}
}
}
-
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
/* Get the Id */
- hcan->pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (hcan->pRxMsg->IDE == CAN_ID_STD)
+ pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
{
- hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
}
else
{
- hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
}
- hcan->pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
- hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
/* Get the FMI */
- hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
/* Get the data field */
- hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
- hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
- hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
- hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
- hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
- hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
/* Release the FIFO */
if(FIFONumber == CAN_FIFO0)
@@ -859,17 +949,44 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
}
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
}
- else
+ else /* FIFONumber == CAN_FIFO1 */
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
@@ -883,66 +1000,102 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u * the configuration information for the specified CAN.
* @param FIFONumber: Specify the FIFO number
* @retval HAL status
- * @retval None
*/
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
- if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
- /* Process locked */
- __HAL_LOCK(hcan);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
- }
-
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Enable interrupts: */
- /* - Enable Error warning Interrupt */
- /* - Enable Error passive Interrupt */
- /* - Enable Bus-off Interrupt */
- /* - Enable Last error code Interrupt */
- /* - Enable Error Interrupt */
- /* - Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME );
+ return HAL_BUSY;
+ }
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
- if(FIFONumber == CAN_FIFO0)
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
{
- /* Enable FIFO 0 message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
}
- else
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
{
- /* Enable FIFO 1 message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
}
-
+ }
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME );
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Enable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
}
else
{
- return HAL_BUSY;
+ /* Enable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
}
-
+
/* Return function status */
return HAL_OK;
}
@@ -955,7 +1108,7 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber */
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Process locked */
__HAL_LOCK(hcan);
@@ -967,7 +1120,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) MODIFY_REG(hcan->Instance->MCR,
CAN_MCR_INRQ ,
CAN_MCR_SLEEP );
-
+
/* Sleep mode status */
if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
@@ -979,20 +1132,20 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) return HAL_ERROR;
}
- /* Get tick */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
- HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
{
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
-
+
return HAL_TIMEOUT;
}
}
@@ -1016,7 +1169,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) */
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Process locked */
__HAL_LOCK(hcan);
@@ -1036,10 +1189,8 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
-
/* Process unlocked */
__HAL_UNLOCK(hcan);
-
return HAL_TIMEOUT;
}
}
@@ -1070,70 +1221,125 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) */
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+
+ /* Check Overrun flag for FIFO0 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Set CAN error code to FOV0 error */
+ errorcode |= HAL_CAN_ERROR_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+
+ /* Check Overrun flag for FIFO1 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Set CAN error code to FOV1 error */
+ errorcode |= HAL_CAN_ERROR_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+
/* Check End of transmission flag */
if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
{
- if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
- (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
- (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
+ /* Check Transmit request completion status */
+ tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
+ tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
+ tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
+ if(tmp1 || tmp2 || tmp3)
{
- /* Call transmit function */
- CAN_Transmit_IT(hcan);
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
+ tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
+ tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
+ /* Check Transmit success */
+ if((tmp1) || (tmp2) || (tmp3))
+ {
+ /* Call transmit function */
+ CAN_Transmit_IT(hcan);
+ }
+ else /* Transmit failure */
+ {
+ /* Set CAN error code to TXFAIL error */
+ errorcode |= HAL_CAN_ERROR_TXFAIL;
+ }
+
+ /* Clear transmission status flags (RQCPx and TXOKx) */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
+ CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
}
}
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
/* Check End of reception flag for FIFO0 */
- if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
- (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
+ if((tmp1 != 0U) && tmp2)
{
/* Call receive function */
CAN_Receive_IT(hcan, CAN_FIFO0);
}
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
/* Check End of reception flag for FIFO1 */
- if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
- (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
+ if((tmp1 != 0U) && tmp2)
{
/* Call receive function */
CAN_Receive_IT(hcan, CAN_FIFO1);
}
-
+
+ /* Set error code in handle */
+ hcan->ErrorCode |= errorcode;
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
/* Check Error Warning Flag */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ if(tmp1 && tmp2 && tmp3)
{
/* Set CAN error code to EWG error */
hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
/* No need for clear of Error Warning Flag as read-only */
}
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
/* Check Error Passive Flag */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ if(tmp1 && tmp2 && tmp3)
{
/* Set CAN error code to EPV error */
hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
/* No need for clear of Error Passive Flag as read-only */
}
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
/* Check Bus-Off Flag */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ if(tmp1 && tmp2 && tmp3)
{
/* Set CAN error code to BOF error */
hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
/* No need for clear of Bus-Off Flag as read-only */
}
+ tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
/* Check Last error code Flag */
- if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ if((!tmp1) && tmp2 && tmp3)
{
- switch(hcan->Instance->ESR & CAN_ESR_LEC)
+ tmp1 = (hcan->Instance->ESR & CAN_ESR_LEC);
+ switch(tmp1)
{
case(CAN_ESR_LEC_0):
/* Set CAN error code to STF error */
@@ -1166,15 +1372,37 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /* Clear Last error code Flag */
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
}
-
+
/* Call the Error call Back in case of Errors */
if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
{
/* Clear ERRI Flag */
- hcan->Instance->MSR |= CAN_MSR_ERRI;
+ hcan->Instance->MSR = CAN_MSR_ERRI;
/* Set the CAN state ready to be able to start again the process */
hcan->State = HAL_CAN_STATE_READY;
-
+
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ /* - Disable FIFO 0 message pending Interrupt */
+ /* - Disable FIFO 0 Overrun Interrupt */
+ /* - Disable FIFO 1 message pending Interrupt */
+ /* - Disable FIFO 1 Overrun Interrupt */
+ /* - Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_FMP0|
+ CAN_IT_FOV0|
+ CAN_IT_FMP1|
+ CAN_IT_FOV1|
+ CAN_IT_TME );
+
/* Call Error callback function */
HAL_CAN_ErrorCallback(hcan);
}
@@ -1230,8 +1458,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) */
/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- *
+ * @brief CAN Peripheral State functions
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@@ -1276,9 +1504,9 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) * @}
*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
- * @{
- */
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
/**
* @brief Initiates and transmits a CAN frame message.
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
@@ -1302,20 +1530,26 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
- CAN_IT_ERR );
- }
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
+ CAN_IT_ERR);
}
- else
+
+ /* Change CAN state */
+ switch(hcan->State)
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
}
-
+
/* Transmission complete callback */
HAL_CAN_TxCpltCallback(hcan);
@@ -1332,50 +1566,66 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) */
static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
+ uint32_t tmp1 = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
/* Get the Id */
- hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (hcan->pRxMsg->IDE == CAN_ID_STD)
+ pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
{
- hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
}
else
{
- hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
}
- hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
- hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
/* Get the FMI */
- hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
/* Get the data field */
- hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
- hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
- hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
- hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
- hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
- hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
/* Release the FIFO */
/* Release FIFO0 */
if (FIFONumber == CAN_FIFO0)
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
- /* Disable FIFO 0 message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
+ /* Disable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
}
/* Release FIFO1 */
else /* FIFONumber == CAN_FIFO1 */
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
- /* Disable FIFO 1 message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
+ /* Disable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
}
-
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+
+ tmp1 = hcan->State;
+ if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
{
/* Disable interrupts: */
/* - Disable Error warning Interrupt */
@@ -1387,18 +1637,45 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
- CAN_IT_ERR );
+ CAN_IT_ERR);
}
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
{
- /* Disable CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
}
- else
+ else /* FIFONumber == CAN_FIFO1 */
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
}
/* Receive complete callback */
@@ -1409,17 +1686,14 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum }
/**
- * @}
- */
-
-/**
* @}
*/
-
-#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */
- /* STM32F103xG) || STM32F105xC || STM32F107xC */
+#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
#endif /* HAL_CAN_MODULE_ENABLED */
+/**
+ * @}
+ */
/**
* @}
|