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path: root/drivers/spi
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2016-02-24spi: Remove default value from platform-specific optionsAndre Guedes
This patch removes the default value from some platform/SoC specific options which are declared in drivers/spi/Kconfig because 1) most of the time they are not valid values and 2) the correct values are already set in the SoC Kconfig. It also moves the interrupt priority definition from the driver's Kconfig to the platform's Kconfig since it is a platform-specific configuration. Change-Id: Ic992749b3210ed8a2e454edece41ceca5edbaf2e Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20spi: dw: Quark SE Sensor Sub-System supportTomasz Bursztyka
Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-20spi: Enable QMSI driver for Quark D2000Andre Guedes
This patch fixes the QMSI SPI shim driver so we are able to use it in Quark D2000 based platforms. The only change required to enable this driver is an #if guard in spi_qmsi_init() because the macro QM_SPI_MST_1 and the function qm_spi_master_1_isr are not defined in QMSI headers from Quark D2000. Since this drivers is now properly working on Quark D2000, this patch also sets the QMSI driver default options in arch/x86/soc/quark_d2000/ Kconfig. Change-Id: Ic6e2f7f5a2c3f350ddf360b23ffab6b812948572 Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-11spi : moving to a single SPI namingDan Kalowsky
Currently we have devices named "dw_spi_0" and "intel_spi_0" etc, which makes it difficult for an application to look up. Or worse, forcing a 3rd party IP to hardcode in support for only one specific IP block. Change-Id: Ie485e2350b171b66b22cd7ab39e0fcd196f38af8 Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-10struct packingDan Kalowsky
Looking at all structs as to where we can pack them a little better, and calling out the padding/stride at the end for future expansion. Change-Id: I4a651092e950dd3d915af9fa0ee0d7d59803e58f Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-08spi: dw: Improve debug outputTomasz Bursztyka
Available only when CONFIG_SPI_DEBUG is set: - Print out all exported functions with relevant infos - Remove superfluous messages - Make counter in push/pull not being instanciated when not debugging Change-Id: Iaa96a897008d360a14bc83da54152c264f42c60d Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-08spi: dw: If an error occurs, nothing should prevent to stopTomasz Bursztyka
It's a bug that did not happen, but is a valid one: if there is an error, we should not care at all about current stage of transmission, thus it will stop right away. Change-Id: Iec2b519d8118233f570ded18d6c6eb4084371e5b Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: qmsi: Fix enabling the CS line too lateVinicius Costa Gomes
There are situations when the transfer starts before we have the time to enable the CS line, so to be sure, we active it before even attempting to start the transfer. This fixes an CC2520 driver initialization issue using the QMSI SPI driver. Change-Id: Ib9b324b77260ac537f714376c8056b1543e7e3b3 Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-02-05spi: qmsi: Add support for selecting the driver's init priorityVinicius Costa Gomes
Because of the necessity of using a GPIO pin as Chip Select, we need to set the initialization priority of the SPI driver so it occurs after the GPIO driver. Change-Id: I02d675d8267ee07b267155a3806be85fbf57378c Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-02-05spi: qmsi: Add support for using a GPIO pin as CSVinicius Costa Gomes
There are cases that it is needed to use a GPIO pin as chip select (frames would be too long, for example), so using a GPIO pin as chip select to keep the line active while the transfer is ongoing is the usual solution. This implements that solution for the QMSI shim driver. Change-Id: Ia6b8f0f17161e20f87ad3def1468fe0abea65fdc Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-02-05spi: Add QMSI-based implementationVinicius Costa Gomes
This driver uses the QMSI library and mostly translates calls from the Zephyr API to QMSI ones. This driver conflicts with the native driver implemenation. In order to enable it, you must set: CONFIG_QMSI_DRIVERS=y CONFIG_QMSI_INSTALL_PATH="PATH_TO_QMSI" CONFIG_SPI_QMSI=y CONFIG_SPI_QMSI_PORT_0=y CONFIG_SPI_QMSI_PORT_1=y Missing: - Support for using a GPIO pin as Chip Select; Change-Id: I0d8eca88a2a803b6b3604f396f874313fe90753c Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-02-05irq: rename irq_connect() to IRQ_CONNECT()Andrew Boie
It's not a function and requires all its arguments to be build-time constants. Make this more obvious to the end user to ease confusion. Change-Id: I64107cf4d9db9f0e853026ce78e477060570fe6f Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05device: use DEVICE_INIT everwhereBenjamin Walsh
This is the last step before obsoleting DEVICE_DEFINE() and DEVICE_INIT_CONFIG_DEFINE(). Change-Id: Ica4257662969048083ab9839872b4b437b8b351b Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05device: rename SYS_GET_DEVICE_NAME/SYS_GET_DEVICEBenjamin Walsh
Rename them to DEVICE_NAME_GET and DEVICE_GET to fit in the 'device' namespace. Change-Id: I407a7f284ed4d1c071961b46615eea859c2e825f Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05device: rename SYS_DEFINE_DEVICE()Benjamin Walsh
Rename it to DEVICE_DEFINE() so that it fits in the 'device' namespace. Change-Id: I3af3a39cf9154359b31d22729d0db9f710cd202b Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05device: rename DECLARE_DEVICE_INIT_CONFIG()Benjamin Walsh
Rename it to DEVICE_INIT_CONFIG_DEFINE(), because (a) it was not fitting in any namespace and (b) it is not used to declare, but rather define a object. Change-Id: I1da5822f06b85a9fb024b5b184afd0ccc01012ec Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05device: rename synchronous_call_ APIsBenjamin Walsh
Rename them to device_sync_ to fit in the device_ namespace. Change-Id: I1088dda958584ed90b97137298050fee44c20ee4 Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05spi: dw: Fix Tx and Rx threshold after each push/pullTomasz Bursztyka
Reading: As when setting up the transfer, Rx has to adapt to current left Tx lenght. Writing: If nothing will be transmitted anymore, downsizing the level to 0. This fixes a hanging issue while making the controller being busy for nothing. Another hack found to fix the same issue was to test the SR Busy flag bit in the ISR handler. As the threshold level makes more sense, kepping this one. Change-Id: I87ba393d507c9418295f188d866d9979f423536c Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05c++: Add extern "C" { } block to header filesPeter Mitsis
Adds extern "C" { } blocks to header files so that they can be safely used by C++ source files. Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05spi: dw: Rework the logic on testing/setting controller's readynessTomasz Bursztyka
Controller should not be enabled while configuring or setting up a transfer call. It's enabled once the transfer call is ready to proceed, and disabled once the last interrupt has be raised. Change-Id: Ib9125a3600971b57e642730682f2b3bfb91b1e02 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: dw: Add an initialization priority Kconfig optionTomasz Bursztyka
On Quark SE, SPI might require GPIO to be ready before hand, to emulate CS, thus providing an option to tweak the intialization priority for SPI DW driver. Change-Id: Ifa373948ac8227bf6e4ed1113bcb4dc9139b6663 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: dw: Add Kconfig option to emulate CS through a GPIO pinTomasz Bursztyka
It might be necessary to emulate CS through a GPIO pin depending on these 2 conditions: - the controller's CS pin is not wired, and thus a GPIO pin is the only option - The controller is unstable at a certain frequency and cannot set/unset CS reliably. This is actually a possible issue on DesignWare's SPI controller in Quark SE or Quarks D2000 where it has been found unstable at 1Mhz and above. Change-Id: Ib6a06577906c005ddd347070d476a367a9c3da8a Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: dw: Fix how internal FIFO is handledTomasz Bursztyka
- Refine how DFS is calulated now that it is strictely used to manipulate buffer lengths. - Fix threshold limit - Tune RX threshold relevantly (reduce it if rx_len is lower than actual) - Don't push more than available left space in FIFO - Tune the private structure to lower memory space occupation Change-Id: I65b1b48b996b2104cebcb24cc366fb4dcbf7d53b Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: Rework constants for better identificationTomasz Bursztyka
IMR and ISR bits are same, but it stil better to differentiate them properly. Also fixing naming where all ISR ends with an 'S'. Change-Id: I2fc1e1d8d2743c3d98f5da40a5f4720a85c4f9a7 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: dw: Add support for auxiliariy registers based accessTomasz Bursztyka
On ARC, the SPI IP block might be accessible only via user extended auxiliary registers, which requires different instructions to read from and write to. Change-Id: I3aa5f223938a9aed7795de4aedc64bd529d62942 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05spi: dw: Differentiate ARC to other arch supportTomasz Bursztyka
Registers offsets are hopefully all the same, but size differs. On x86, thus 32bits support, CTRL0 or DR for instance are 32 bits r/w. And DFS on 32 bits support is placed differently as well. Change-Id: I5115d5c3c9bba71ece4a6f4a1d3d2fdc203c8da1 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: dw:support all frame sizesRamesh Thomas
Only 8 bit frames were supported. Added support for bigger data frames which can go up to 32 bits (on 32bits version of the controller, 16 bits otherwise). Store the frame size in bytes during configure, and use it during pull/push to read/write correct frame size. Change-Id: Iae8c55442e0a205403aa3febd1811b36aaf4c5b6 Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com> Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: Make sure option are generated according to their dependenciesTomasz Bursztyka
If SPI_INTEL is not requested, no need to instanciate specific value. Change-Id: I5f41d919e258e420f2bd099db88ed2259f9cd27e Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: Rename files according to rulesTomasz Bursztyka
Renaming files as: <domain>_<model or manufacturer>.<c/h> Change-Id: I018f6fdb4ba8aac8bb96e848f0f3633bd032b44e Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com> Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05spi: dw: Fix build issueTomasz Bursztyka
Introduced by commit 01d6f9f5ee0867f6ee8dc1506c2ebe62d9f296bb Reported by Gustavo Lima Chaves Change-Id: Ic29c33f4339c83a55ca45e93000cbc07b8dadbd2 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: dw: Fix build errorTomasz Bursztyka
Introduced by commit a6873a00d816daf303b0380dda91accd28df6497 Reordering the irq config function, and removing useless parameter. Change-Id: I2d22cfe81153b104044d8672dd57115138437ed9 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: Make the API fully synchronousTomasz Bursztyka
The driver has to implement the logic in an interrupt based manner. Applying the changes to the existing drivers. Changing ADC's API and implementation as well to follow those changes. Change-Id: Ie0c3e3e318f619ade6be935adb064a25446cc29c Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05interrupts: new static IRQ APIAndrew Boie
The interrupt API has been redesigned: - irq_connect() for dynamic interrupts renamed to irq_connect_dynamic(). It will be used in situations where the new static irq_connect() won't work, i.e. the value of arguments can't be computed at build time - a new API for static interrupts replaces irq_connect(). it is used exactly the same way as its dynamic counterpart. The old static irq macros will be removed - Separate stub assembly files are no longer needed as the stubs are now generated inline with irq_connect() ReST documentation updated for the changed API. Some detail about the IDT in ROM added, and an oblique reference to the internal-only _irq_handler_set() API removed; we don't talk about internal APIs in the official documentation. Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05drivers: pci: struct pci_dev_info rename classJavier B Perez Hernandez
Rename class in pci_dev_info struct to allow to use C++ compilers. Updated drivers to use new struct. Change-Id: I17b94cb7bc094bccd615c8389a28589bfa90cab8 Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
2016-02-05drivers: set default priority for driversAnas Nashif
Use a default priority to avoid Kconfig blocking when priority is not set in SoC or Board. Change-Id: I4edda47b955a7ee834f04dc40d0decbd8dee6305 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05Use SoC instead of platform.Anas Nashif
Change terminology and use SoC instead of platform. An SoC provides features and default configurations available with an SoC. A board implements the SoC and adds more features and IP block specific to the board to extend the SoC functionality such as sensors and debugging features. Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05spi: dw: intel: move IOAPIC interrupt trigger flags into driverDaniel Leung
Move the common #define for IOAPIC interrupt trigger flags out of platform board.h and into the driver. Change-Id: I89090181acb5f48dd797e7773ab65c5f3d46c42a Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05irq: removes priority parameter from IRQ_CONFIG macroJuan Manuel Cruz
Removes the 'priority' parameter from the IRQ_CONFIG macro. This parameter was not used anymore in any architecture. The priority is handled in the IRQ_CONNECT macro. The documentation is updated as well. Change-Id: I24a293c5e41bd729d5e759113e0c4a8a6a61e0dd Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05quark_se: rename platform and remove x86 suffixAnas Nashif
Change-Id: I19ac3a4c6081720736c6fbf16b649ccf6ae60e2f Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05init: Implement fine-grained initialization policyDmitriy Korovkin
Put initialization priorities as device driver Kconfig parameter. Initialization priority value for each platform is defined in the platform Kconfig file. Drivers and platform code use SYS_DEFINE_DEVICE to add and initialization function. Change-Id: I2f4f3c7370dac02408a1b50a0a1bade8b427a282 Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05kconfig: define architecture as a kconfig variableAnas Nashif
Do not depend on environment variables and use a kconfig variable for defining the architecture. In addition, remove the X86_32 variable, it just duplicates X86 for not good reason, at least until start supporting MCUs with 64bit. Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05spi: dw: Fix various building and support issuesTomasz Bursztyka
- Build the actual driver when relevant - Provide the IOAPIC stub - Provide the IRQ flags for IRQ_CONNECT_STATIC - Set the default IRQ priorities Change-Id: Iea20ef67c92cf7f48791fba5a8021448b7059950 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: Add support for Designware SPI controllerTomasz Bursztyka
Such controller is found on Quark SE Lakemont and ARC cores. This driver currently supports the Lakemont core (x86). Change-Id: Iefebd6ce9dbe81aa3902e7c2d801b07c027c548a Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05irq: Add flags to IRQ_CONNECT_STATIC() macro and irq_connect() functionDmitriy Korovkin
Flags allow passing IRQ triggering option for x86 architecture. Each platform defines flags for a particular device and then device driver uses them when registers the interrupt handler. The change in API means that device drivers and sample applications need to use the new API. IRQ triggering configuration is now handled by device drivers by using flags passed to interrupt registering API: IRQ_CONNECT_STATIC() or irq_connect() Change-Id: Ibc4312ea2b4032a2efc5b913c6389f780a2a11d1 Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05spi: intel: Fix byte flow and error handlingTomasz Bursztyka
- ROR interrupt needs to be acked by resetting the bit to 0 - Rx threshold seems buggy on that controller and setting it above 1 generates unreliable transmission as sometimes it does not trigger any interrupt though the rx fifo is just full. Change-Id: I4949c1fe7b42c70973efd4e0dafd14c6171f13f6 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05galileo: SPI and pinmux init level need to be reversedTomasz Bursztyka
SPI port 1 needs the pinmuxer to be initialized first. Or then, all modifications required from the CS GPIO logic won't apply. Change-Id: Ibe4b2d4096065a9add23373075090d5e8a014650 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05spi: galileo: SPI port 1 uses DW GPIO pin 2 for CSTomasz Bursztyka
As for the SPI port 0, SPI port 1 needs a GPIO pin to emulate the CS. Change-Id: I00911cd25c3fa0ae17a02ee6f43cbea7f4fbcca2 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05spi: intel: Fix the retrieval of the clock dividerTomasz Bursztyka
Obviously it's '&' and not '&&'. Change-Id: I9bb9fee80a67697e8ea62bb001af1b72f5a356e6 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05intel_spi: convert SPI to new driver init methodDan Kalowsky
Convering the intel_spi to use the updated device model Change-Id: I016822aeecaf707ffa31b57b4e51e99262fce0e5 Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com> Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05Fix various default IRQ prioritiesPeter Mitsis
Changes the default IRQ priority level from 0 to 2 for the following kernel configuration options as priorities 0 and 1 are reserved for the first 32 IDT entries. SHARED_IRQ_0_PRI SHARED_IRQ_1_PRI I2C_DW_0_INT_PRIORITY GPIO_DW_0_PRI GPIO_DW_1_PRI SPI_INTEL_PORT_0_PRI SPI_INTEL_PORT_1_PRI Change-Id: I0fc821c68156eb1e1fe776b2bd4ff5890bba40e8 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
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