From 4792f363a4c63e1cd49a84ba1494b8464d9509a9 Mon Sep 17 00:00:00 2001 From: fallrisk Date: Wed, 26 Apr 2017 09:52:42 -0700 Subject: arch: Moved atmel_sam3 to atmel_sam3x. Found out that the SAM3 series is not a single series. There are actully 3 different series, 3U, 3A, and 3X. Origin: Original Jira: ZEP-2067 Change-Id: I61cdc826cc32dbdd25b5e6bafaada062c8ae8417 Signed-off-by: Justin Watson --- .../soc/atmel_sam/sam3/Kconfig.defconfig.series | 107 --------- arch/arm/soc/atmel_sam/sam3/Kconfig.series | 28 --- arch/arm/soc/atmel_sam/sam3/Kconfig.soc | 85 ------- arch/arm/soc/atmel_sam/sam3/Makefile | 9 - arch/arm/soc/atmel_sam/sam3/linker.ld | 9 - arch/arm/soc/atmel_sam/sam3/soc.c | 184 --------------- arch/arm/soc/atmel_sam/sam3/soc.h | 247 --------------------- arch/arm/soc/atmel_sam/sam3/soc_registers.h | 235 -------------------- .../soc/atmel_sam/sam3x/Kconfig.defconfig.series | 107 +++++++++ arch/arm/soc/atmel_sam/sam3x/Kconfig.series | 28 +++ arch/arm/soc/atmel_sam/sam3x/Kconfig.soc | 85 +++++++ arch/arm/soc/atmel_sam/sam3x/Makefile | 9 + arch/arm/soc/atmel_sam/sam3x/linker.ld | 9 + arch/arm/soc/atmel_sam/sam3x/soc.c | 184 +++++++++++++++ arch/arm/soc/atmel_sam/sam3x/soc.h | 247 +++++++++++++++++++++ arch/arm/soc/atmel_sam/sam3x/soc_registers.h | 235 ++++++++++++++++++++ 16 files changed, 904 insertions(+), 904 deletions(-) delete mode 100644 arch/arm/soc/atmel_sam/sam3/Kconfig.defconfig.series delete mode 100644 arch/arm/soc/atmel_sam/sam3/Kconfig.series delete mode 100644 arch/arm/soc/atmel_sam/sam3/Kconfig.soc delete mode 100644 arch/arm/soc/atmel_sam/sam3/Makefile delete mode 100644 arch/arm/soc/atmel_sam/sam3/linker.ld delete mode 100644 arch/arm/soc/atmel_sam/sam3/soc.c delete mode 100644 arch/arm/soc/atmel_sam/sam3/soc.h delete mode 100644 arch/arm/soc/atmel_sam/sam3/soc_registers.h create mode 100644 arch/arm/soc/atmel_sam/sam3x/Kconfig.defconfig.series create mode 100644 arch/arm/soc/atmel_sam/sam3x/Kconfig.series create mode 100644 arch/arm/soc/atmel_sam/sam3x/Kconfig.soc create mode 100644 arch/arm/soc/atmel_sam/sam3x/Makefile create mode 100644 arch/arm/soc/atmel_sam/sam3x/linker.ld create mode 100644 arch/arm/soc/atmel_sam/sam3x/soc.c create mode 100644 arch/arm/soc/atmel_sam/sam3x/soc.h create mode 100644 arch/arm/soc/atmel_sam/sam3x/soc_registers.h diff --git a/arch/arm/soc/atmel_sam/sam3/Kconfig.defconfig.series b/arch/arm/soc/atmel_sam/sam3/Kconfig.defconfig.series deleted file mode 100644 index 39f1b7a7b..000000000 --- a/arch/arm/soc/atmel_sam/sam3/Kconfig.defconfig.series +++ /dev/null @@ -1,107 +0,0 @@ -# Kconfig - Atmel SAM3 MCU series configuration options -# -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2016 Intel Corporation. -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_SAM3 || SOC_ATMEL_SAM3X8E - -config SOC_SERIES - string - default sam3 - -config SOC_PART_NUMBER - string - default sam3x8e if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E - -config NUM_IRQ_PRIO_BITS - int - default 3 - -# -# SAM3 family has total 45 peripherals capable of -# generating interrupts. -# -config NUM_IRQS - int - default 45 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 84000000 - -# -# SRAM address depends on the processor. -# -# SAM3X8E has two SRAM banks: -# 64K @ 0x20000000 -# 32K @ 0x20080000 -# The first 64K is mirrored at 0x20070000 -# to provide one continuous 96K block. -# -config SRAM_SIZE - default 96 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E - -config SRAM_BASE_ADDRESS - default 0x20000000 if !SOC_PART_NUMBER_SAM3X8E && !SOC_ATMEL_SAM3X8E - default 0x20070000 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E - -# -# Atmel SAM3 family has flash starting @ 0x00080000. -# -config FLASH_SIZE - default 512 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E - -config FLASH_BASE_ADDRESS - default 0x00080000 - -if UART_ATMEL_SAM3 - -config UART_ATMEL_SAM3_BAUD_RATE - default 115200 - -config UART_ATMEL_SAM3_CLK_FREQ - default 84000000 - -endif # UART_ATMEL_SAM3 - -if GPIO - -config GPIO_ATMEL_SAM3 - def_bool y - -config GPIO_ATMEL_SAM3_PORTA - default y - -config GPIO_ATMEL_SAM3_PORTB - default y - -config GPIO_ATMEL_SAM3_PORTC - default y - -config GPIO_ATMEL_SAM3_PORTD - default y - -endif # GPIO - -if I2C - -config I2C_ATMEL_SAM3 - def_bool y - -config I2C_0 - default y -config I2C_0_IRQ_PRI - default 0 - -config I2C_1 - default y - -config I2C_1_IRQ_PRI - default 0 - -endif # I2C - -endif # SOC_SERIES_SAM3 diff --git a/arch/arm/soc/atmel_sam/sam3/Kconfig.series b/arch/arm/soc/atmel_sam/sam3/Kconfig.series deleted file mode 100644 index c403bd1b8..000000000 --- a/arch/arm/soc/atmel_sam/sam3/Kconfig.series +++ /dev/null @@ -1,28 +0,0 @@ -# Kconfig - Atmel SAM3 MCU series -# -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2016 Intel Corporation. -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_SAM3 - bool "Atmel SAM3 MCU" - select CPU_CORTEX_M - select CPU_CORTEX_M3 - select SOC_FAMILY_SAM - select SYS_POWER_LOW_POWER_STATE_SUPPORTED - select CPU_HAS_SYSTICK - help - Enable support for Atmel SAM3 Cortex-M3 microcontrollers. - Part No.: SAM3X8E - -config SOC_ATMEL_SAM3X8E - bool "Atmel SAM3X8E Processor" - select SOC_PART_NUMBER_SAM3X8E - select CPU_CORTEX_M - select CPU_CORTEX_M3 - select SOC_FAMILY_SAM - select SYS_POWER_LOW_POWER_STATE_SUPPORTED - select CPU_HAS_SYSTICK - select SOC_ATMEL_SAM3 diff --git a/arch/arm/soc/atmel_sam/sam3/Kconfig.soc b/arch/arm/soc/atmel_sam/sam3/Kconfig.soc deleted file mode 100644 index 8af9aa168..000000000 --- a/arch/arm/soc/atmel_sam/sam3/Kconfig.soc +++ /dev/null @@ -1,85 +0,0 @@ -# Kconfig - Atmel SAM3 MCU series -# -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2016 Intel Corporation. -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -choice - prompt "Atmel SAM3 MCU Selection" - depends on SOC_SERIES_SAM3 - - config SOC_PART_NUMBER_SAM3X8E - bool "SAM3X8E" -endchoice - -if SOC_SERIES_SAM3 || SOC_ATMEL_SAM3X8E - -config SOC_ATMEL_SAM3_EXT_SLCK - bool "Atmel SAM3 to use external crystal oscillator for slow clock" - default n - help - Says y if you want to use external 32 kHz crystal - oscillator to drive the slow clock. Note that this - adds a few seconds to boot time, as the crystal - needs to stabilize after power-up. - - Says n if you do not need accurate and precise timers. - The slow clock will be driven by the internal fast - RC oscillator running at 32 kHz. - -config SOC_ATMEL_SAM3_EXT_MAINCK - bool "Atmel SAM3 to use external crystal oscillator for main clock" - default n - help - The main clock is being used to drive the PLL, and - thus driving the processor clock. - - Says y if you want to use external crystal oscillator - to drive the main clock. Note that this adds about - a second to boot time, as the crystal needs to - stabilize after power-up. - - The crystal used here can be from 3 to 20 MHz. - - Says n here will use the internal fast RC oscillator - running at 12 MHz. - -config SOC_ATMEL_SAM3_PLLA_MULA - hex - default 0x06 - help - This is the multiplier (MULA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 6, and DIVA == 1, - PLL is running at 7 times of main clock. - -config SOC_ATMEL_SAM3_PLLA_DIVA - hex - default 0x01 - help - This is the divider (DIVA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 6, and DIVA == 1, - PLL is running at 7 times of main clock. - -config SOC_ATMEL_SAM3_WAIT_MODE - bool "Atmel SAM3 goes to Wait mode instead of Sleep mode" - depends on SOC_ATMEL_SAM3_EXT_MAINCK - default y if DEBUG - help - For JTAG debugging CPU clock (HCLK) should not stop. In order - to achieve this, make CPU go to Wait mode instead of Sleep - mode while using external crystal oscillator for main clock. - -endif # SOC_SERIES_SAM3 diff --git a/arch/arm/soc/atmel_sam/sam3/Makefile b/arch/arm/soc/atmel_sam/sam3/Makefile deleted file mode 100644 index c5859e1cb..000000000 --- a/arch/arm/soc/atmel_sam/sam3/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# Makefile - Atmel SAM3 MCU series -# -# Copyright (c) 2017 Justin Watson -# SPDX-License-Identifier: Apache-2.0 -# - -ZEPHYRINCLUDE += -I$(srctree)/arch/arm/soc/atmel_sam/common - -obj-y += soc.o diff --git a/arch/arm/soc/atmel_sam/sam3/linker.ld b/arch/arm/soc/atmel_sam/sam3/linker.ld deleted file mode 100644 index b6ccb0279..000000000 --- a/arch/arm/soc/atmel_sam/sam3/linker.ld +++ /dev/null @@ -1,9 +0,0 @@ -/* linker.ld - Linker command/script file */ - -/* - * Copyright (c) 2014 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include diff --git a/arch/arm/soc/atmel_sam/sam3/soc.c b/arch/arm/soc/atmel_sam/sam3/soc.c deleted file mode 100644 index 28276ecd3..000000000 --- a/arch/arm/soc/atmel_sam/sam3/soc.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief System/hardware module for Atmel SAM3 family processor - * - * This module provides routines to initialize and support board-level hardware - * for the Atmel SAM3 family processor. - */ - -#include -#include -#include -#include - -#include -#include - -/** - * @brief Setup various clock on SoC. - * - * Setup the SoC clocks according to section 28.12 in datasheet. - * - * Assumption: - * SLCK = 32.768kHz - */ -static ALWAYS_INLINE void clock_init(void) -{ - u32_t tmp; - - /* Note: - * Magic numbers below are obtained by reading the registers - * when the SoC was running the SAM-BA bootloader - * (with reserved bits set to 0). - */ - -#ifdef CONFIG_SOC_ATMEL_SAM3_EXT_SLCK - /* This part is to switch the slow clock to using - * the external 32 kHz crystal oscillator. - */ - - /* Select external crystal */ - __SUPC->cr = SUPC_CR_KEY | SUPC_CR_XTALSEL; - - /* Wait for oscillator to be stablized */ - while (!(__SUPC->sr & SUPC_SR_OSCSEL)) - ; -#endif /* CONFIG_SOC_ATMEL_SAM3_EXT_SLCK */ - -#ifdef CONFIG_SOC_ATMEL_SAM3_EXT_MAINCK - /* Start the external main oscillator */ - __PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_4MHZ - | PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN - | PMC_CKGR_MOR_MOSCXTST; - - /* Wait for main oscillator to be stablized */ - while (!(__PMC->sr & PMC_INT_MOSCXTS)) - ; - - /* Select main oscillator as source since it is more accurate - * according to datasheet. - */ - __PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_4MHZ - | PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN - | PMC_CKGR_MOR_MOSCXTST | PMC_CKGR_MOR_MOSCSEL; - - /* Wait for main oscillator to be selected */ - while (!(__PMC->sr & PMC_INT_MOSCSELS)) - ; -#ifdef CONFIG_SOC_ATMEL_SAM3_WAIT_MODE - /* - * Instruct CPU enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG - */ - __PMC->fsmr |= PMC_FSMR_LPM; -#endif -#else - /* Set main fast RC oscillator to 12 MHz */ - __PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_12MHZ - | PMC_CKGR_MOR_MOSCRCEN; - - /* Wait for main fast RC oscillator to be stablized */ - while (!(__PMC->sr & PMC_INT_MOSCRCS)) - ; -#endif /* CONFIG_SOC_ATMEL_SAM3_EXT_MAINCK */ - - /* Use PLLA as master clock. - * According to datasheet, PMC_MCKR must not be programmed in - * a single write operation. So it seems the safe way is to - * get the system to use main clock (by setting CSS). Then set - * the prescaler (PRES). Finally setting it back to using PLL. - */ - - /* Switch to main clock first so we can setup PLL */ - tmp = __PMC->mckr & ~PMC_MCKR_CSS_MASK; - __PMC->mckr = tmp | PMC_MCKR_CSS_MAIN; - - /* Wait for clock selection complete */ - while (!(__PMC->sr & PMC_INT_MCKRDY)) - ; - - /* Setup PLLA */ - __PMC->ckgr_pllar = PMC_CKGR_PLLAR_DIVA | PMC_CKGR_PLLAR_ONE - | PMC_CKGR_PLLAR_MULA - | PMC_CKGR_PLLAR_PLLACOUNT; - - /* Wait for PLL lock */ - while (!(__PMC->sr & PMC_INT_LOCKA)) - ; - - /* Setup prescaler */ - tmp = __PMC->mckr & ~PMC_MCKR_PRES_MASK; - __PMC->mckr = tmp | PMC_MCKR_PRES_CLK; - - /* Wait for main clock setup complete */ - while (!(__PMC->sr & PMC_INT_MCKRDY)) - ; - - /* Finally select PLL as clock source */ - tmp = __PMC->mckr & ~PMC_MCKR_CSS_MASK; - __PMC->mckr = tmp | PMC_MCKR_CSS_PLLA; - - /* Wait for main clock setup complete */ - while (!(__PMC->sr & PMC_INT_MCKRDY)) - ; -} - -/** - * @brief Perform basic hardware initialization at boot. - * - * This needs to be run from the very beginning. - * So the init priority has to be 0 (zero). - * - * @return 0 - */ -static int atmel_sam3_init(struct device *arg) -{ - u32_t key; - - ARG_UNUSED(arg); - - /* Note: - * Magic numbers below are obtained by reading the registers - * when the SoC was running the SAM-BA bootloader - * (with reserved bits set to 0). - */ - - key = irq_lock(); - - /* Setup the flash controller. - * The bootloader is running @ 48 MHz with - * FWS == 2. - * When running at 84 MHz, FWS == 4 seems - * to be more stable, and allows the board - * to boot. - */ - __EEFC0->fmr = 0x00000400; - __EEFC1->fmr = 0x00000400; - - _ClearFaults(); - - /* Setup master clock */ - clock_init(); - - /* Disable watchdog timer, not used by system */ - __WDT->mr |= WDT_DISABLE; - - /* Install default handler that simply resets the CPU - * if configured in the kernel, NOP otherwise - */ - NMI_INIT(); - - irq_unlock(key); - - return 0; -} - -SYS_INIT(atmel_sam3_init, PRE_KERNEL_1, 0); diff --git a/arch/arm/soc/atmel_sam/sam3/soc.h b/arch/arm/soc/atmel_sam/sam3/soc.h deleted file mode 100644 index 39945d13b..000000000 --- a/arch/arm/soc/atmel_sam/sam3/soc.h +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file SoC configuration macros for the Atmel SAM3 family processors. - */ - -#ifndef _ATMEL_SAM3_SOC_H_ -#define _ATMEL_SAM3_SOC_H_ - -/* IRQ numbers (from section 9.1, Peripheral Identifiers). */ -#define IRQ_SUPC 0 /* Supply Controller */ -#define IRQ_RSTC 1 /* Reset Controller */ -#define IRQ_RTC 2 /* Real-time Clock */ -#define IRQ_RTT 3 /* Real-time Timer */ -#define IRQ_WDG 4 /* Watchdog Timer */ -#define IRQ_PMC 5 /* Power Management Controller */ -#define IRQ_EEFC0 6 /* Enhanced Embedded Flash Controller 0 */ -#define IRQ_EEFC1 7 /* Enhanced Embedded Flash Controller 1 */ -#define IRQ_UART 8 /* UART */ -#define IRQ_PIOA 11 /* Parallel IO Controller A */ -#define IRQ_PIOB 12 /* Parallel IO Controller B */ -#define IRQ_PIOC 13 /* Parallel IO Controller C */ -#define IRQ_PIOD 14 /* Parallel IO Controller D */ -#define IRQ_PIOE 15 /* Parallel IO Controller E */ -#define IRQ_PIOF 16 /* Parallel IO Controller F */ -#define IRQ_USART0 17 /* USART #0 */ -#define IRQ_USART1 18 /* USART #1 */ -#define IRQ_USART2 19 /* USART #2 */ -#define IRQ_USART3 20 /* USART #3 */ -#define IRQ_HSMCI 21 /* High Speed Multimedia Card Interface */ -#define IRQ_TWI0 22 /* Two-wire Interface #0 */ -#define IRQ_TWI1 23 /* Two-wire Interface #1 */ -#define IRQ_SPI0 24 /* SPI #0 */ -#define IRQ_SPI1 25 /* SPI #1 */ -#define IRQ_SSC 26 /* Synchronous Serial Controller */ -#define IRQ_TC0 27 /* Timer Counter Channel #0 */ -#define IRQ_TC1 28 /* Timer Counter Channel #1 */ -#define IRQ_TC2 29 /* Timer Counter Channel #2 */ -#define IRQ_TC3 30 /* Timer Counter Channel #3 */ -#define IRQ_TC4 31 /* Timer Counter Channel #4 */ -#define IRQ_TC5 32 /* Timer Counter Channel #5 */ -#define IRQ_TC6 33 /* Timer Counter Channel #6 */ -#define IRQ_TC7 34 /* Timer Counter Channel #7 */ -#define IRQ_TC8 35 /* Timer Counter Channel #8 */ -#define IRQ_PWM 36 /* PWM Controller */ -#define IRQ_ADC 37 /* ADC Controller */ -#define IRQ_DACC 38 /* DAC Controller */ -#define IRQ_DMAC 39 /* DMA Controller */ -#define IRQ_UOTGHS 40 /* USB OTG High Speed */ -#define IRQ_TRNG 41 /* True Random Number Generator */ -#define IRQ_EMAC 42 /* Ehternet MAC */ -#define IRQ_CAN0 43 /* CAN Controller #0 */ -#define IRQ_CAN1 44 /* CAN Controller #1 */ - -/* PID: Peripheral IDs (from section 9.1, Peripheral Identifiers). - * PMC uses PIDs to enable clock for peripherals. - */ -#define PID_RTC 2 /* Real-time Clock */ -#define PID_RTT 3 /* Real-time Timer */ -#define PID_WDG 4 /* Watchdog Timer */ -#define PID_PMC 5 /* Power Management Controller */ -#define PID_EEFC0 6 /* Enhanced Embedded Flash Controller 0 */ -#define PID_EEFC1 7 /* Enhanced Embedded Flash Controller 1 */ -#define PID_UART 8 /* UART */ -#define PID_PIOA 11 /* Parallel IO Controller A */ -#define PID_PIOB 12 /* Parallel IO Controller B */ -#define PID_PIOC 13 /* Parallel IO Controller C */ -#define PID_PIOD 14 /* Parallel IO Controller D */ -#define PID_PIOE 15 /* Parallel IO Controller E */ -#define PID_PIOF 16 /* Parallel IO Controller F */ -#define PID_USART0 17 /* USART #0 */ -#define PID_USART1 18 /* USART #1 */ -#define PID_USART2 19 /* USART #2 */ -#define PID_USART3 20 /* USART #3 */ -#define PID_HSMCI 21 /* High Speed Multimedia Card Interface */ -#define PID_TWI0 22 /* Two-wire Interface #0 */ -#define PID_TWI1 23 /* Two-wire Interface #1 */ -#define PID_SPI0 24 /* SPI #0 */ -#define PID_SPI1 25 /* SPI #1 */ -#define PID_SSC 26 /* Synchronous Serial Controller */ -#define PID_TC0 27 /* Timer Counter Channel #0 */ -#define PID_TC1 28 /* Timer Counter Channel #1 */ -#define PID_TC2 29 /* Timer Counter Channel #2 */ -#define PID_TC3 30 /* Timer Counter Channel #3 */ -#define PID_TC4 31 /* Timer Counter Channel #4 */ -#define PID_TC5 32 /* Timer Counter Channel #5 */ -#define PID_TC6 33 /* Timer Counter Channel #6 */ -#define PID_TC7 34 /* Timer Counter Channel #7 */ -#define PID_TC8 35 /* Timer Counter Channel #8 */ -#define PID_PWM 36 /* PWM Controller */ -#define PID_ADC 37 /* ADC Controller */ -#define PID_DACC 38 /* DAC Controller */ -#define PID_DMAC 39 /* DMA Controller */ -#define PID_UOTGHS 40 /* USB OTG High Speed */ -#define PID_TRNG 41 /* True Random Number Generator */ -#define PID_EMAC 42 /* Ehternet MAC */ -#define PID_CAN0 43 /* CAN Controller #0 */ -#define PID_CAN1 44 /* CAN Controller #1 */ - -/* Power Manager Controller */ -#define PMC_ADDR 0x400E0600 - -#define PMC_CKGR_UCKR_UPLLEN (1 << 16) -#define PMC_CKGR_UCKR_UPLLCOUNT (3 << 20) - -#define PMC_CKGR_MOR_KEY (0x37 << 16) -#define PMC_CKGR_MOR_MOSCXTST (0xFF << 8) -#define PMC_CKGR_MOR_MOSCXTEN (1 << 0) -#define PMC_CKGR_MOR_MOSCRCEN (1 << 3) -#define PMC_CKGR_MOR_MOSCRCF_4MHZ (0 << 4) -#define PMC_CKGR_MOR_MOSCRCF_8MHZ (1 << 4) -#define PMC_CKGR_MOR_MOSCRCF_12MHZ (2 << 4) -#define PMC_CKGR_MOR_MOSCSEL (1 << 24) - -#define PMC_CKGR_PLLAR_PLLACOUNT (0x3F << 8) -#define PMC_CKGR_PLLAR_ONE (1 << 29) - -/* - * PLL clock = Main * (MULA + 1) / DIVA - * - * By default, MULA == 6, DIVA == 1. - * With main crystal running at 12 MHz, - * PLL = 12 * (6 + 1) / 1 = 84 MHz - * - * With processor clock prescaler at 1, - * the processor clock is at 84 MHz. - */ -#define PMC_CKGR_PLLAR_MULA \ - ((CONFIG_SOC_ATMEL_SAM3_PLLA_MULA) << 16) -#define PMC_CKGR_PLLAR_DIVA \ - ((CONFIG_SOC_ATMEL_SAM3_PLLA_DIVA) << 0) - -#define PMC_MCKR_CSS_MASK (0x3) -#define PMC_MCKR_CSS_SLOW (0 << 0) -#define PMC_MCKR_CSS_MAIN (1 << 0) -#define PMC_MCKR_CSS_PLLA (2 << 0) -#define PMC_MCKR_CSS_UPLL (3 << 0) -#define PMC_MCKR_PRES_MASK (0x70) -#define PMC_MCKR_PRES_CLK (0 << 4) -#define PMC_MCKR_PRES_DIV2 (1 << 4) -#define PMC_MCKR_PRES_DIV4 (2 << 4) -#define PMC_MCKR_PRES_DIV8 (3 << 4) -#define PMC_MCKR_PRES_DIV16 (4 << 4) -#define PMC_MCKR_PRES_DIV32 (5 << 4) -#define PMC_MCKR_PRES_DIV64 (6 << 4) -#define PMC_MCKR_PRES_DIV3 (7 << 4) -#define PMC_MCKR_PLLADIV2 (1 << 12) -#define PMC_MCKR_UPLLDIV2 (1 << 13) - -#define PMC_FSMR_LPM (1 << 20) - -#define PMC_INT_MOSCXTS (1 << 0) -#define PMC_INT_LOCKA (1 << 1) -#define PMC_INT_MCKRDY (1 << 3) -#define PMC_INT_LOCKU (1 << 6) -#define PMC_INT_OSCSELS (1 << 7) -#define PMC_INT_PCKRDY0 (1 << 8) -#define PMC_INT_PCKRDY1 (1 << 9) -#define PMC_INT_PCKRDY2 (1 << 10) -#define PMC_INT_MOSCSELS (1 << 16) -#define PMC_INT_MOSCRCS (1 << 17) -#define PMC_INT_CFDEV (1 << 18) -#define PMC_INT_CFDS (1 << 19) -#define PMC_INT_FOS (1 << 20) - -/* UART */ -#define UART_ADDR 0x400E0800 - -/* EEFC */ -#define EEFC_BANK0_ADDR 0x400E0A00 -#define EEFC_BANK1_ADDR 0x400E0C00 - -/* Peripheral DMA Controller (PDC) */ -#define PDC_PTCR_RXTEN (1 << 0) -#define PDC_PTCR_RXTDIS (1 << 1) -#define PDC_PTCR_TXTEN (1 << 8) -#define PDC_PTCR_TXTDIS (1 << 9) - -/* PIO Controllers */ -#define PIOA_ADDR 0x400E0E00 -#define PIOB_ADDR 0x400E1000 -#define PIOC_ADDR 0x400E1200 -#define PIOD_ADDR 0x400E1400 -#define PIOE_ADDR 0x400E1600 -#define PIOF_ADDR 0x400E1800 - -/* Supply Controller (SUPC) */ -#define SUPC_ADDR 0x400E1A10 - -#define SUPC_CR_KEY (0xA5 << 24) -#define SUPC_CR_XTALSEL (1 << 3) - -#define SUPC_SR_OSCSEL (1 << 7) - -/* Two-wire Interface (TWI) */ -#define TWI0_ADDR 0x4008C000 -#define TWI1_ADDR 0x40090000 - -/* Watchdog timer (WDT) */ -#define WDT_ADDR 0x400E1A50 - -#define WDT_DISABLE (1 << 15) - -#ifndef _ASMLANGUAGE - -#include -#include -#include - -#include "soc_registers.h" - -/* uart configuration settings */ -#define UART_IRQ_FLAGS 0 - -/* EEFC Register struct */ -#define __EEFC0 ((volatile struct __eefc *)EEFC_BANK0_ADDR) -#define __EEFC1 ((volatile struct __eefc *)EEFC_BANK1_ADDR) - -/* PMC Register struct */ -#define __PMC ((volatile struct __pmc *)PMC_ADDR) - -/* PIO Registers struct */ -#define __PIOA ((volatile struct __pio *)PIOA_ADDR) -#define __PIOB ((volatile struct __pio *)PIOB_ADDR) -#define __PIOC ((volatile struct __pio *)PIOC_ADDR) -#define __PIOD ((volatile struct __pio *)PIOD_ADDR) -#define __PIOE ((volatile struct __pio *)PIOE_ADDR) -#define __PIOF ((volatile struct __pio *)PIOF_ADDR) - -/* Supply Controller Register struct */ -#define __SUPC ((volatile struct __supc *)SUPC_ADDR) - -/* Two-wire Interface (TWI) */ -#define __TWI0 ((volatile struct __twi *)TWI0_ADDR) -#define __TWI1 ((volatile struct __twi *)TWI1_ADDR) - -/* Watchdog timer (WDT) */ -#define __WDT ((volatile struct __wdt *)WDT_ADDR) - -#endif /* !_ASMLANGUAGE */ - -#endif /* _ATMEL_SAM3_SOC_H_ */ diff --git a/arch/arm/soc/atmel_sam/sam3/soc_registers.h b/arch/arm/soc/atmel_sam/sam3/soc_registers.h deleted file mode 100644 index 050269e5b..000000000 --- a/arch/arm/soc/atmel_sam/sam3/soc_registers.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file SoC configuration macros for the Atmel SAM3 family processors. - * - * Refer to the datasheet for more information about these registers. - */ - -#ifndef _ATMEL_SAM3_SOC_REGS_H_ -#define _ATMEL_SAM3_SOC_REGS_H_ - -/* Peripheral DMA Controller - * - * DO NOT USE DIRECTLY! This is to be used within individual - * peripheral's register struct. - * - * Starts at offset 0x100. - */ -struct __pdc { - u32_t rpr; /* 0x100 Receive Pointer */ - u32_t rcr; /* 0x104 Receive Counter */ - u32_t tpr; /* 0x108 Transmit Pointer */ - u32_t tcr; /* 0x10C Transmit Counter */ - u32_t rnpr; /* 0x110 Receive Next Pointer */ - u32_t rncr; /* 0x114 Receive Next Counter */ - u32_t tnpr; /* 0x118 Transmit Next Pointer */ - u32_t tncr; /* 0x11C Transmit Next Counter */ - u32_t ptcr; /* 0x120 Transfer Control */ - u32_t ptsr; /* 0x124 Transfer Status */ -}; - -/* Enhanced Embedded Flash Controller */ -struct __eefc { - u32_t fmr; /* 0x00 Flash Mode Register */ - u32_t fcr; /* 0x04 Flash Command Register */ - u32_t fsr; /* 0x08 Flash Status Register */ - u32_t frr; /* 0x0C Flash Result Register */ -}; - -/* PIO Controller */ -struct __pio { - u32_t per; /* 0x00 Enable */ - u32_t pdr; /* 0x04 Disable */ - u32_t psr; /* 0x08 Status */ - - u32_t res0; /* 0x0C reserved */ - - u32_t oer; /* 0x10 Output Enable */ - u32_t odr; /* 0x14 Output Disable */ - u32_t osr; /* 0x18 Output Status */ - - u32_t res1; /* 0x1C reserved */ - - u32_t ifer; /* 0x20 Glitch Input Filter Enable */ - u32_t ifdr; /* 0x24 Glitch Input Filter Disable */ - u32_t ifsr; /* 0x28 Glitch Input Fitler Status */ - - u32_t res2; /* 0x2C reserved */ - - u32_t sodr; /* 0x30 Set Output Data */ - u32_t codr; /* 0x34 Clear Output Data */ - u32_t odsr; /* 0x38 Output Data Status */ - u32_t pdsr; /* 0x3C Pin Data Status */ - - u32_t ier; /* 0x40 Interrupt Enable */ - u32_t idr; /* 0x44 Interrupt Disable */ - u32_t imr; /* 0x48 Interrupt Mask */ - u32_t isr; /* 0x4C Interrupt Status */ - - u32_t mder; /* 0x50 Multi-driver Enable */ - u32_t mddr; /* 0x54 Multi-driver Disable */ - u32_t mdsr; /* 0x58 Multi-driver Status */ - - u32_t res3; /* 0x5C reserved */ - - u32_t pudr; /* 0x60 Pull-up Disable */ - u32_t puer; /* 0x64 Pull-up Enable */ - u32_t pusr; /* 0x68 Pad Pull-up Status */ - - u32_t res4; /* 0x6C reserved */ - - u32_t absr; /* 0x70 Peripheral AB Select */ - - u32_t res5[3]; /* 0x74-0x7C reserved */ - - u32_t scifsr; /* 0x80 System Clock Glitch Input */ - /* Filter Select */ - - u32_t difsr; /* 0x84 Debouncing Input Filter */ - /* Select */ - - u32_t ifdgsr; /* 0x88 Glitch or Debouncing Input */ - /* Filter Clock Selection */ - /* Status */ - - u32_t scdr; /* 0x8C Slow Clock Divider Debounce */ - - u32_t res6[4]; /* 0x90-0x9C reserved */ - - u32_t ower; /* 0xA0 Output Write Enable */ - u32_t owdr; /* 0xA4 Output Write Disable */ - u32_t owsr; /* 0xA8 Output Write Status */ - - u32_t res7; /* 0xAC reserved */ - - u32_t aimer; /* 0xB0 Additional Interrupt Modes */ - /* Enable */ - u32_t aimdr; /* 0xB4 Additional Interrupt Modes */ - /* Disable */ - u32_t aimmr; /* 0xB8 Additional Interrupt Modes */ - /* Mask */ - - u32_t res8; /* 0xBC reserved */ - - u32_t esr; /* 0xC0 Edge Select */ - u32_t lsr; /* 0xC4 Level Select */ - u32_t elsr; /* 0xC8 Edge/Level Status */ - - u32_t res9; /* 0xCC reserved */ - - u32_t fellsr; /* 0xD0 Falling Edge/Low Level Sel */ - u32_t rehlsr; /* 0xD4 Rising Edge/High Level Sel */ - u32_t frlhsr; /* 0xD8 Fall/Rise - Low/High Status */ - - u32_t res10; /* 0xDC reserved */ - - u32_t locksr; /* 0xE0 Lock Status */ - - u32_t wpmr; /* 0xE4 Write Protect Mode */ - u32_t wpsr; /* 0xE8 Write Protect Status */ -}; - -/* Power Management Controller */ -struct __pmc { - u32_t scer; /* 0x00 System Clock Enable */ - u32_t scdr; /* 0x04 System Clock Disable */ - u32_t scsr; /* 0x08 System Clock Status */ - - u32_t res0; /* 0x0C reserved */ - - u32_t pcer0; /* 0x10 Peripheral Clock Enable 0 */ - u32_t pcdr0; /* 0x14 Peripheral Clock Disable 0 */ - u32_t pcsr0; /* 0x18 Peripheral Clock Status 0 */ - - u32_t ckgr_uckr; /* 0x1C UTMI Clock */ - u32_t ckgr_mor; /* 0x20 Main Oscillator */ - u32_t ckgr_mcfr; /* 0x24 Main Clock Freq. */ - u32_t ckgr_pllar; /* 0x28 PLLA */ - - u32_t res1; /* 0x2C reserved */ - - u32_t mckr; /* 0x30 Master Clock */ - - u32_t res2; /* 0x34 reserved */ - - u32_t usb; /* 0x38 USB Clock */ - - u32_t res3; /* 0x3C reserved */ - - u32_t pck0; /* 0x40 Programmable Clock 0 */ - u32_t pck1; /* 0x44 Programmable Clock 1 */ - u32_t pck2; /* 0x48 Programmable Clock 2 */ - - u32_t res4[5]; /* 0x4C-0x5C reserved */ - - u32_t ier; /* 0x60 Interrupt Enable */ - u32_t idr; /* 0x64 Interrupt Disable */ - u32_t sr; /* 0x68 Status */ - u32_t imr; /* 0x6C Interrupt Mask */ - - u32_t fsmr; /* 0x70 Fast Startup Mode */ - u32_t fspr; /* 0x74 Fast Startup Polarity */ - - u32_t focr; /* 0x78 Fault Outpu Clear */ - - u32_t res5[26]; /* 0x7C-0xE0 reserved */ - - u32_t wpmr; /* 0xE4 Write Protect Mode */ - u32_t wpsr; /* 0xE8 Write Protect Status */ - - u32_t res6[5]; /* 0xEC-0xFC reserved */ - - u32_t pcer1; /* 0x100 Peripheral Clock Enable 1 */ - u32_t pcdr1; /* 0x104 Peripheral Clock Disable 1 */ - u32_t pcsr1; /* 0x108 Peripheral Clock Status 1 */ - - u32_t pcr; /* 0x10C Peripheral Control */ -}; - -/* Supply Controller (SUPC) */ -struct __supc { - u32_t cr; /* 0x00 Control */ - u32_t smmr; /* 0x04 Supply Monitor Mode */ - u32_t mr; /* 0x08 Mode */ - u32_t wumr; /* 0x0C Wake Up Mode */ - u32_t wuir; /* 0x10 Wake Up Inputs */ - u32_t sr; /* 0x14 Status */ -}; - -/* Two-wire Interface (TWI), aka I2C */ -struct __twi { - u32_t cr; /* 0x00 Control */ - u32_t mmr; /* 0x04 Master Mode */ - u32_t smr; /* 0x08 Slave Mode */ - u32_t iadr; /* 0x0C Internal Address */ - u32_t cwgr; /* 0x10 Clock Waveform Generator */ - - u32_t rev0[3]; /* 0x14-0x1C reserved */ - - u32_t sr; /* 0x20 Status */ - - u32_t ier; /* 0x24 Interrupt Enable */ - u32_t idr; /* 0x28 Interrupt Disable */ - u32_t imr; /* 0x2C Interrupt Mask */ - - u32_t rhr; /* 0x30 Receive Holding */ - u32_t thr; /* 0x34 Transmit Holding */ - - u32_t rev1[50]; /* 0x38-0xFC Reserved */ - - struct __pdc pdc; /* 0x100 - 0x124 PDC */ -}; - -/* Watchdog timer (WDT) */ -struct __wdt { - u32_t cr; /* 0x00 Control Register */ - u32_t mr; /* 0x04 Mode Register */ - u32_t sr; /* 0x08 Status Register */ -}; - -#endif /* _ATMEL_SAM3_SOC_REGS_H_ */ diff --git a/arch/arm/soc/atmel_sam/sam3x/Kconfig.defconfig.series b/arch/arm/soc/atmel_sam/sam3x/Kconfig.defconfig.series new file mode 100644 index 000000000..30159e2eb --- /dev/null +++ b/arch/arm/soc/atmel_sam/sam3x/Kconfig.defconfig.series @@ -0,0 +1,107 @@ +# Kconfig - Atmel SAM3X MCU series configuration options +# +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2016 Intel Corporation. +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_SAM3X || SOC_ATMEL_SAM3X8E + +config SOC_SERIES + string + default sam3x + +config SOC_PART_NUMBER + string + default sam3x8e if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E + +config NUM_IRQ_PRIO_BITS + int + default 3 + +# +# SAM3 family has total 45 peripherals capable of +# generating interrupts. +# +config NUM_IRQS + int + default 45 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 84000000 + +# +# SRAM address depends on the processor. +# +# SAM3X8E has two SRAM banks: +# 64K @ 0x20000000 +# 32K @ 0x20080000 +# The first 64K is mirrored at 0x20070000 +# to provide one continuous 96K block. +# +config SRAM_SIZE + default 96 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E + +config SRAM_BASE_ADDRESS + default 0x20000000 if !SOC_PART_NUMBER_SAM3X8E && !SOC_ATMEL_SAM3X8E + default 0x20070000 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E + +# +# Atmel SAM3X family has flash starting @ 0x00080000. +# +config FLASH_SIZE + default 512 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E + +config FLASH_BASE_ADDRESS + default 0x00080000 + +if UART_ATMEL_SAM3 + +config UART_ATMEL_SAM3_BAUD_RATE + default 115200 + +config UART_ATMEL_SAM3_CLK_FREQ + default 84000000 + +endif # UART_ATMEL_SAM3 + +if GPIO + +config GPIO_ATMEL_SAM3 + def_bool y + +config GPIO_ATMEL_SAM3_PORTA + default y + +config GPIO_ATMEL_SAM3_PORTB + default y + +config GPIO_ATMEL_SAM3_PORTC + default y + +config GPIO_ATMEL_SAM3_PORTD + default y + +endif # GPIO + +if I2C + +config I2C_ATMEL_SAM3 + def_bool y + +config I2C_0 + default y +config I2C_0_IRQ_PRI + default 0 + +config I2C_1 + default y + +config I2C_1_IRQ_PRI + default 0 + +endif # I2C + +endif # SOC_SERIES_SAM3X diff --git a/arch/arm/soc/atmel_sam/sam3x/Kconfig.series b/arch/arm/soc/atmel_sam/sam3x/Kconfig.series new file mode 100644 index 000000000..59bb0f4ea --- /dev/null +++ b/arch/arm/soc/atmel_sam/sam3x/Kconfig.series @@ -0,0 +1,28 @@ +# Kconfig - Atmel SAM3X MCU series +# +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2016 Intel Corporation. +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_SAM3X + bool "Atmel SAM3X MCU" + select CPU_CORTEX_M + select CPU_CORTEX_M3 + select SOC_FAMILY_SAM + select SYS_POWER_LOW_POWER_STATE_SUPPORTED + select CPU_HAS_SYSTICK + help + Enable support for Atmel SAM3X Cortex-M3 microcontrollers. + Part No.: SAM3X8E + +config SOC_ATMEL_SAM3X8E + bool "Atmel SAM3X8E Processor" + select SOC_PART_NUMBER_SAM3X8E + select CPU_CORTEX_M + select CPU_CORTEX_M3 + select SOC_FAMILY_SAM + select SYS_POWER_LOW_POWER_STATE_SUPPORTED + select CPU_HAS_SYSTICK + select SOC_ATMEL_SAM3 diff --git a/arch/arm/soc/atmel_sam/sam3x/Kconfig.soc b/arch/arm/soc/atmel_sam/sam3x/Kconfig.soc new file mode 100644 index 000000000..06bf04672 --- /dev/null +++ b/arch/arm/soc/atmel_sam/sam3x/Kconfig.soc @@ -0,0 +1,85 @@ +# Kconfig - Atmel SAM3X MCU series +# +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2016 Intel Corporation. +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +choice + prompt "Atmel SAM3X MCU Selection" + depends on SOC_SERIES_SAM3X + + config SOC_PART_NUMBER_SAM3X8E + bool "SAM3X8E" +endchoice + +if SOC_SERIES_SAM3X || SOC_ATMEL_SAM3X8E + +config SOC_ATMEL_SAM3X_EXT_SLCK + bool "Atmel SAM3 to use external crystal oscillator for slow clock" + default n + help + Says y if you want to use external 32 kHz crystal + oscillator to drive the slow clock. Note that this + adds a few seconds to boot time, as the crystal + needs to stabilize after power-up. + + Says n if you do not need accurate and precise timers. + The slow clock will be driven by the internal fast + RC oscillator running at 32 kHz. + +config SOC_ATMEL_SAM3X_EXT_MAINCK + bool "Atmel SAM3 to use external crystal oscillator for main clock" + default n + help + The main clock is being used to drive the PLL, and + thus driving the processor clock. + + Says y if you want to use external crystal oscillator + to drive the main clock. Note that this adds about + a second to boot time, as the crystal needs to + stabilize after power-up. + + The crystal used here can be from 3 to 20 MHz. + + Says n here will use the internal fast RC oscillator + running at 12 MHz. + +config SOC_ATMEL_SAM3X_PLLA_MULA + hex + default 0x06 + help + This is the multiplier (MULA) used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings + for a particular board. + + With default of MULA == 6, and DIVA == 1, + PLL is running at 7 times of main clock. + +config SOC_ATMEL_SAM3X_PLLA_DIVA + hex + default 0x01 + help + This is the divider (DIVA) used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings + for a particular board. + + With default of MULA == 6, and DIVA == 1, + PLL is running at 7 times of main clock. + +config SOC_ATMEL_SAM3X_WAIT_MODE + bool "Atmel SAM3 goes to Wait mode instead of Sleep mode" + depends on SOC_ATMEL_SAM3_EXT_MAINCK + default y if DEBUG + help + For JTAG debugging CPU clock (HCLK) should not stop. In order + to achieve this, make CPU go to Wait mode instead of Sleep + mode while using external crystal oscillator for main clock. + +endif # SOC_SERIES_SAM3X diff --git a/arch/arm/soc/atmel_sam/sam3x/Makefile b/arch/arm/soc/atmel_sam/sam3x/Makefile new file mode 100644 index 000000000..11934ad20 --- /dev/null +++ b/arch/arm/soc/atmel_sam/sam3x/Makefile @@ -0,0 +1,9 @@ +# Makefile - Atmel SAM3X MCU series +# +# Copyright (c) 2017 Justin Watson +# SPDX-License-Identifier: Apache-2.0 +# + +ZEPHYRINCLUDE += -I$(srctree)/arch/arm/soc/atmel_sam/common + +obj-y += soc.o diff --git a/arch/arm/soc/atmel_sam/sam3x/linker.ld b/arch/arm/soc/atmel_sam/sam3x/linker.ld new file mode 100644 index 000000000..b6ccb0279 --- /dev/null +++ b/arch/arm/soc/atmel_sam/sam3x/linker.ld @@ -0,0 +1,9 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/arch/arm/soc/atmel_sam/sam3x/soc.c b/arch/arm/soc/atmel_sam/sam3x/soc.c new file mode 100644 index 000000000..1e8b01fb4 --- /dev/null +++ b/arch/arm/soc/atmel_sam/sam3x/soc.c @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Atmel SAM3X series processor + * + * This module provides routines to initialize and support board-level hardware + * for the Atmel SAM3X series processor. + */ + +#include +#include +#include +#include + +#include +#include + +/** + * @brief Setup various clock on SoC. + * + * Setup the SoC clocks according to section 28.12 in datasheet. + * + * Assumption: + * SLCK = 32.768kHz + */ +static ALWAYS_INLINE void clock_init(void) +{ + u32_t tmp; + + /* Note: + * Magic numbers below are obtained by reading the registers + * when the SoC was running the SAM-BA bootloader + * (with reserved bits set to 0). + */ + +#ifdef CONFIG_SOC_ATMEL_SAM3X_EXT_SLCK + /* This part is to switch the slow clock to using + * the external 32 kHz crystal oscillator. + */ + + /* Select external crystal */ + __SUPC->cr = SUPC_CR_KEY | SUPC_CR_XTALSEL; + + /* Wait for oscillator to be stablized */ + while (!(__SUPC->sr & SUPC_SR_OSCSEL)) + ; +#endif /* CONFIG_SOC_ATMEL_SAM3_EXT_SLCK */ + +#ifdef CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK + /* Start the external main oscillator */ + __PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_4MHZ + | PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN + | PMC_CKGR_MOR_MOSCXTST; + + /* Wait for main oscillator to be stablized */ + while (!(__PMC->sr & PMC_INT_MOSCXTS)) + ; + + /* Select main oscillator as source since it is more accurate + * according to datasheet. + */ + __PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_4MHZ + | PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN + | PMC_CKGR_MOR_MOSCXTST | PMC_CKGR_MOR_MOSCSEL; + + /* Wait for main oscillator to be selected */ + while (!(__PMC->sr & PMC_INT_MOSCSELS)) + ; +#ifdef CONFIG_SOC_ATMEL_SAM3X_WAIT_MODE + /* + * Instruct CPU enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG + */ + __PMC->fsmr |= PMC_FSMR_LPM; +#endif +#else + /* Set main fast RC oscillator to 12 MHz */ + __PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_12MHZ + | PMC_CKGR_MOR_MOSCRCEN; + + /* Wait for main fast RC oscillator to be stablized */ + while (!(__PMC->sr & PMC_INT_MOSCRCS)) + ; +#endif /* CONFIG_SOC_ATMEL_SAM3_EXT_MAINCK */ + + /* Use PLLA as master clock. + * According to datasheet, PMC_MCKR must not be programmed in + * a single write operation. So it seems the safe way is to + * get the system to use main clock (by setting CSS). Then set + * the prescaler (PRES). Finally setting it back to using PLL. + */ + + /* Switch to main clock first so we can setup PLL */ + tmp = __PMC->mckr & ~PMC_MCKR_CSS_MASK; + __PMC->mckr = tmp | PMC_MCKR_CSS_MAIN; + + /* Wait for clock selection complete */ + while (!(__PMC->sr & PMC_INT_MCKRDY)) + ; + + /* Setup PLLA */ + __PMC->ckgr_pllar = PMC_CKGR_PLLAR_DIVA | PMC_CKGR_PLLAR_ONE + | PMC_CKGR_PLLAR_MULA + | PMC_CKGR_PLLAR_PLLACOUNT; + + /* Wait for PLL lock */ + while (!(__PMC->sr & PMC_INT_LOCKA)) + ; + + /* Setup prescaler */ + tmp = __PMC->mckr & ~PMC_MCKR_PRES_MASK; + __PMC->mckr = tmp | PMC_MCKR_PRES_CLK; + + /* Wait for main clock setup complete */ + while (!(__PMC->sr & PMC_INT_MCKRDY)) + ; + + /* Finally select PLL as clock source */ + tmp = __PMC->mckr & ~PMC_MCKR_CSS_MASK; + __PMC->mckr = tmp | PMC_MCKR_CSS_PLLA; + + /* Wait for main clock setup complete */ + while (!(__PMC->sr & PMC_INT_MCKRDY)) + ; +} + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int atmel_sam3x_init(struct device *arg) +{ + u32_t key; + + ARG_UNUSED(arg); + + /* Note: + * Magic numbers below are obtained by reading the registers + * when the SoC was running the SAM-BA bootloader + * (with reserved bits set to 0). + */ + + key = irq_lock(); + + /* Setup the flash controller. + * The bootloader is running @ 48 MHz with + * FWS == 2. + * When running at 84 MHz, FWS == 4 seems + * to be more stable, and allows the board + * to boot. + */ + __EEFC0->fmr = 0x00000400; + __EEFC1->fmr = 0x00000400; + + _ClearFaults(); + + /* Setup master clock */ + clock_init(); + + /* Disable watchdog timer, not used by system */ + __WDT->mr |= WDT_DISABLE; + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + irq_unlock(key); + + return 0; +} + +SYS_INIT(atmel_sam3x_init, PRE_KERNEL_1, 0); diff --git a/arch/arm/soc/atmel_sam/sam3x/soc.h b/arch/arm/soc/atmel_sam/sam3x/soc.h new file mode 100644 index 000000000..74fad28b1 --- /dev/null +++ b/arch/arm/soc/atmel_sam/sam3x/soc.h @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Atmel SAM3X family processors. + */ + +#ifndef _ATMEL_SAM3X_SOC_H_ +#define _ATMEL_SAM3X_SOC_H_ + +/* IRQ numbers (from section 9.1, Peripheral Identifiers). */ +#define IRQ_SUPC 0 /* Supply Controller */ +#define IRQ_RSTC 1 /* Reset Controller */ +#define IRQ_RTC 2 /* Real-time Clock */ +#define IRQ_RTT 3 /* Real-time Timer */ +#define IRQ_WDG 4 /* Watchdog Timer */ +#define IRQ_PMC 5 /* Power Management Controller */ +#define IRQ_EEFC0 6 /* Enhanced Embedded Flash Controller 0 */ +#define IRQ_EEFC1 7 /* Enhanced Embedded Flash Controller 1 */ +#define IRQ_UART 8 /* UART */ +#define IRQ_PIOA 11 /* Parallel IO Controller A */ +#define IRQ_PIOB 12 /* Parallel IO Controller B */ +#define IRQ_PIOC 13 /* Parallel IO Controller C */ +#define IRQ_PIOD 14 /* Parallel IO Controller D */ +#define IRQ_PIOE 15 /* Parallel IO Controller E */ +#define IRQ_PIOF 16 /* Parallel IO Controller F */ +#define IRQ_USART0 17 /* USART #0 */ +#define IRQ_USART1 18 /* USART #1 */ +#define IRQ_USART2 19 /* USART #2 */ +#define IRQ_USART3 20 /* USART #3 */ +#define IRQ_HSMCI 21 /* High Speed Multimedia Card Interface */ +#define IRQ_TWI0 22 /* Two-wire Interface #0 */ +#define IRQ_TWI1 23 /* Two-wire Interface #1 */ +#define IRQ_SPI0 24 /* SPI #0 */ +#define IRQ_SPI1 25 /* SPI #1 */ +#define IRQ_SSC 26 /* Synchronous Serial Controller */ +#define IRQ_TC0 27 /* Timer Counter Channel #0 */ +#define IRQ_TC1 28 /* Timer Counter Channel #1 */ +#define IRQ_TC2 29 /* Timer Counter Channel #2 */ +#define IRQ_TC3 30 /* Timer Counter Channel #3 */ +#define IRQ_TC4 31 /* Timer Counter Channel #4 */ +#define IRQ_TC5 32 /* Timer Counter Channel #5 */ +#define IRQ_TC6 33 /* Timer Counter Channel #6 */ +#define IRQ_TC7 34 /* Timer Counter Channel #7 */ +#define IRQ_TC8 35 /* Timer Counter Channel #8 */ +#define IRQ_PWM 36 /* PWM Controller */ +#define IRQ_ADC 37 /* ADC Controller */ +#define IRQ_DACC 38 /* DAC Controller */ +#define IRQ_DMAC 39 /* DMA Controller */ +#define IRQ_UOTGHS 40 /* USB OTG High Speed */ +#define IRQ_TRNG 41 /* True Random Number Generator */ +#define IRQ_EMAC 42 /* Ehternet MAC */ +#define IRQ_CAN0 43 /* CAN Controller #0 */ +#define IRQ_CAN1 44 /* CAN Controller #1 */ + +/* PID: Peripheral IDs (from section 9.1, Peripheral Identifiers). + * PMC uses PIDs to enable clock for peripherals. + */ +#define PID_RTC 2 /* Real-time Clock */ +#define PID_RTT 3 /* Real-time Timer */ +#define PID_WDG 4 /* Watchdog Timer */ +#define PID_PMC 5 /* Power Management Controller */ +#define PID_EEFC0 6 /* Enhanced Embedded Flash Controller 0 */ +#define PID_EEFC1 7 /* Enhanced Embedded Flash Controller 1 */ +#define PID_UART 8 /* UART */ +#define PID_PIOA 11 /* Parallel IO Controller A */ +#define PID_PIOB 12 /* Parallel IO Controller B */ +#define PID_PIOC 13 /* Parallel IO Controller C */ +#define PID_PIOD 14 /* Parallel IO Controller D */ +#define PID_PIOE 15 /* Parallel IO Controller E */ +#define PID_PIOF 16 /* Parallel IO Controller F */ +#define PID_USART0 17 /* USART #0 */ +#define PID_USART1 18 /* USART #1 */ +#define PID_USART2 19 /* USART #2 */ +#define PID_USART3 20 /* USART #3 */ +#define PID_HSMCI 21 /* High Speed Multimedia Card Interface */ +#define PID_TWI0 22 /* Two-wire Interface #0 */ +#define PID_TWI1 23 /* Two-wire Interface #1 */ +#define PID_SPI0 24 /* SPI #0 */ +#define PID_SPI1 25 /* SPI #1 */ +#define PID_SSC 26 /* Synchronous Serial Controller */ +#define PID_TC0 27 /* Timer Counter Channel #0 */ +#define PID_TC1 28 /* Timer Counter Channel #1 */ +#define PID_TC2 29 /* Timer Counter Channel #2 */ +#define PID_TC3 30 /* Timer Counter Channel #3 */ +#define PID_TC4 31 /* Timer Counter Channel #4 */ +#define PID_TC5 32 /* Timer Counter Channel #5 */ +#define PID_TC6 33 /* Timer Counter Channel #6 */ +#define PID_TC7 34 /* Timer Counter Channel #7 */ +#define PID_TC8 35 /* Timer Counter Channel #8 */ +#define PID_PWM 36 /* PWM Controller */ +#define PID_ADC 37 /* ADC Controller */ +#define PID_DACC 38 /* DAC Controller */ +#define PID_DMAC 39 /* DMA Controller */ +#define PID_UOTGHS 40 /* USB OTG High Speed */ +#define PID_TRNG 41 /* True Random Number Generator */ +#define PID_EMAC 42 /* Ehternet MAC */ +#define PID_CAN0 43 /* CAN Controller #0 */ +#define PID_CAN1 44 /* CAN Controller #1 */ + +/* Power Manager Controller */ +#define PMC_ADDR 0x400E0600 + +#define PMC_CKGR_UCKR_UPLLEN (1 << 16) +#define PMC_CKGR_UCKR_UPLLCOUNT (3 << 20) + +#define PMC_CKGR_MOR_KEY (0x37 << 16) +#define PMC_CKGR_MOR_MOSCXTST (0xFF << 8) +#define PMC_CKGR_MOR_MOSCXTEN (1 << 0) +#define PMC_CKGR_MOR_MOSCRCEN (1 << 3) +#define PMC_CKGR_MOR_MOSCRCF_4MHZ (0 << 4) +#define PMC_CKGR_MOR_MOSCRCF_8MHZ (1 << 4) +#define PMC_CKGR_MOR_MOSCRCF_12MHZ (2 << 4) +#define PMC_CKGR_MOR_MOSCSEL (1 << 24) + +#define PMC_CKGR_PLLAR_PLLACOUNT (0x3F << 8) +#define PMC_CKGR_PLLAR_ONE (1 << 29) + +/* + * PLL clock = Main * (MULA + 1) / DIVA + * + * By default, MULA == 6, DIVA == 1. + * With main crystal running at 12 MHz, + * PLL = 12 * (6 + 1) / 1 = 84 MHz + * + * With processor clock prescaler at 1, + * the processor clock is at 84 MHz. + */ +#define PMC_CKGR_PLLAR_MULA \ + ((CONFIG_SOC_ATMEL_SAM3X_PLLA_MULA) << 16) +#define PMC_CKGR_PLLAR_DIVA \ + ((CONFIG_SOC_ATMEL_SAM3X_PLLA_DIVA) << 0) + +#define PMC_MCKR_CSS_MASK (0x3) +#define PMC_MCKR_CSS_SLOW (0 << 0) +#define PMC_MCKR_CSS_MAIN (1 << 0) +#define PMC_MCKR_CSS_PLLA (2 << 0) +#define PMC_MCKR_CSS_UPLL (3 << 0) +#define PMC_MCKR_PRES_MASK (0x70) +#define PMC_MCKR_PRES_CLK (0 << 4) +#define PMC_MCKR_PRES_DIV2 (1 << 4) +#define PMC_MCKR_PRES_DIV4 (2 << 4) +#define PMC_MCKR_PRES_DIV8 (3 << 4) +#define PMC_MCKR_PRES_DIV16 (4 << 4) +#define PMC_MCKR_PRES_DIV32 (5 << 4) +#define PMC_MCKR_PRES_DIV64 (6 << 4) +#define PMC_MCKR_PRES_DIV3 (7 << 4) +#define PMC_MCKR_PLLADIV2 (1 << 12) +#define PMC_MCKR_UPLLDIV2 (1 << 13) + +#define PMC_FSMR_LPM (1 << 20) + +#define PMC_INT_MOSCXTS (1 << 0) +#define PMC_INT_LOCKA (1 << 1) +#define PMC_INT_MCKRDY (1 << 3) +#define PMC_INT_LOCKU (1 << 6) +#define PMC_INT_OSCSELS (1 << 7) +#define PMC_INT_PCKRDY0 (1 << 8) +#define PMC_INT_PCKRDY1 (1 << 9) +#define PMC_INT_PCKRDY2 (1 << 10) +#define PMC_INT_MOSCSELS (1 << 16) +#define PMC_INT_MOSCRCS (1 << 17) +#define PMC_INT_CFDEV (1 << 18) +#define PMC_INT_CFDS (1 << 19) +#define PMC_INT_FOS (1 << 20) + +/* UART */ +#define UART_ADDR 0x400E0800 + +/* EEFC */ +#define EEFC_BANK0_ADDR 0x400E0A00 +#define EEFC_BANK1_ADDR 0x400E0C00 + +/* Peripheral DMA Controller (PDC) */ +#define PDC_PTCR_RXTEN (1 << 0) +#define PDC_PTCR_RXTDIS (1 << 1) +#define PDC_PTCR_TXTEN (1 << 8) +#define PDC_PTCR_TXTDIS (1 << 9) + +/* PIO Controllers */ +#define PIOA_ADDR 0x400E0E00 +#define PIOB_ADDR 0x400E1000 +#define PIOC_ADDR 0x400E1200 +#define PIOD_ADDR 0x400E1400 +#define PIOE_ADDR 0x400E1600 +#define PIOF_ADDR 0x400E1800 + +/* Supply Controller (SUPC) */ +#define SUPC_ADDR 0x400E1A10 + +#define SUPC_CR_KEY (0xA5 << 24) +#define SUPC_CR_XTALSEL (1 << 3) + +#define SUPC_SR_OSCSEL (1 << 7) + +/* Two-wire Interface (TWI) */ +#define TWI0_ADDR 0x4008C000 +#define TWI1_ADDR 0x40090000 + +/* Watchdog timer (WDT) */ +#define WDT_ADDR 0x400E1A50 + +#define WDT_DISABLE (1 << 15) + +#ifndef _ASMLANGUAGE + +#include +#include +#include + +#include "soc_registers.h" + +/* uart configuration settings */ +#define UART_IRQ_FLAGS 0 + +/* EEFC Register struct */ +#define __EEFC0 ((volatile struct __eefc *)EEFC_BANK0_ADDR) +#define __EEFC1 ((volatile struct __eefc *)EEFC_BANK1_ADDR) + +/* PMC Register struct */ +#define __PMC ((volatile struct __pmc *)PMC_ADDR) + +/* PIO Registers struct */ +#define __PIOA ((volatile struct __pio *)PIOA_ADDR) +#define __PIOB ((volatile struct __pio *)PIOB_ADDR) +#define __PIOC ((volatile struct __pio *)PIOC_ADDR) +#define __PIOD ((volatile struct __pio *)PIOD_ADDR) +#define __PIOE ((volatile struct __pio *)PIOE_ADDR) +#define __PIOF ((volatile struct __pio *)PIOF_ADDR) + +/* Supply Controller Register struct */ +#define __SUPC ((volatile struct __supc *)SUPC_ADDR) + +/* Two-wire Interface (TWI) */ +#define __TWI0 ((volatile struct __twi *)TWI0_ADDR) +#define __TWI1 ((volatile struct __twi *)TWI1_ADDR) + +/* Watchdog timer (WDT) */ +#define __WDT ((volatile struct __wdt *)WDT_ADDR) + +#endif /* !_ASMLANGUAGE */ + +#endif /* _ATMEL_SAM3X_SOC_H_ */ diff --git a/arch/arm/soc/atmel_sam/sam3x/soc_registers.h b/arch/arm/soc/atmel_sam/sam3x/soc_registers.h new file mode 100644 index 000000000..637e60a05 --- /dev/null +++ b/arch/arm/soc/atmel_sam/sam3x/soc_registers.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2016 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Atmel SAM3X family processors. + * + * Refer to the datasheet for more information about these registers. + */ + +#ifndef _ATMEL_SAM3_SOC_REGS_H_ +#define _ATMEL_SAM3_SOC_REGS_H_ + +/* Peripheral DMA Controller + * + * DO NOT USE DIRECTLY! This is to be used within individual + * peripheral's register struct. + * + * Starts at offset 0x100. + */ +struct __pdc { + u32_t rpr; /* 0x100 Receive Pointer */ + u32_t rcr; /* 0x104 Receive Counter */ + u32_t tpr; /* 0x108 Transmit Pointer */ + u32_t tcr; /* 0x10C Transmit Counter */ + u32_t rnpr; /* 0x110 Receive Next Pointer */ + u32_t rncr; /* 0x114 Receive Next Counter */ + u32_t tnpr; /* 0x118 Transmit Next Pointer */ + u32_t tncr; /* 0x11C Transmit Next Counter */ + u32_t ptcr; /* 0x120 Transfer Control */ + u32_t ptsr; /* 0x124 Transfer Status */ +}; + +/* Enhanced Embedded Flash Controller */ +struct __eefc { + u32_t fmr; /* 0x00 Flash Mode Register */ + u32_t fcr; /* 0x04 Flash Command Register */ + u32_t fsr; /* 0x08 Flash Status Register */ + u32_t frr; /* 0x0C Flash Result Register */ +}; + +/* PIO Controller */ +struct __pio { + u32_t per; /* 0x00 Enable */ + u32_t pdr; /* 0x04 Disable */ + u32_t psr; /* 0x08 Status */ + + u32_t res0; /* 0x0C reserved */ + + u32_t oer; /* 0x10 Output Enable */ + u32_t odr; /* 0x14 Output Disable */ + u32_t osr; /* 0x18 Output Status */ + + u32_t res1; /* 0x1C reserved */ + + u32_t ifer; /* 0x20 Glitch Input Filter Enable */ + u32_t ifdr; /* 0x24 Glitch Input Filter Disable */ + u32_t ifsr; /* 0x28 Glitch Input Fitler Status */ + + u32_t res2; /* 0x2C reserved */ + + u32_t sodr; /* 0x30 Set Output Data */ + u32_t codr; /* 0x34 Clear Output Data */ + u32_t odsr; /* 0x38 Output Data Status */ + u32_t pdsr; /* 0x3C Pin Data Status */ + + u32_t ier; /* 0x40 Interrupt Enable */ + u32_t idr; /* 0x44 Interrupt Disable */ + u32_t imr; /* 0x48 Interrupt Mask */ + u32_t isr; /* 0x4C Interrupt Status */ + + u32_t mder; /* 0x50 Multi-driver Enable */ + u32_t mddr; /* 0x54 Multi-driver Disable */ + u32_t mdsr; /* 0x58 Multi-driver Status */ + + u32_t res3; /* 0x5C reserved */ + + u32_t pudr; /* 0x60 Pull-up Disable */ + u32_t puer; /* 0x64 Pull-up Enable */ + u32_t pusr; /* 0x68 Pad Pull-up Status */ + + u32_t res4; /* 0x6C reserved */ + + u32_t absr; /* 0x70 Peripheral AB Select */ + + u32_t res5[3]; /* 0x74-0x7C reserved */ + + u32_t scifsr; /* 0x80 System Clock Glitch Input */ + /* Filter Select */ + + u32_t difsr; /* 0x84 Debouncing Input Filter */ + /* Select */ + + u32_t ifdgsr; /* 0x88 Glitch or Debouncing Input */ + /* Filter Clock Selection */ + /* Status */ + + u32_t scdr; /* 0x8C Slow Clock Divider Debounce */ + + u32_t res6[4]; /* 0x90-0x9C reserved */ + + u32_t ower; /* 0xA0 Output Write Enable */ + u32_t owdr; /* 0xA4 Output Write Disable */ + u32_t owsr; /* 0xA8 Output Write Status */ + + u32_t res7; /* 0xAC reserved */ + + u32_t aimer; /* 0xB0 Additional Interrupt Modes */ + /* Enable */ + u32_t aimdr; /* 0xB4 Additional Interrupt Modes */ + /* Disable */ + u32_t aimmr; /* 0xB8 Additional Interrupt Modes */ + /* Mask */ + + u32_t res8; /* 0xBC reserved */ + + u32_t esr; /* 0xC0 Edge Select */ + u32_t lsr; /* 0xC4 Level Select */ + u32_t elsr; /* 0xC8 Edge/Level Status */ + + u32_t res9; /* 0xCC reserved */ + + u32_t fellsr; /* 0xD0 Falling Edge/Low Level Sel */ + u32_t rehlsr; /* 0xD4 Rising Edge/High Level Sel */ + u32_t frlhsr; /* 0xD8 Fall/Rise - Low/High Status */ + + u32_t res10; /* 0xDC reserved */ + + u32_t locksr; /* 0xE0 Lock Status */ + + u32_t wpmr; /* 0xE4 Write Protect Mode */ + u32_t wpsr; /* 0xE8 Write Protect Status */ +}; + +/* Power Management Controller */ +struct __pmc { + u32_t scer; /* 0x00 System Clock Enable */ + u32_t scdr; /* 0x04 System Clock Disable */ + u32_t scsr; /* 0x08 System Clock Status */ + + u32_t res0; /* 0x0C reserved */ + + u32_t pcer0; /* 0x10 Peripheral Clock Enable 0 */ + u32_t pcdr0; /* 0x14 Peripheral Clock Disable 0 */ + u32_t pcsr0; /* 0x18 Peripheral Clock Status 0 */ + + u32_t ckgr_uckr; /* 0x1C UTMI Clock */ + u32_t ckgr_mor; /* 0x20 Main Oscillator */ + u32_t ckgr_mcfr; /* 0x24 Main Clock Freq. */ + u32_t ckgr_pllar; /* 0x28 PLLA */ + + u32_t res1; /* 0x2C reserved */ + + u32_t mckr; /* 0x30 Master Clock */ + + u32_t res2; /* 0x34 reserved */ + + u32_t usb; /* 0x38 USB Clock */ + + u32_t res3; /* 0x3C reserved */ + + u32_t pck0; /* 0x40 Programmable Clock 0 */ + u32_t pck1; /* 0x44 Programmable Clock 1 */ + u32_t pck2; /* 0x48 Programmable Clock 2 */ + + u32_t res4[5]; /* 0x4C-0x5C reserved */ + + u32_t ier; /* 0x60 Interrupt Enable */ + u32_t idr; /* 0x64 Interrupt Disable */ + u32_t sr; /* 0x68 Status */ + u32_t imr; /* 0x6C Interrupt Mask */ + + u32_t fsmr; /* 0x70 Fast Startup Mode */ + u32_t fspr; /* 0x74 Fast Startup Polarity */ + + u32_t focr; /* 0x78 Fault Outpu Clear */ + + u32_t res5[26]; /* 0x7C-0xE0 reserved */ + + u32_t wpmr; /* 0xE4 Write Protect Mode */ + u32_t wpsr; /* 0xE8 Write Protect Status */ + + u32_t res6[5]; /* 0xEC-0xFC reserved */ + + u32_t pcer1; /* 0x100 Peripheral Clock Enable 1 */ + u32_t pcdr1; /* 0x104 Peripheral Clock Disable 1 */ + u32_t pcsr1; /* 0x108 Peripheral Clock Status 1 */ + + u32_t pcr; /* 0x10C Peripheral Control */ +}; + +/* Supply Controller (SUPC) */ +struct __supc { + u32_t cr; /* 0x00 Control */ + u32_t smmr; /* 0x04 Supply Monitor Mode */ + u32_t mr; /* 0x08 Mode */ + u32_t wumr; /* 0x0C Wake Up Mode */ + u32_t wuir; /* 0x10 Wake Up Inputs */ + u32_t sr; /* 0x14 Status */ +}; + +/* Two-wire Interface (TWI), aka I2C */ +struct __twi { + u32_t cr; /* 0x00 Control */ + u32_t mmr; /* 0x04 Master Mode */ + u32_t smr; /* 0x08 Slave Mode */ + u32_t iadr; /* 0x0C Internal Address */ + u32_t cwgr; /* 0x10 Clock Waveform Generator */ + + u32_t rev0[3]; /* 0x14-0x1C reserved */ + + u32_t sr; /* 0x20 Status */ + + u32_t ier; /* 0x24 Interrupt Enable */ + u32_t idr; /* 0x28 Interrupt Disable */ + u32_t imr; /* 0x2C Interrupt Mask */ + + u32_t rhr; /* 0x30 Receive Holding */ + u32_t thr; /* 0x34 Transmit Holding */ + + u32_t rev1[50]; /* 0x38-0xFC Reserved */ + + struct __pdc pdc; /* 0x100 - 0x124 PDC */ +}; + +/* Watchdog timer (WDT) */ +struct __wdt { + u32_t cr; /* 0x00 Control Register */ + u32_t mr; /* 0x04 Mode Register */ + u32_t sr; /* 0x08 Status Register */ +}; + +#endif /* _ATMEL_SAM3_SOC_REGS_H_ */ -- cgit v1.2.3