ARM: Hi3620: simplify the div-clk driver for Hi3620

Simplify the divider clock driver for hi3620 SoC by optimizing the
div-table in DTS file.

Signed-off-by: LiXin <li.xin@linaro.org>

2 files changed, 21 insertions, 58 deletions

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index 2974dbaef18..1636e4b3726 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -876,23 +876,12 @@
 				clock-output-names = "clk_edc1";
 				hisilicon,hi3620-clkgate = <0x30 0x400>;
 			};
-			dtable: clkdiv@0 {
-				#hisilicon,clkdiv-table-cells = <2>;
- 			};
 			div_shareaxi: clkdiv@1 {
 				compatible = "hisilicon,hi3620-clk-div";
 				#clock-cells = <0>;
 				clocks = <&refclk_shareAXI>;
 				clock-output-names = "shareAXI_div";
-				hisilicon,clkdiv-table = <
-					&dtable 0 1 &dtable 1 2 &dtable 2 3 &dtable 3 4
-					&dtable 4 5 &dtable 5 6 &dtable 6 7 &dtable 7 8
-					&dtable 8 9 &dtable 9 10 &dtable 10 11 &dtable 11 12
-					&dtable 12 13 &dtable 13 14 &dtable 14 15 &dtable 15 16
-					&dtable 16 17 &dtable 17 18 &dtable 18 19 &dtable 19 20
-					&dtable 20 21 &dtable 21 22 &dtable 22 23 &dtable 23 24
-					&dtable 24 25 &dtable 25 26 &dtable 26 27 &dtable 27 28
-					&dtable 28 29 &dtable 29 30 &dtable 30 31 &dtable 31 32>;
+				hisilicon,clkdiv-table = <32 1>;
 				/* divider register offset, mask */
 				hisilicon,clkdiv = <0x100 0x1f>;
 			};
@@ -901,59 +890,35 @@
 				#clock-cells = <0>;
 				clocks = <&div_shareaxi>;
 				clock-output-names = "cfgAXI_div";
-				hisilicon,clkdiv-table = <&dtable 0x01 2>;
+				hisilicon,clkdiv-table = <2 2>;
 				hisilicon,clkdiv = <0x100 0x60>;
  			};
 			div_mmc1: clkdiv@3 {
 				compatible = "hisilicon,hi3620-clk-div";
 				#clock-cells = <0>;
 				clocks = <&refclk_mmc1>;
-				hisilicon,clkdiv-table = <
-					&dtable 0xf 16 &dtable 0xe 15 &dtable 0xd 14
-					&dtable 0xc 13 &dtable 0xb 12 &dtable 0xa 11
-					&dtable 9 10 &dtable 8 9 &dtable 7 8
-					&dtable 6 7 &dtable 5 6 &dtable 4 5
-					&dtable 3 4 &dtable 2 3 &dtable 1 2
-					&dtable 0 1>;
+				hisilicon,clkdiv-table = <16 1>;
 				hisilicon,clkdiv = <0x108 0x1e0>;
 			};
 			div_mmc2: clkdiv@4 {
 				compatible = "hisilicon,hi3620-clk-div";
 				#clock-cells = <0>;
 				clocks = <&refclk_mmc2>;
-				hisilicon,clkdiv-table = <
-					&dtable 0xf 16 &dtable 0xe 15 &dtable 0xd 14
-					&dtable 0xc 13 &dtable 0xb 12 &dtable 0xa 11
-					&dtable 9 10 &dtable 8 9 &dtable 7 8
-					&dtable 6 7 &dtable 5 6 &dtable 4 5
-					&dtable 3 4 &dtable 2 3 &dtable 1 2
-					&dtable 0 1>;
+				hisilicon,clkdiv-table = <16 1>;
 				hisilicon,clkdiv = <0x140 0xf>;
 			};
 			div_mmc3: clkdiv@5 {
 				compatible = "hisilicon,hi3620-clk-div";
 				#clock-cells = <0>;
 				clocks = <&refclk_mmc3>;
-				hisilicon,clkdiv-table = <
-					&dtable 0xf 16 &dtable 0xe 15 &dtable 0xd 14
-					&dtable 0xc 13 &dtable 0xb 12 &dtable 0xa 11
-					&dtable 9 10 &dtable 8 9 &dtable 7 8
-					&dtable 6 7 &dtable 5 6 &dtable 4 5
-					&dtable 3 4 &dtable 2 3 &dtable 1 2
-					&dtable 0 1>;
+				hisilicon,clkdiv-table = <16 1>;
 				hisilicon,clkdiv = <0x140 0x1e0>;
 			};
 			div_sd: clkdiv@6 {
 				compatible = "hisilicon,hi3620-clk-div";
 				#clock-cells = <0>;
 				clocks = <&refclk_sd>;
-				hisilicon,clkdiv-table = <
-					&dtable 0xf 16 &dtable 0xe 15 &dtable 0xd 14
-					&dtable 0xc 13 &dtable 0xb 12 &dtable 0xa 11
-					&dtable 9 10 &dtable 8 9 &dtable 7 8
-					&dtable 6 7 &dtable 5 6 &dtable 4 5
-					&dtable 3 4 &dtable 2 3 &dtable 1 2
-					&dtable 0 1>;
+				hisilicon,clkdiv-table = <16 1>;
 				hisilicon,clkdiv = <0x108 0xf>;
 			};
 		};
diff --git a/drivers/clk/hisilicon/clk-hi3xxx.c b/drivers/clk/hisilicon/clk-hi3xxx.c
index 9682517edfd..72115a5763b 100644
--- a/drivers/clk/hisilicon/clk-hi3xxx.c
+++ b/drivers/clk/hisilicon/clk-hi3xxx.c
@@ -561,8 +561,7 @@ void __init hi3620_clkdiv_setup(struct device_node *np)
 	unsigned int table_num;
 	int i;
 	u32 data[2];
-	const char *propname = "hisilicon,clkdiv-table";
-	const char *cellname = "#hisilicon,clkdiv-table-cells";
+    unsigned int max_div, min_div;
 	struct of_phandle_args div_table;
 
 	reg_base = hs_init_clocks(np);
@@ -571,31 +570,29 @@ void __init hi3620_clkdiv_setup(struct device_node *np)
 
 	if (of_property_read_string(np, "clock-output-names", &clk_name))
 		return;
-	if (of_property_read_u32_array(np, "hisilicon,clkdiv",
+
+    /*process the div_table*/
+    if (of_property_read_u32_array(np, "hisilicon,clkdiv-table",
 				       &data[0], 2))
 		return;
 
-	/*process the div_table*/
-	for (i = 0; ; i++) {
-		if (of_parse_phandle_with_args(np, propname, cellname,
-					       i, &div_table))
-			break;
-	}
+    max_div = (u8)data[0];
+    min_div = (u8)data[1];
+
+	if (of_property_read_u32_array(np, "hisilicon,clkdiv",
+                       &data[0], 2))
+        return;
 
 	/*table ends with <0, 0>, so plus one to table_num*/
-	table_num = i + 1;
+	table_num = max_div - min_div + 1;
 
 	table = kzalloc(sizeof(struct clk_div_table) * table_num, GFP_KERNEL);
 	if (!table)
 		return ;
 
-	for (i = 0; ; i++) {
-		if (of_parse_phandle_with_args(np, propname, cellname,
-					       i, &div_table))
-			break;
-
-		table[i].val = div_table.args[0];
-		table[i].div = div_table.args[1];
+	for (i = 0; i < table_num; i++) {
+		table[i].div = min_div + i;
+		table[i].val = table[i].div - 1;
 	}
 
 	/* gate only has the fixed parent */
@@ -626,6 +623,7 @@ void __init hi3620_clkdiv_setup(struct device_node *np)
 	if (IS_ERR(clk))
 		goto err_clk;
 	of_clk_add_provider(np, of_clk_src_simple_get, clk);
+	clk_register_clkdev(clk, clk_name, NULL);
 	return;
 err_clk:
 	kfree(init);