diff options
Diffstat (limited to 'arch/arm/boot/dts/hi3620.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 47 |
1 files changed, 6 insertions, 41 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 2974dbaef18..1636e4b3726 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -876,23 +876,12 @@ clock-output-names = "clk_edc1"; hisilicon,hi3620-clkgate = <0x30 0x400>; }; - dtable: clkdiv@0 { - #hisilicon,clkdiv-table-cells = <2>; - }; div_shareaxi: clkdiv@1 { compatible = "hisilicon,hi3620-clk-div"; #clock-cells = <0>; clocks = <&refclk_shareAXI>; clock-output-names = "shareAXI_div"; - hisilicon,clkdiv-table = < - &dtable 0 1 &dtable 1 2 &dtable 2 3 &dtable 3 4 - &dtable 4 5 &dtable 5 6 &dtable 6 7 &dtable 7 8 - &dtable 8 9 &dtable 9 10 &dtable 10 11 &dtable 11 12 - &dtable 12 13 &dtable 13 14 &dtable 14 15 &dtable 15 16 - &dtable 16 17 &dtable 17 18 &dtable 18 19 &dtable 19 20 - &dtable 20 21 &dtable 21 22 &dtable 22 23 &dtable 23 24 - &dtable 24 25 &dtable 25 26 &dtable 26 27 &dtable 27 28 - &dtable 28 29 &dtable 29 30 &dtable 30 31 &dtable 31 32>; + hisilicon,clkdiv-table = <32 1>; /* divider register offset, mask */ hisilicon,clkdiv = <0x100 0x1f>; }; @@ -901,59 +890,35 @@ #clock-cells = <0>; clocks = <&div_shareaxi>; clock-output-names = "cfgAXI_div"; - hisilicon,clkdiv-table = <&dtable 0x01 2>; + hisilicon,clkdiv-table = <2 2>; hisilicon,clkdiv = <0x100 0x60>; }; div_mmc1: clkdiv@3 { compatible = "hisilicon,hi3620-clk-div"; #clock-cells = <0>; clocks = <&refclk_mmc1>; - hisilicon,clkdiv-table = < - &dtable 0xf 16 &dtable 0xe 15 &dtable 0xd 14 - &dtable 0xc 13 &dtable 0xb 12 &dtable 0xa 11 - &dtable 9 10 &dtable 8 9 &dtable 7 8 - &dtable 6 7 &dtable 5 6 &dtable 4 5 - &dtable 3 4 &dtable 2 3 &dtable 1 2 - &dtable 0 1>; + hisilicon,clkdiv-table = <16 1>; hisilicon,clkdiv = <0x108 0x1e0>; }; div_mmc2: clkdiv@4 { compatible = "hisilicon,hi3620-clk-div"; #clock-cells = <0>; clocks = <&refclk_mmc2>; - hisilicon,clkdiv-table = < - &dtable 0xf 16 &dtable 0xe 15 &dtable 0xd 14 - &dtable 0xc 13 &dtable 0xb 12 &dtable 0xa 11 - &dtable 9 10 &dtable 8 9 &dtable 7 8 - &dtable 6 7 &dtable 5 6 &dtable 4 5 - &dtable 3 4 &dtable 2 3 &dtable 1 2 - &dtable 0 1>; + hisilicon,clkdiv-table = <16 1>; hisilicon,clkdiv = <0x140 0xf>; }; div_mmc3: clkdiv@5 { compatible = "hisilicon,hi3620-clk-div"; #clock-cells = <0>; clocks = <&refclk_mmc3>; - hisilicon,clkdiv-table = < - &dtable 0xf 16 &dtable 0xe 15 &dtable 0xd 14 - &dtable 0xc 13 &dtable 0xb 12 &dtable 0xa 11 - &dtable 9 10 &dtable 8 9 &dtable 7 8 - &dtable 6 7 &dtable 5 6 &dtable 4 5 - &dtable 3 4 &dtable 2 3 &dtable 1 2 - &dtable 0 1>; + hisilicon,clkdiv-table = <16 1>; hisilicon,clkdiv = <0x140 0x1e0>; }; div_sd: clkdiv@6 { compatible = "hisilicon,hi3620-clk-div"; #clock-cells = <0>; clocks = <&refclk_sd>; - hisilicon,clkdiv-table = < - &dtable 0xf 16 &dtable 0xe 15 &dtable 0xd 14 - &dtable 0xc 13 &dtable 0xb 12 &dtable 0xa 11 - &dtable 9 10 &dtable 8 9 &dtable 7 8 - &dtable 6 7 &dtable 5 6 &dtable 4 5 - &dtable 3 4 &dtable 2 3 &dtable 1 2 - &dtable 0 1>; + hisilicon,clkdiv-table = <16 1>; hisilicon,clkdiv = <0x108 0xf>; }; }; |