diff options
| author | Aravind Ganesan <aravindg@codeaurora.org> | 2014-10-10 16:47:00 -0600 |
|---|---|---|
| committer | Nicolas Dechesne <nicolas.dechesne@linaro.org> | 2014-11-19 23:42:29 +0100 |
| commit | a1f30f60e858168021e10a062f737f83366f7de2 (patch) | |
| tree | aa4934862b52908791114c24590a52da9573b0ee | |
| parent | 0969c170b77cf92da95c1968dd2fd3d6edb7bb42 (diff) | |
Added IOCTL support for getting the last-fence processed by GPU.freedreno/ifc6410-v2.0-drm
Change-Id: I355f97e43bf0dfa2c28914b2943f2b2d3c7c3be1
Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org>
| -rw-r--r-- | drivers/gpu/drm/msm/msm_drv.c | 20 | ||||
| -rw-r--r-- | include/uapi/drm/msm_drm.h | 12 |
2 files changed, 31 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 460d09b64f03..becf36563080 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -802,6 +802,25 @@ static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, &TS(args->timeout)); } +static int msm_ioctl_get_last_fence(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct msm_drm_private *priv = dev->dev_private; + struct drm_msm_get_last_fence *args = data; + struct msm_gpu *gpu = priv->gpu; + + if (!gpu) + return -ENXIO; + + if (args->pad) { + DRM_ERROR("invalid pad: %08x\n", args->pad); + return -EINVAL; + } + args->fence = gpu->funcs->last_fence(gpu); + + return 0; +} + static const struct drm_ioctl_desc msm_ioctls[] = { DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), @@ -810,6 +829,7 @@ static const struct drm_ioctl_desc msm_ioctls[] = { DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_GET_LAST_FENCE, msm_ioctl_get_last_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), }; static const struct vm_operations_struct vm_ops = { diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 0664c31f010c..0e099ccef9c5 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -196,6 +196,14 @@ struct drm_msm_wait_fence { struct drm_msm_timespec timeout; /* in */ }; +/* + * User space can get the last fence processed by the GPU + * */ +struct drm_msm_get_last_fence{ + uint32_t fence; /* out*/ + uint32_t pad; +}; + #define DRM_MSM_GET_PARAM 0x00 /* placeholder: #define DRM_MSM_SET_PARAM 0x01 @@ -206,7 +214,8 @@ struct drm_msm_wait_fence { #define DRM_MSM_GEM_CPU_FINI 0x05 #define DRM_MSM_GEM_SUBMIT 0x06 #define DRM_MSM_WAIT_FENCE 0x07 -#define DRM_MSM_NUM_IOCTLS 0x08 +#define DRM_MSM_GET_LAST_FENCE 0x08 +#define DRM_MSM_NUM_IOCTLS 0x09 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) @@ -215,5 +224,6 @@ struct drm_msm_wait_fence { #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) +#define DRM_IOCTL_MSM_GET_LAST_FENCE DRM_IOR (DRM_COMMAND_BASE + DRM_MSM_GET_LAST_FENCE, struct drm_msm_get_last_fence) #endif /* __MSM_DRM_H__ */ |