From 40dff8c89e0a28233bd50698670c0ee965437fc7 Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Wed, 12 Dec 2018 15:36:21 +0530 Subject: msm: camera: flash: Remove race condition in subdev close Subdev close is calling flash_shutdown() to flush req and release device operation. flash_subdev_close() does the mutex lock already. Removing same mutex lock opertion from flash_shutdown() function to remove race condition. Change-Id: Ib5fcb6f683b8c997121b3f4fb301eb34b76c2c1b Signed-off-by: Trishansh Bhardwaj --- .../platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c index ff385ca06528..8c075f576ce6 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c @@ -1565,9 +1565,7 @@ void cam_flash_shutdown(struct cam_flash_ctrl *fctrl) if ((fctrl->flash_state == CAM_FLASH_STATE_CONFIG) || (fctrl->flash_state == CAM_FLASH_STATE_START)) { - mutex_lock(&(fctrl->flash_mutex)); fctrl->func_tbl.flush_req(fctrl, FLUSH_ALL, 0); - mutex_unlock(&(fctrl->flash_mutex)); rc = fctrl->func_tbl.power_ops(fctrl, false); if (rc) CAM_ERR(CAM_FLASH, "Power Down Failed rc: %d", -- cgit v1.2.3 From c3bfeff361c3e488e91496299e22f155e5132506 Mon Sep 17 00:00:00 2001 From: Ping Li Date: Wed, 21 Mar 2018 17:08:28 -0700 Subject: drm/msm/sde: Add property for AD vsync count On command mode panel, vsync notification will triggered for each TE, not actual vsync commit. This change adds an AD property to track vsync event count for AD, so that AD feature can converge with the correct display commit count. Change-Id: I6c87ce989203f8bb121723465c661e2b2f27c179 Signed-off-by: Ping Li --- drivers/gpu/drm/msm/sde/sde_ad4.h | 1 + drivers/gpu/drm/msm/sde/sde_color_processing.c | 71 +++++++++++++++++++++++++- drivers/gpu/drm/msm/sde/sde_color_processing.h | 9 +++- drivers/gpu/drm/msm/sde/sde_crtc.c | 1 + drivers/gpu/drm/msm/sde/sde_crtc.h | 2 + drivers/gpu/drm/msm/sde/sde_hw_ad4.c | 34 ++++++++++++ 6 files changed, 116 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/sde/sde_ad4.h b/drivers/gpu/drm/msm/sde/sde_ad4.h index bf08360e9862..b254d7dc981e 100644 --- a/drivers/gpu/drm/msm/sde/sde_ad4.h +++ b/drivers/gpu/drm/msm/sde/sde_ad4.h @@ -52,6 +52,7 @@ enum ad_property { AD_IPC_SUSPEND, AD_IPC_RESUME, AD_IPC_RESET, + AD_VSYNC_UPDATE, AD_PROPMAX, }; diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.c b/drivers/gpu/drm/msm/sde/sde_color_processing.c index 8dc31d1e0872..0faae5a551bc 100644 --- a/drivers/gpu/drm/msm/sde/sde_color_processing.c +++ b/drivers/gpu/drm/msm/sde/sde_color_processing.c @@ -88,6 +88,7 @@ static void sde_cp_ad_set_prop(struct sde_crtc *sde_crtc, enum ad_property ad_prop); static void sde_cp_notify_hist_event(struct drm_crtc *crtc_drm, void *arg); +static void sde_cp_update_ad_vsync_prop(struct sde_crtc *sde_crtc, u32 val); #define setup_dspp_prop_install_funcs(func) \ do { \ @@ -138,6 +139,7 @@ enum { SDE_CP_CRTC_DSPP_AD_ASSERTIVENESS, SDE_CP_CRTC_DSPP_AD_BACKLIGHT, SDE_CP_CRTC_DSPP_AD_STRENGTH, + SDE_CP_CRTC_DSPP_AD_VSYNC_COUNT, SDE_CP_CRTC_DSPP_MAX, /* DSPP features end */ @@ -407,6 +409,7 @@ void sde_cp_crtc_init(struct drm_crtc *crtc) if (IS_ERR(sde_crtc->hist_blob)) sde_crtc->hist_blob = NULL; + sde_crtc->ad_vsync_count = 0; mutex_init(&sde_crtc->crtc_cp_lock); INIT_LIST_HEAD(&sde_crtc->active_list); INIT_LIST_HEAD(&sde_crtc->dirty_list); @@ -789,6 +792,9 @@ static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node, ad_cfg.prop = AD_MODE; ad_cfg.hw_cfg = &hw_cfg; hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg); + sde_crtc->ad_vsync_count = 0; + sde_cp_update_ad_vsync_prop(sde_crtc, + sde_crtc->ad_vsync_count); break; case SDE_CP_CRTC_DSPP_AD_INIT: if (!hw_dspp || !hw_dspp->ops.setup_ad) { @@ -798,6 +804,9 @@ static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node, ad_cfg.prop = AD_INIT; ad_cfg.hw_cfg = &hw_cfg; hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg); + sde_crtc->ad_vsync_count = 0; + sde_cp_update_ad_vsync_prop(sde_crtc, + sde_crtc->ad_vsync_count); break; case SDE_CP_CRTC_DSPP_AD_CFG: if (!hw_dspp || !hw_dspp->ops.setup_ad) { @@ -807,6 +816,9 @@ static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node, ad_cfg.prop = AD_CFG; ad_cfg.hw_cfg = &hw_cfg; hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg); + sde_crtc->ad_vsync_count = 0; + sde_cp_update_ad_vsync_prop(sde_crtc, + sde_crtc->ad_vsync_count); break; case SDE_CP_CRTC_DSPP_AD_INPUT: if (!hw_dspp || !hw_dspp->ops.setup_ad) { @@ -816,6 +828,9 @@ static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node, ad_cfg.prop = AD_INPUT; ad_cfg.hw_cfg = &hw_cfg; hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg); + sde_crtc->ad_vsync_count = 0; + sde_cp_update_ad_vsync_prop(sde_crtc, + sde_crtc->ad_vsync_count); break; case SDE_CP_CRTC_DSPP_AD_ASSERTIVENESS: if (!hw_dspp || !hw_dspp->ops.setup_ad) { @@ -825,6 +840,9 @@ static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node, ad_cfg.prop = AD_ASSERTIVE; ad_cfg.hw_cfg = &hw_cfg; hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg); + sde_crtc->ad_vsync_count = 0; + sde_cp_update_ad_vsync_prop(sde_crtc, + sde_crtc->ad_vsync_count); break; case SDE_CP_CRTC_DSPP_AD_BACKLIGHT: if (!hw_dspp || !hw_dspp->ops.setup_ad) { @@ -834,6 +852,9 @@ static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node, ad_cfg.prop = AD_BACKLIGHT; ad_cfg.hw_cfg = &hw_cfg; hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg); + sde_crtc->ad_vsync_count = 0; + sde_cp_update_ad_vsync_prop(sde_crtc, + sde_crtc->ad_vsync_count); break; case SDE_CP_CRTC_DSPP_AD_STRENGTH: if (!hw_dspp || !hw_dspp->ops.setup_ad) { @@ -843,6 +864,9 @@ static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node, ad_cfg.prop = AD_STRENGTH; ad_cfg.hw_cfg = &hw_cfg; hw_dspp->ops.setup_ad(hw_dspp, &ad_cfg); + sde_crtc->ad_vsync_count = 0; + sde_cp_update_ad_vsync_prop(sde_crtc, + sde_crtc->ad_vsync_count); break; default: ret = -EINVAL; @@ -924,10 +948,15 @@ void sde_cp_crtc_apply_properties(struct drm_crtc *crtc) DRM_DEBUG_DRIVER("Dirty list is empty\n"); goto exit; } - sde_cp_ad_set_prop(sde_crtc, AD_IPC_RESET); set_dspp_flush = true; } + if (!list_empty(&sde_crtc->ad_active)) { + sde_cp_ad_set_prop(sde_crtc, AD_IPC_RESET); + sde_cp_ad_set_prop(sde_crtc, AD_VSYNC_UPDATE); + sde_cp_update_ad_vsync_prop(sde_crtc, sde_crtc->ad_vsync_count); + } + list_for_each_entry_safe(prop_node, n, &sde_crtc->dirty_list, dirty_list) { sde_dspp_feature = crtc_feature_map[prop_node->feature]; @@ -1444,6 +1473,9 @@ static void dspp_ad_install_property(struct drm_crtc *crtc) "SDE_DSPP_AD_V4_BACKLIGHT", SDE_CP_CRTC_DSPP_AD_BACKLIGHT, 0, (BIT(16) - 1), 0); + sde_cp_crtc_install_range_property(crtc, + "SDE_DSPP_AD_V4_VSYNC_COUNT", + SDE_CP_CRTC_DSPP_AD_VSYNC_COUNT, 0, U32_MAX, 0); break; default: DRM_ERROR("version %d not supported\n", version); @@ -1862,6 +1894,11 @@ static void sde_cp_ad_set_prop(struct sde_crtc *sde_crtc, hw_cfg.displayh = num_mixers * hw_lm->cfg.out_width; hw_cfg.displayv = hw_lm->cfg.out_height; hw_cfg.mixer_info = hw_lm; + + if (ad_prop == AD_VSYNC_UPDATE) { + hw_cfg.payload = &sde_crtc->ad_vsync_count; + hw_cfg.len = sizeof(sde_crtc->ad_vsync_count); + } ad_cfg.prop = ad_prop; ad_cfg.hw_cfg = &hw_cfg; ret = hw_dspp->ops.validate_ad(hw_dspp, (u32 *)&ad_prop); @@ -2113,3 +2150,35 @@ int sde_cp_hist_interrupt(struct drm_crtc *crtc_drm, bool en, exit: return ret; } + +void sde_cp_update_ad_vsync_count(struct drm_crtc *crtc, u32 val) +{ + struct sde_crtc *sde_crtc; + + if (!crtc) { + DRM_ERROR("invalid crtc %pK\n", crtc); + return; + } + + sde_crtc = to_sde_crtc(crtc); + if (!sde_crtc) { + DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc); + return; + } + + sde_crtc->ad_vsync_count = val; + sde_cp_update_ad_vsync_prop(sde_crtc, val); +} + +static void sde_cp_update_ad_vsync_prop(struct sde_crtc *sde_crtc, u32 val) +{ + struct sde_cp_node *prop_node = NULL; + + list_for_each_entry(prop_node, &sde_crtc->feature_list, feature_list) { + if (prop_node->feature == SDE_CP_CRTC_DSPP_AD_VSYNC_COUNT) { + prop_node->prop_val = val; + pr_debug("AD vsync count updated to %d\n", val); + return; + } + } +} diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.h b/drivers/gpu/drm/msm/sde/sde_color_processing.h index 7eb173852611..620db26775a9 100644 --- a/drivers/gpu/drm/msm/sde/sde_color_processing.h +++ b/drivers/gpu/drm/msm/sde/sde_color_processing.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -146,4 +146,11 @@ void sde_cp_crtc_post_ipc(struct drm_crtc *crtc); */ int sde_cp_hist_interrupt(struct drm_crtc *crtc_drm, bool en, struct sde_irq_callback *hist_irq); + +/** + * sde_cp_update_ad_vsync_count: Api to update AD vsync count + * @crtc: Pointer to crtc. + * @val: vsync count value + */ +void sde_cp_update_ad_vsync_count(struct drm_crtc *crtc, u32 val); #endif /*_SDE_COLOR_PROCESSING_H */ diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c index 600bbec6631b..65145010a861 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.c +++ b/drivers/gpu/drm/msm/sde/sde_crtc.c @@ -4287,6 +4287,7 @@ static void sde_crtc_disable(struct drm_crtc *crtc) event.type = DRM_EVENT_CRTC_POWER; event.length = sizeof(u32); sde_cp_crtc_suspend(crtc); + sde_cp_update_ad_vsync_count(crtc, 0); power_on = 0; msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, (u8 *)&power_on); diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h index f5a814540b53..0a3de1842674 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.h +++ b/drivers/gpu/drm/msm/sde/sde_crtc.h @@ -199,6 +199,7 @@ struct sde_crtc_event { * @dirty_list : list of color processing features are dirty * @ad_dirty: list containing ad properties that are dirty * @ad_active: list containing ad properties that are active + * @ad_vsync_count : count of vblank since last reset for AD * @crtc_lock : crtc lock around create, destroy and access. * @frame_pending : Whether or not an update is pending * @frame_events : static allocation of in-flight frame events @@ -266,6 +267,7 @@ struct sde_crtc { struct list_head ad_dirty; struct list_head ad_active; struct list_head user_event_list; + u32 ad_vsync_count; struct mutex crtc_lock; struct mutex crtc_cp_lock; diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ad4.c b/drivers/gpu/drm/msm/sde/sde_hw_ad4.c index 66445da368fc..e60defd2c35b 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_ad4.c +++ b/drivers/gpu/drm/msm/sde/sde_hw_ad4.c @@ -109,6 +109,9 @@ static int ad4_ipc_reset_setup_ipcr(struct sde_hw_dspp *dspp, static int ad4_cfg_ipc_reset(struct sde_hw_dspp *dspp, struct sde_ad_hw_cfg *cfg); +static int ad4_vsync_update(struct sde_hw_dspp *dspp, + struct sde_ad_hw_cfg *cfg); + static ad4_prop_setup prop_set_func[ad4_state_max][AD_PROPMAX] = { [ad4_state_idle][AD_MODE] = ad4_mode_setup_common, [ad4_state_idle][AD_INIT] = ad4_init_setup_idle, @@ -121,6 +124,7 @@ static ad4_prop_setup prop_set_func[ad4_state_max][AD_PROPMAX] = { [ad4_state_idle][AD_IPC_SUSPEND] = ad4_no_op_setup, [ad4_state_idle][AD_IPC_RESUME] = ad4_no_op_setup, [ad4_state_idle][AD_IPC_RESET] = ad4_no_op_setup, + [ad4_state_idle][AD_VSYNC_UPDATE] = ad4_no_op_setup, [ad4_state_startup][AD_MODE] = ad4_mode_setup_common, [ad4_state_startup][AD_INIT] = ad4_init_setup, @@ -133,6 +137,7 @@ static ad4_prop_setup prop_set_func[ad4_state_max][AD_PROPMAX] = { [ad4_state_startup][AD_STRENGTH] = ad4_no_op_setup, [ad4_state_startup][AD_IPC_RESUME] = ad4_no_op_setup, [ad4_state_startup][AD_IPC_RESET] = ad4_ipc_reset_setup_startup, + [ad4_state_startup][AD_VSYNC_UPDATE] = ad4_vsync_update, [ad4_state_run][AD_MODE] = ad4_mode_setup_common, [ad4_state_run][AD_INIT] = ad4_init_setup_run, @@ -145,6 +150,7 @@ static ad4_prop_setup prop_set_func[ad4_state_max][AD_PROPMAX] = { [ad4_state_run][AD_IPC_SUSPEND] = ad4_ipc_suspend_setup_run, [ad4_state_run][AD_IPC_RESUME] = ad4_no_op_setup, [ad4_state_run][AD_IPC_RESET] = ad4_setup_debug, + [ad4_state_run][AD_VSYNC_UPDATE] = ad4_vsync_update, [ad4_state_ipcs][AD_MODE] = ad4_no_op_setup, [ad4_state_ipcs][AD_INIT] = ad4_no_op_setup, @@ -157,6 +163,7 @@ static ad4_prop_setup prop_set_func[ad4_state_max][AD_PROPMAX] = { [ad4_state_ipcs][AD_IPC_SUSPEND] = ad4_no_op_setup, [ad4_state_ipcs][AD_IPC_RESUME] = ad4_ipc_resume_setup_ipcs, [ad4_state_ipcs][AD_IPC_RESET] = ad4_no_op_setup, + [ad4_state_ipcs][AD_VSYNC_UPDATE] = ad4_no_op_setup, [ad4_state_ipcr][AD_MODE] = ad4_mode_setup_common, [ad4_state_ipcr][AD_INIT] = ad4_init_setup_ipcr, @@ -169,6 +176,7 @@ static ad4_prop_setup prop_set_func[ad4_state_max][AD_PROPMAX] = { [ad4_state_ipcr][AD_IPC_SUSPEND] = ad4_ipc_suspend_setup_ipcr, [ad4_state_ipcr][AD_IPC_RESUME] = ad4_no_op_setup, [ad4_state_ipcr][AD_IPC_RESET] = ad4_ipc_reset_setup_ipcr, + [ad4_state_ipcr][AD_VSYNC_UPDATE] = ad4_no_op_setup, [ad4_state_manual][AD_MODE] = ad4_mode_setup_common, [ad4_state_manual][AD_INIT] = ad4_init_setup, @@ -181,6 +189,7 @@ static ad4_prop_setup prop_set_func[ad4_state_max][AD_PROPMAX] = { [ad4_state_manual][AD_IPC_SUSPEND] = ad4_no_op_setup, [ad4_state_manual][AD_IPC_RESUME] = ad4_no_op_setup, [ad4_state_manual][AD_IPC_RESET] = ad4_setup_debug_manual, + [ad4_state_manual][AD_VSYNC_UPDATE] = ad4_no_op_setup, }; struct ad4_info { @@ -201,6 +210,7 @@ struct ad4_info { u32 irdx_control_0; u32 tf_ctrl; u32 vc_control_0; + u32 frame_pushes; }; static struct ad4_info info[DSPP_MAX] = { @@ -905,6 +915,8 @@ static int ad4_cfg_setup(struct sde_hw_dspp *dspp, struct sde_ad_hw_cfg *cfg) val = (ad_cfg->cfg_param_046 & (BIT(16) - 1)); SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset, val); + info[dspp->idx].frame_pushes = ad_cfg->cfg_param_047; + return 0; } @@ -1546,3 +1558,25 @@ static int ad4_strength_setup_idle(struct sde_hw_dspp *dspp, ad4_mode_setup(dspp, info[dspp->idx].mode); return 0; } + +static int ad4_vsync_update(struct sde_hw_dspp *dspp, + struct sde_ad_hw_cfg *cfg) +{ + u32 *count; + struct sde_hw_mixer *hw_lm; + + if (cfg->hw_cfg->len != sizeof(u32) || !cfg->hw_cfg->payload) { + DRM_ERROR("invalid sz param exp %zd given %d cfg %pK\n", + sizeof(u32), cfg->hw_cfg->len, cfg->hw_cfg->payload); + return -EINVAL; + } + + count = (u32 *)(cfg->hw_cfg->payload); + hw_lm = cfg->hw_cfg->mixer_info; + + if (hw_lm && !hw_lm->cfg.right_mixer && + (*count < info[dspp->idx].frame_pushes)) + (*count)++; + + return 0; +} -- cgit v1.2.3 From 900157ca68bf2cfe892e45537e5d63365b57bd78 Mon Sep 17 00:00:00 2001 From: Dhaval Patel Date: Mon, 12 Mar 2018 14:26:09 -0700 Subject: drm/msm/sde: update rgba4444 and rgba5551 color component order fix rgba4444 and rgba5551 color component order. Change-Id: I49d1ecb51a53f1535ff2d68a5e7375eba0cc8f48 Signed-off-by: Dhaval Patel --- drivers/gpu/drm/msm/sde/sde_formats.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/sde/sde_formats.c b/drivers/gpu/drm/msm/sde/sde_formats.c index d09054ecb552..719b8c1e8d0c 100644 --- a/drivers/gpu/drm/msm/sde/sde_formats.c +++ b/drivers/gpu/drm/msm/sde/sde_formats.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -275,97 +275,97 @@ static const struct sde_format sde_format_map[] = { INTERLEAVED_RGB_FMT(ARGB1555, COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, + C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, true, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(ABGR1555, COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, + C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, true, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(RGBA5551, COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, true, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(BGRA5551, COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, + C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, true, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(XRGB1555, COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, + C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, false, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(XBGR1555, COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, + C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, false, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(RGBX5551, COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, false, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(BGRX5551, COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, + C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, false, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(ARGB4444, COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, + C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, true, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(ABGR4444, COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, + C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, true, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(RGBA4444, COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, true, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(BGRA4444, COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, + C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, true, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(XRGB4444, COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, + C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, false, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(XBGR4444, COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, + C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, false, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(RGBX4444, COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, false, 2, 0, SDE_FETCH_LINEAR, 1), INTERLEAVED_RGB_FMT(BGRX4444, COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, + C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, false, 2, 0, SDE_FETCH_LINEAR, 1), -- cgit v1.2.3