[ROM-7420] Add ROM-7420 imx6 Project in Uboot

12 files changed, 770 insertions, 11 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d97e50d325..4b683b3f20 100755
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -594,7 +594,8 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
 	imx53-m53menlo.dtb
 
 dtb-$(CONFIG_ADVANTECH) += imx6q-rsb4410-a1.dtb \
-	imx6q-rsb4411-a1.dtb 
+	imx6q-rsb4411-a1.dtb \
+	imx6q-rom7420-a1.dtb
 
 ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
 dtb-y += \
@@ -800,7 +801,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mp-ddr4-evk.dtb \
 	imx8mp-evk.dtb \
 	imx8mp-rsb3720-a1.dtb \
-	imx8mp-rom5722-a1.dtb \
 	imx8mm-ddr4-ab2.dtb \
 	imx8mm-rom5721-a1.dtb \
 	imx8mq-rom5720-a1.dtb \
diff --git a/arch/arm/dts/imx6q-rom7420-a1.dts b/arch/arm/dts/imx6q-rom7420-a1.dts
new file mode 100644
index 0000000000..ca74158420
--- /dev/null
+++ b/arch/arm/dts/imx6q-rom7420-a1.dts
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-advantech.dtsi"
+
+/ {
+	model = "i.MX6 Quad ADVANTECH Smart Device Board";
+	compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
+        aliases {
+                mmc0 = &usdhc2;
+                mmc1 = &usdhc4;
+                mmc2;
+                mmc3;
+        };
+
+};
+
+&ecspi1 {
+	cs-gpios = <&gpio3 19 0>;
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_ecspi1_cs_0: ecspi1_cs_grp-0 {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x80000000	/* ECSPI1_CS1 */
+			>;
+		};
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&fec {
+	status = "okay";
+};
+
+&usdhc2 {
+	status = "okay";
+};
+
+&usdhc4 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6q-rsb4410-a1.dts b/arch/arm/dts/imx6q-rsb4410-a1.dts
index 476cc31682..70c7bad129 100644
--- a/arch/arm/dts/imx6q-rsb4410-a1.dts
+++ b/arch/arm/dts/imx6q-rsb4410-a1.dts
@@ -20,11 +20,18 @@
 
 };
 
-&uart1 {
-	status = "okay";
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_ecspi1_cs_0: ecspi1_cs_grp-0 {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x80000000	/* ECSPI1_CS0 */
+			>;
+		};
 };
 
-&ecspi1 {
+&uart1 {
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/imx6q-rsb4411-a1.dts b/arch/arm/dts/imx6q-rsb4411-a1.dts
index f02b9c2e62..5754e23fa0 100644
--- a/arch/arm/dts/imx6q-rsb4411-a1.dts
+++ b/arch/arm/dts/imx6q-rsb4411-a1.dts
@@ -20,11 +20,18 @@
 
 };
 
-&uart1 {
-	status = "okay";
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_ecspi1_cs_0: ecspi1_cs_grp-0 {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x80000000	/* ECSPI1_CS0 */
+			>;
+		};
 };
 
-&ecspi1 {
+&uart1 {
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/imx6qdl-advantech.dtsi b/arch/arm/dts/imx6qdl-advantech.dtsi
index 4a1b5c7e8d..cb0cd52e95 100644
--- a/arch/arm/dts/imx6qdl-advantech.dtsi
+++ b/arch/arm/dts/imx6qdl-advantech.dtsi
@@ -320,8 +320,8 @@
 	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio2 30 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1>;
-	status = "disabled";
+	pinctrl-0 = <&pinctrl_ecspi1_cs_0 &pinctrl_ecspi1>;
+	status = "okay";
 
 	flash: m25p80@0 {
 		#address-cells = <1>;
@@ -678,7 +678,6 @@
                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 	0x100b1
                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 	0x100b1
                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 	0x100b1
-				MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x1b0b0
 			>;
 		};
 
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 6d2997ede6..496c0cfd25 100755
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -488,6 +488,11 @@ config TARGET_MX6QRSB4411A1_1G
     select TARGET_MX6ADVANTECH_COMMON
     select MX6Q
 
+config TARGET_MX6QROM7420A1_1G
+	bool "Support mx6qrom7420a1 1G"
+    select TARGET_MX6ADVANTECH_COMMON
+    select MX6Q
+
 config TARGET_MX6QPSABRESD
 	bool "mx6qpsabresd"
     select TARGET_MX6SABRESD_COMMON
diff --git a/board/freescale/mx6advantech/Kconfig b/board/freescale/mx6advantech/Kconfig
index d41c8d6f22..3ec3fcd14c 100755
--- a/board/freescale/mx6advantech/Kconfig
+++ b/board/freescale/mx6advantech/Kconfig
@@ -17,3 +17,8 @@ config SYS_CONFIG_NAME
 	default "mx6rsb4411"
 endif
 
+if TARGET_MX6QROM7420A1_1G
+config SYS_CONFIG_NAME
+        default "mx6rom7420"
+endif
+
diff --git a/board/freescale/mx6advantech/mx6qrom7420_4x_IM4G16D3FABG-125_1410025137-01_20140424.inc b/board/freescale/mx6advantech/mx6qrom7420_4x_IM4G16D3FABG-125_1410025137-01_20140424.inc
new file mode 100755
index 0000000000..91979bcc1f
--- /dev/null
+++ b/board/freescale/mx6advantech/mx6qrom7420_4x_IM4G16D3FABG-125_1410025137-01_20140424.inc
@@ -0,0 +1,292 @@
+//*================================================================================================
+//* Copyright (C) 2011, Freescale Semiconductor, Inc. All Rights Reserved
+//* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
+//* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
+//* Freescale Semiconductor, Inc.
+//*================================================================================================
+
+
+// DDR init script, written in ARM RVDS syntax
+// Target the CPUDDR3 board
+// Timing optimized to 528MHz. 64-bit data bus 
+
+
+// Initialization script for i.MX6q CPU Board (DDR3)
+// Version 1.0 (07-06-11)
+// v 1.01 (June 16, 2011)
+// - based on Boaz's orignal script
+// - changed write leveling to 0x44
+// - updated DDR calibration (DQS gating, read/write) per latest gathered from stress test code
+//
+// v 1.02 (July 20, 2011)
+// - DDR_INPUT bit cleared for: DQM, RAS, CAS, SDCLK, RESET (All output only...)
+
+
+// v 1.03 (July 20, 2011)
+//   - ADOPT, DDRCTL power down timer activated by configuring MMDC0_MAPSR & MMDC0_MDPDC 
+
+//  v 1.04 (Oct 20, 2011)
+//  - More order in file
+//  - One-time HW ZQ calibration added.
+//  - power down timers enable moved to end of config
+// 
+//  v 1.05 (Mar 25, 2012)
+//  - IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET setup corrected to set DDR_SEL='11' (DDR3). This corrects ZQ calibration operation. 
+//    Improvment of DDR signals levels is expected.  
+//  - DQS drive strength reduced 6->7,device Rtt_nom 120->60, show better overclocking with new DDR_SEL 
+//  - tMRD value increased by 1 to match JEDEC
+
+//  v 1.06 (june 12, 2012)
+// - SDCLK duty cycle fine tunning changed from default to low.
+// - Previous step of setting DRAM_RESET/DDR_SEL='11' is reversed back to '00'
+//   , after finding the later to have a better DDR signals integrity. IO design are still investigating this.
+// -  i.mx ODT configs changed : 60 -> 120Ohm, to save power. See more in comment bellow.
+// - IOMUX configs: Remove redundant (input only...) pull setup from output signals: SDCKE, ODT
+
+//  v 1.07 
+// - Silicon version v1.2 (MX6Q/DxxxxxxxC) compatible. SDCLK duty cycle fine tute is back to default (2).
+// - MAARCR registers modified to reflect the best simulated ADOPT performence
+
+//  v 1.08 (Sep 2012)
+// DQ & DQS input sensing mode changed to CMOS - for power saving.
+//(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL,IOMUXC_SW_PAD_CTL_GRP_DDRMODE )
+// CMOS mode means less timing margins than "DDR" mode.
+// For i.mx6Q v1.2, CMOS mode seen to operate 10% above the target 528MHz
+// , so it is ok to cjange default setup to CMOS 
+
+//  v 1.09 (Sep 2012)
+// MDOR register updated RST_to_CKE=0x23, SDE_to_RST=0x10, to meet JEDEC. 
+//Apparently there is no actual DDR issue with previous (smaller ) values, as these parameters got spares. 
+//================================================================================================
+
+
+
+wait = on
+
+//*================================================================================================
+// Disable WDOG
+//*================================================================================================
+//setmem /16 0x020bc000 = 0x30
+
+
+//*================================================================================================
+// Enable all clocks (they are disabled by ROM code)
+//*================================================================================================
+setmem /32 0x020c4068 = 0xffffffff
+setmem /32 0x020c406c = 0xffffffff
+setmem /32 0x020c4070 = 0xffffffff
+setmem /32 0x020c4074 = 0xffffffff
+setmem /32 0x020c4078 = 0xffffffff
+setmem /32 0x020c407c = 0xffffffff
+setmem /32 0x020c4080 = 0xffffffff
+setmem /32 0x020c4084 = 0xffffffff
+
+
+//*================================================================================================
+// Initialize 64-bit DDR3 
+//*================================================================================================
+
+//######################################################
+// IOMUX 
+//######################################################
+
+//DDR IO TYPE:
+setmem /32 0x020e0798 = 0x000c0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=11 
+setmem /32 0x020e0758 = 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE - PKE=0 , Pull disabled for all, except DQS.
+
+//CLOCK:
+setmem /32 0x020e0588 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - DSE=101, DDR_INPUT=0, HYS=0
+setmem /32 0x020e0594 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - DSE=101, DDR_INPUT=0, HYS=0
+
+//ADDRESS:
+setmem /32 0x020e056c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS - DSE=110, DDR_INPUT=1, HYS=0
+setmem /32 0x020e0578 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS - DSE=110, DDR_INPUT=1, HYS=0
+setmem /32 0x020e074c = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS - DSE=110
+
+//CONTROL:
+setmem /32 0x020e057c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET - DSE=110, DDR_INPUT=1, HYS=0, DDR_SEL=00
+
+setmem /32 0x020e058c = 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
+setmem /32 0x020e059c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+setmem /32 0x020e05a0 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
+setmem /32 0x020e078c = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS - DSE=110
+
+
+//DATA STROBE:
+setmem /32 0x020e0750 = 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS
+//in case of DDR timing issue on your board you can try DDR_MODE:  [= 0x00020000]
+
+setmem /32 0x020e05a8 = 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 - DSE=110
+setmem /32 0x020e05b0 = 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 - DSE=110
+setmem /32 0x020e0524 = 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 - DSE=110
+setmem /32 0x020e051c = 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 - DSE=110
+setmem /32 0x020e0518 = 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 - DSE=110
+setmem /32 0x020e050c = 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 - DSE=110
+setmem /32 0x020e05b8 = 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 - DSE=110
+setmem /32 0x020e05c0 = 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 - DSE=110
+
+//DATA:
+setmem /32 0x020e0774 = 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE- DDR_INPUT 0,CMOS
+//in case of DDR timing issue on your board you can try DDR_MODE:  [= 0x00020000]
+
+setmem /32 0x020e0784 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS - DSE=110
+setmem /32 0x020e0788 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS - DSE=110
+setmem /32 0x020e0794 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS - DSE=110
+setmem /32 0x020e079c = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS - DSE=110
+setmem /32 0x020e07a0 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS - DSE=110
+setmem /32 0x020e07a4 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS - DSE=110
+setmem /32 0x020e07a8 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS - DSE=110
+setmem /32 0x020e0748 = 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS - DSE=110
+
+setmem /32 0x020e05ac = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 - DSE=110, DDR_INPUT=1, HYS=0
+setmem /32 0x020e05b4 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 - DSE=110, DDR_INPUT=1, HYS=0
+setmem /32 0x020e0528 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 - DSE=110, DDR_INPUT=1, HYS=0
+setmem /32 0x020e0520 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 - DSE=110, DDR_INPUT=1, HYS=0
+setmem /32 0x020e0514 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 - DSE=110, DDR_INPUT=1, HYS=0
+setmem /32 0x020e0510 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 - DSE=110, DDR_INPUT=1, HYS=0
+setmem /32 0x020e05bc = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 - DSE=110, DDR_INPUT=1, HYS=0
+setmem /32 0x020e05c4 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 - DSE=110, DDR_INPUT=1, HYS=0
+
+
+
+//######################################################
+//Calibrations:
+//######################################################
+// ZQ:
+setmem /32 0x021b0800 = 0xa1390003      // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
+
+// write leveling
+setmem /32 0x021b080c = 0x001F001F
+setmem /32 0x021b0810 = 0x001F001F
+
+setmem /32 0x021b480c = 0x00440044
+setmem /32 0x021b4810 = 0x00440044
+
+//DQS gating, read delay, write delay calibration values based on calibration compare of 0x00ffff00:
+// It is highly recommended for the user to run calibration code on her/his specific board 
+//and replace following delay values accordingly: 
+   
+//Read DQS Gating calibration
+setmem /32 0x021b083c = 0x45640570
+setmem /32 0x021b0840 = 0x05300554
+setmem /32 0x021b483c = 0x456C056C
+setmem /32 0x021b4840 = 0x0560053C
+
+//Read calibration
+setmem /32 0x021b0848 = 0x3434383A
+setmem /32 0x021b4848 = 0x3A38343C
+
+//Write calibration
+setmem /32 0x021b0850 = 0x3E3C403C
+setmem /32 0x021b4850 = 0x4436443E
+
+
+//read data bit delay: (3 is the reccommended default value, although out of reset value is 0):
+setmem /32 0x021b081c = 0x33333333      // DDR_PHY_P0_MPREDQBY0DL3
+setmem /32 0x021b0820 = 0x33333333      // DDR_PHY_P0_MPREDQBY1DL3
+setmem /32 0x021b0824 = 0x33333333      // DDR_PHY_P0_MPREDQBY2DL3
+setmem /32 0x021b0828 = 0x33333333      // DDR_PHY_P0_MPREDQBY3DL3
+setmem /32 0x021b481c = 0x33333333      // DDR_PHY_P1_MPREDQBY0DL3
+setmem /32 0x021b4820 = 0x33333333      // DDR_PHY_P1_MPREDQBY1DL3
+setmem /32 0x021b4824 = 0x33333333      // DDR_PHY_P1_MPREDQBY2DL3
+setmem /32 0x021b4828 = 0x33333333      // DDR_PHY_P1_MPREDQBY3DL3
+
+
+//setmem /32	0x021b082c =	0xf3333333 	// wr bit delay, byte 0
+//setmem /32	0x021b0830 =	0xf3333333 	// wr bit delay, byte 1
+//setmem /32	0x021b0834 =	0xf3333333 	// wr bit delay, byte 2
+//setmem /32	0x021b0838 =	0xf3333333 	// wr bit delay, byte 3
+//setmem /32	0x021b482c =	0xf3333333 	// wr bit delay, byte 4
+//setmem /32	0x021b4830 =	0xf3333333 	// wr bit delay, byte 5
+//setmem /32	0x021b4834 =	0xf3333333 	// wr bit delay, byte 6
+//setmem /32	0x021b4838 =	0xf3333333 	// wr bit delay, byte 7
+
+
+//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented
+//setmem /32	0x021b08c0 =	0x24911492	// fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
+//setmem /32	0x021b48c0 =	0x24911492	
+
+//######################################################
+// Complete calibration by forced measurment:
+//######################################################
+setmem /32 0x021b08b8 = 0x00000800      // DDR_PHY_P0_MPMUR0, frc_msr
+setmem /32 0x021b48b8 = 0x00000800      // DDR_PHY_P0_MPMUR0, frc_msr
+
+//######################################################
+//MMDC init:
+
+
+//528MHz
+//in DDR3, 64-bit mode, only MMDC0 is initiated:
+setmem /32 0x021b0004 = 0x0002002D		// MMDC0_MDPDC see spread sheet for timings. tCKE=3CLK; tCKSRX=5CLK; tCKSRE=5CLK
+setmem /32 0x021b0008 = 0x09446060		// MMDC0_MDOTC see spread sheet for timings. tAOFPD=2CLK; tAONPD=2CLK; tANPD=5CLK; tAXPD=5CLK; tODTLon=6CLK;
+//org CFGs
+//setmem /32 0x021b000c = 0x555A7975		// MMDC0_MDCFG0 see spread sheet for timings. CL=8
+//setmem /32 0x021b0010 = 0xFF538F64		// MMDC0_MDCFG1 see spread sheet for timings
+//setmem /32 0x021b0014 = 0x01ff00db      // MMDC0_MDCFG2 - tRRD - 4ck; tWTR - 4ck; tRTP - 4ck; tDLLK - 512ck
+
+setmem /32 0x021b000c = 0x8A8F79A4		// MMDC0_MDCFG0 see spread sheet for timings. tRFC=139CLK; tXS=144CLK; tXP=4CLK; tXPDLL=13CLK; tFAW=27CLK; CL=7
+setmem /32 0x021b0010 = 0xDB538F64		// MMDC0_MDCFG1 see spread sheet for timings. tCL=7CLK; tRCD=7CLK; tRP=7CLK; tRC=27CLK; tRAS=20CLK; tWR=8CLK; tMRD=12CLK; tCWL=6CLK
+setmem /32 0x021b0014 = 0x01FF016D	// MMDC0_MDCFG2. tDLLK=512CLK; tRTP=6CLK; tWTR=6CLK; tRRD=6CLK
+
+setmem /32 0x021b0018 = 0x00081740      // MMDC0_MDMISC, RALAT=0x5
+//MDMISC: RALAT kept to the high level of 5. 
+//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: 
+//a. better operation at low frequency
+//b. Small performence improvment
+
+setmem /32 0x021b001c = 0x00008000      // MMDC0_MDSCR
+
+setmem /32 0x021b002c = 0x000026d2      // MMDC0_MDRWD
+setmem /32 0x021b0030 = 0x008F1023      // MMDC0_MDOR - tXPR - 139CLK; SDE_to_RST - 14CLK; RST_to_CKE - 33CLK
+setmem /32 0x021b0040 = 0x00000047      // CS0_END - 0x4fffffff 
+
+setmem /32 0x021b0400 = 0x11420000      //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled
+setmem /32 0x021b4400 = 0x11420000      
+
+
+setmem /32 0x021b0000 = 0x841A0000      // MMDC0_MDCTL - row - 15its; col = 10bits; burst length 8; 64-bit data bus
+
+
+
+//######################################################
+// Initialize 2GB DDR3 - Micron MT41J128M , but fit wide range of other DDR3 devices
+//MR2:
+setmem /32 0x021b001c = 0x04088032      // MMDC0_MDSCR
+setmem /32 0x021b001c = 0x0408803A      // MMDC0_MDSCR
+
+
+//MR3:
+setmem /32 0x021b001c = 0x00008033      // MMDC0_MDSCR
+setmem /32 0x021b001c = 0x0000803b      // MMDC0_MDSCR
+//MR1:	A6,A2 --> Rtt Norm;   A5,A1 --> Drive Output Control(00, 01)
+setmem /32 0x021b001c = 0x00048031      // MMDC0_MDSCR
+setmem /32 0x021b001c = 0x00048039      // MMDC0_MDSCR
+//MR0:
+
+setmem /32 0x021b001c = 0x09408030      // MMDC0_MDSCR, 
+setmem /32 0x021b001c = 0x09408038      // MMDC0_MDSCR, 
+
+//DDR device ZQ calibration:
+setmem /32 0x021b001c = 0x04008040      // MMDC0_MDSCR, 
+setmem /32 0x021b001c = 0x04008048      // MMDC0_MDSCR
+//######################################################
+//final DDR setup, before operation start:
+
+setmem /32 0x021b0020 = 0x00005800      // MMDC0_MDREF, enable auto refresh, set refresh rate.
+
+//Following ODT setup (0x11117) represents(along with obove DDR device configs) : i.mx_ODT=DDR_device_ODT=120OHm.
+//User might to also interested in trying the value of 0x00000007,which represents: i.mx_ODT disabled, DDR_device_ODT=120Ohm.
+//0x00000007 saves more power, and seen to run very well with Freescale RDKs. Still, running with no ODT has it's implications 
+// of signal integrity and should be carefully simulated during board design.
+
+setmem /32 0x021b0818 = 0x00011117      // DDR_PHY_P0_MPODTCTRL, ODT enable
+setmem /32 0x021b4818 = 0x00011117      // DDR_PHY_P1_MPODTCTRL
+
+setmem /32 0x021b0004 = 0x00025576		// MMDC0_MDPDC see spread sheet for timings, SDCTL power down enabled
+
+setmem /32 0x021b0404 = 0x00011006      //MMDC0_MAPSR ADOPT power down enabled
+
+setmem /32 0x021b001c = 0x00000000      // MMDC0_MDSCR
+
+// 0003
diff --git a/board/freescale/mx6advantech/mx6qrom7420_4x_K4B2G1646Q-BCK0_1410024420-01.cfg b/board/freescale/mx6advantech/mx6qrom7420_4x_K4B2G1646Q-BCK0_1410024420-01.cfg
new file mode 100755
index 0000000000..a0946ba7f0
--- /dev/null
+++ b/board/freescale/mx6advantech/mx6qrom7420_4x_K4B2G1646Q-BCK0_1410024420-01.cfg
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, sata
+ * the board has no nand and eimnor
+ * spinor: flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ */
+
+/* the same flash_offset as sd */
+BOOT_FROM      sd
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sabresd/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+DATA 4, 0x020e0798, 0x000c0000
+DATA 4, 0x020e0758, 0x00000000
+DATA 4, 0x020e0588, 0x00000030
+DATA 4, 0x020e0594, 0x00000030
+DATA 4, 0x020e056c, 0x00000030
+DATA 4, 0x020e0578, 0x00000030
+DATA 4, 0x020e074c, 0x00000030
+DATA 4, 0x020e057c, 0x00000030
+DATA 4, 0x020e058c, 0x00000000
+DATA 4, 0x020e059c, 0x00000030
+DATA 4, 0x020e05a0, 0x00000030
+DATA 4, 0x020e078c, 0x00000030
+DATA 4, 0x020e0750, 0x00020000
+DATA 4, 0x020e05a8, 0x00000030
+DATA 4, 0x020e05b0, 0x00000030
+DATA 4, 0x020e0524, 0x00000030
+DATA 4, 0x020e051c, 0x00000030
+DATA 4, 0x020e0518, 0x00000030
+DATA 4, 0x020e050c, 0x00000030
+DATA 4, 0x020e05b8, 0x00000030
+DATA 4, 0x020e05c0, 0x00000030
+DATA 4, 0x020e0774, 0x00020000
+DATA 4, 0x020e0784, 0x00000030
+DATA 4, 0x020e0788, 0x00000030
+DATA 4, 0x020e0794, 0x00000030
+DATA 4, 0x020e079c, 0x00000030
+DATA 4, 0x020e07a0, 0x00000030
+DATA 4, 0x020e07a4, 0x00000030
+DATA 4, 0x020e07a8, 0x00000030
+DATA 4, 0x020e0748, 0x00000030
+DATA 4, 0x020e05ac, 0x00000030
+DATA 4, 0x020e05b4, 0x00000030
+DATA 4, 0x020e0528, 0x00000030
+DATA 4, 0x020e0520, 0x00000030
+DATA 4, 0x020e0514, 0x00000030
+DATA 4, 0x020e0510, 0x00000030
+DATA 4, 0x020e05bc, 0x00000030
+DATA 4, 0x020e05c4, 0x00000030
+DATA 4, 0x021b0800, 0xa1390003
+DATA 4, 0x021b080c, 0x001F001F
+DATA 4, 0x021b0810, 0x001F001F
+DATA 4, 0x021b480c, 0x001F001F
+DATA 4, 0x021b4810, 0x001F001F
+DATA 4, 0x021b083c, 0x43680370
+DATA 4, 0x021b0840, 0x035C0358
+DATA 4, 0x021b483c, 0x43700370
+DATA 4, 0x021b4840, 0x035C0330
+DATA 4, 0x021b0848, 0x4238383C
+DATA 4, 0x021b4848, 0x3C3A3440
+DATA 4, 0x021b0850, 0x3C3E4444
+DATA 4, 0x021b4850, 0x463E4C42
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b481c, 0x33333333
+DATA 4, 0x021b4820, 0x33333333
+DATA 4, 0x021b4824, 0x33333333
+DATA 4, 0x021b4828, 0x33333333
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b48b8, 0x00000800
+DATA 4, 0x021b0004, 0x00020036
+DATA 4, 0x021b0008, 0x09444040
+DATA 4, 0x021b000c, 0x555A79A5
+DATA 4, 0x021b0010, 0xDB538E64
+DATA 4, 0x021b0014, 0x01FF00DB
+DATA 4, 0x021b0018, 0x00001740
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b002c, 0x000026d2
+DATA 4, 0x021b0030, 0x005a1023
+DATA 4, 0x021b0040, 0x00000027
+//IPU error and should remove
+//DATA 4, 0x021b0400, 0x11420000
+//DATA 4, 0x021b4400, 0x11420000
+DATA 4, 0x021b0000, 0x831a0000
+DATA 4, 0x021b001c, 0x04088032
+DATA 4, 0x021b001c, 0x0408803a
+DATA 4, 0x021b001c, 0x00008033
+DATA 4, 0x021b001c, 0x0000803b
+DATA 4, 0x021b001c, 0x00468031
+DATA 4, 0x021b001c, 0x00468039
+DATA 4, 0x021b001c, 0x09408030
+DATA 4, 0x021b001c, 0x09408038
+DATA 4, 0x021b001c, 0x04008040
+DATA 4, 0x021b001c, 0x04008048
+DATA 4, 0x021b0020, 0x00005800
+DATA 4, 0x021b0818, 0x00011117
+DATA 4, 0x021b4818, 0x00011117
+DATA 4, 0x021b0004, 0x00025576
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b001c, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, 0x020c4060, 0x000000fb
+#endif
diff --git a/common/board_r.c b/common/board_r.c
index a11713626f..bf0096270f 100755
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -1181,11 +1181,15 @@ static init_fnc_t init_sequence_r[] = {
 #endif
 	/* PPC has a udelay(20) here dating from 2002. Why? */
 #ifdef CONFIG_CMD_NET
+#ifndef CONFIG_TARGET_MX6QROM7420A1_1G
 	initr_ethaddr,
+#endif
 #if defined(CONFIG_ADVANTECH) || defined(CONFIG_ADVANTECH_MX8)
+#ifndef CONFIG_TARGET_MX6QROM7420A1_1G
 	boardcfg_get_mac,	/* Get MAC address from SPI */
 #endif
 #endif
+#endif
 #if defined(CONFIG_GPIO_HOG)
 	gpio_hog_probe_all,
 #endif
diff --git a/configs/mx6qrom7420a1_1G_defconfig b/configs/mx6qrom7420a1_1G_defconfig
new file mode 100644
index 0000000000..820b432c25
--- /dev/null
+++ b/configs/mx6qrom7420a1_1G_defconfig
@@ -0,0 +1,102 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+# CONFIG_LDO_BYPASS_CHECK is not set
+CONFIG_TARGET_MX6QROM7420A1_1G=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xC0000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_ADVANTECH=y
+CONFIG_SMBIOS_PRODUCT_NAME="mx6rom7420a1"
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_BUILD_TARGET=""
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6advantech/mx6qrom7420_4x_K4B2G1646Q-BCK0_1410024420-01.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-rom7420-a1"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=20000000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DWC_AHSATA=y
+# CONFIG_BLK is not set
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
\ No newline at end of file
diff --git a/include/configs/mx6rom7420.h b/include/configs/mx6rom7420.h
new file mode 100755
index 0000000000..6f2d27316f
--- /dev/null
+++ b/include/configs/mx6rom7420.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ */
+
+#ifndef __MX6ADVANTECH_CONFIG_H
+#define __MX6ADVANTECH_CONFIG_H
+
+#ifdef CONFIG_SPL
+#include "imx6_spl_advantech.h"
+#endif
+
+#define CONFIG_MACH_TYPE	3980
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONSOLE_DEV		"ttymxc0"
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* SDHC2 */
+
+
+#if defined(CONFIG_TARGET_MX6QROM7420A1_512M)
+#define PHYS_SDRAM_SIZE         (512u * 1024 * 1024)
+#elif defined(CONFIG_TARGET_MX6QROM7420A1_1G)
+#define PHYS_SDRAM_SIZE         (1u * 1024 * 1024 * 1024)
+#elif defined(CONFIG_TARGET_MX6QROM7420A1_2G)
+#define PHYS_SDRAM_SIZE         (2u * 1024 * 1024 * 1024)
+#endif
+
+#include "mx6advantech_common.h"
+
+/* Falcon Mode */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
+#define CONFIG_SYS_SPL_ARGS_ADDR       0x18000000
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
+
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SDHC3 */
+#ifndef CONFIG_SYS_MMC_ENV_PART
+#define CONFIG_SYS_MMC_ENV_PART                0       /* user partition */
+#endif
+
+#undef CONFIG_FEC_MXC_PHYADDR
+#define CONFIG_FEC_MXC_PHYADDR  0
+
+/*
+ * imx6 q/dl/solo pcie would be failed to work properly in kernel, if
+ * the pcie module is iniialized/enumerated both in uboot and linux
+ * kernel.
+ * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism.
+ * it is only be RESET by the POR. So, the pcie module only be
+ * initialized/enumerated once in one POR.
+ * Set to use pcie in kernel defaultly, mask the pcie config here.
+ * Remove the mask freely, if the uboot pcie functions, rather than
+ * the kernel's, are required.
+ */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#ifndef CONFIG_DM_PCI
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(3, 19)
+#endif
+#endif
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1 /* Enabled USB controller number */
+#endif
+
+/*#define CONFIG_SPLASH_SCREEN*/
+/*#define CONFIG_MXC_EPDC*/
+
+/*
+ * SPLASH SCREEN Configs
+ */
+#ifndef CONFIG_ADVANTECH
+#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
+	/*
+	 * Framebuffer and LCD
+	 */
+	#define CONFIG_CMD_BMP
+	#undef LCD_TEST_PATTERN
+	/* #define CONFIG_SPLASH_IS_IN_MMC			1 */
+	#define LCD_BPP					LCD_MONOCHROME
+	/* #define CONFIG_SPLASH_SCREEN_ALIGN		1 */
+
+	#define CONFIG_WAVEFORM_BUF_SIZE		0x400000
+#endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */
+#endif
+
+#define CONFIG_SUPPORT_LVDS
+#ifdef CONFIG_SUPPORT_LVDS
+#define IOMUX_LCD_BKLT_PWM 	MX6_PAD_GPIO_1__GPIO1_IO01
+#define IOMUX_LCD_BKLT_EN	MX6_PAD_KEY_COL0__GPIO4_IO06
+#define IOMUX_LCD_VDD_EN	MX6_PAD_KEY_ROW0__GPIO4_IO07
+#define LCD_BKLT_PWM 		IMX_GPIO_NR(1, 1)
+#define LCD_BKLT_EN 		IMX_GPIO_NR(4, 6)
+#define LCD_VDD_EN 		IMX_GPIO_NR(4, 7)	
+#endif
+#define USDHC3_CD_GPIO          IMX_GPIO_NR(7, 1)
+
+#define CONFIG_PCIE_RESET
+#define IOMUX_PCIE_RESET	MX6_PAD_CSI0_DAT4__GPIO5_IO22	//CPU_WIFI_RESET
+#define PCIE_RESET              IMX_GPIO_NR(5,22)
+
+#define CONFIG_M2_SLOT
+#define IOMUX_M2_WLAN_OFF	MX6_PAD_NANDF_D7__GPIO2_IO07	//M.2_WLAN_OFF
+#define IOMUX_M2_BT_OFF		MX6_PAD_NANDF_D1__GPIO2_IO01	//M.2_BT_OFF
+#define	M2_WLAN_OFF		IMX_GPIO_NR(2, 7)
+#define	M2_BT_OFF		IMX_GPIO_NR(2, 1)
+#endif                         /* __MX6ADVANTECH_CONFIG_H */