6 files changed, 81 insertions, 11 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d97e50d325..4b683b3f20 100755
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -594,7 +594,8 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
 	imx53-m53menlo.dtb
 
 dtb-$(CONFIG_ADVANTECH) += imx6q-rsb4410-a1.dtb \
-	imx6q-rsb4411-a1.dtb 
+	imx6q-rsb4411-a1.dtb \
+	imx6q-rom7420-a1.dtb
 
 ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
 dtb-y += \
@@ -800,7 +801,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mp-ddr4-evk.dtb \
 	imx8mp-evk.dtb \
 	imx8mp-rsb3720-a1.dtb \
-	imx8mp-rom5722-a1.dtb \
 	imx8mm-ddr4-ab2.dtb \
 	imx8mm-rom5721-a1.dtb \
 	imx8mq-rom5720-a1.dtb \
diff --git a/arch/arm/dts/imx6q-rom7420-a1.dts b/arch/arm/dts/imx6q-rom7420-a1.dts
new file mode 100644
index 0000000000..ca74158420
--- /dev/null
+++ b/arch/arm/dts/imx6q-rom7420-a1.dts
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-advantech.dtsi"
+
+/ {
+	model = "i.MX6 Quad ADVANTECH Smart Device Board";
+	compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
+        aliases {
+                mmc0 = &usdhc2;
+                mmc1 = &usdhc4;
+                mmc2;
+                mmc3;
+        };
+
+};
+
+&ecspi1 {
+	cs-gpios = <&gpio3 19 0>;
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_ecspi1_cs_0: ecspi1_cs_grp-0 {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x80000000	/* ECSPI1_CS1 */
+			>;
+		};
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&fec {
+	status = "okay";
+};
+
+&usdhc2 {
+	status = "okay";
+};
+
+&usdhc4 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6q-rsb4410-a1.dts b/arch/arm/dts/imx6q-rsb4410-a1.dts
index 476cc31682..70c7bad129 100644
--- a/arch/arm/dts/imx6q-rsb4410-a1.dts
+++ b/arch/arm/dts/imx6q-rsb4410-a1.dts
@@ -20,11 +20,18 @@
 
 };
 
-&uart1 {
-	status = "okay";
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_ecspi1_cs_0: ecspi1_cs_grp-0 {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x80000000	/* ECSPI1_CS0 */
+			>;
+		};
 };
 
-&ecspi1 {
+&uart1 {
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/imx6q-rsb4411-a1.dts b/arch/arm/dts/imx6q-rsb4411-a1.dts
index f02b9c2e62..5754e23fa0 100644
--- a/arch/arm/dts/imx6q-rsb4411-a1.dts
+++ b/arch/arm/dts/imx6q-rsb4411-a1.dts
@@ -20,11 +20,18 @@
 
 };
 
-&uart1 {
-	status = "okay";
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_ecspi1_cs_0: ecspi1_cs_grp-0 {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x80000000	/* ECSPI1_CS0 */
+			>;
+		};
 };
 
-&ecspi1 {
+&uart1 {
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/imx6qdl-advantech.dtsi b/arch/arm/dts/imx6qdl-advantech.dtsi
index 4a1b5c7e8d..cb0cd52e95 100644
--- a/arch/arm/dts/imx6qdl-advantech.dtsi
+++ b/arch/arm/dts/imx6qdl-advantech.dtsi
@@ -320,8 +320,8 @@
 	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio2 30 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1>;
-	status = "disabled";
+	pinctrl-0 = <&pinctrl_ecspi1_cs_0 &pinctrl_ecspi1>;
+	status = "okay";
 
 	flash: m25p80@0 {
 		#address-cells = <1>;
@@ -678,7 +678,6 @@
                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 	0x100b1
                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 	0x100b1
                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 	0x100b1
-				MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x1b0b0
 			>;
 		};
 
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 6d2997ede6..496c0cfd25 100755
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -488,6 +488,11 @@ config TARGET_MX6QRSB4411A1_1G
     select TARGET_MX6ADVANTECH_COMMON
     select MX6Q
 
+config TARGET_MX6QROM7420A1_1G
+	bool "Support mx6qrom7420a1 1G"
+    select TARGET_MX6ADVANTECH_COMMON
+    select MX6Q
+
 config TARGET_MX6QPSABRESD
 	bool "mx6qpsabresd"
     select TARGET_MX6SABRESD_COMMON