diff options
| author | Stephan Gerhold <stephan@gerhold.net> | 2019-11-25 13:22:55 +0100 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2019-12-11 16:45:33 +0100 |
| commit | 92b33c010e612cccc069d25a354dabc1380e5cb9 (patch) | |
| tree | d8fa8625e74f06f683e91e3a6f036c2c1d67616e | |
| parent | 15e8a2993d776fcc499451bb05d7082c4757f12f (diff) | |
ARM: dts: ux500: Add pin configs for UART1 CTS/RTS pins
UART1 can optionally be used with additional CTS/RTS pins.
The pinctrl driver has an extra "u1ctsrts_a_1" pin group for them.
Add a new pin configuration to configure them correctly if needed.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125122256.53482-4-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi index b6d0a60e9aed..e85a08ad2ea7 100644 --- a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi @@ -65,6 +65,32 @@ ste,config = <&slpm_out_wkup_pdis>; }; }; + + u1ctsrts_a_1_default: u1ctsrts_a_1_default { + default_mux { + function = "u1"; + groups = "u1ctsrts_a_1"; + }; + default_cfg1 { + pins = "GPIO6_AF6"; /* CTS */ + ste,config = <&in_pu>; + }; + default_cfg2 { + pins = "GPIO7_AG5"; /* RTS */ + ste,config = <&out_hi>; + }; + }; + + u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep { + sleep_cfg1 { + pins = "GPIO6_AF6"; /* CTS */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg2 { + pins = "GPIO7_AG5"; /* RTS */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + }; }; uart2 { |