From 3c77307fbf0c36d572023f9ed95b308a9b2c4510 Mon Sep 17 00:00:00 2001 From: Shunqian Zheng Date: Thu, 8 Mar 2018 17:48:05 +0800 Subject: arm64: dts: rockchip: add isp0 node for rk3399 rk3399 have two ISP, but we havn't test isp1, so just add isp0 at present. Signed-off-by: Shunqian Zheng Signed-off-by: Jacob Chen [update for upstream] Signed-off-by: Helen Koike Series-changes: 7 - add phy properties - add ports --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index cede1ad81be2..776d2bd48c06 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1698,6 +1698,31 @@ status = "disabled"; }; + isp0: isp0@ff910000 { + compatible = "rockchip,rk3399-cif-isp"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_ISP0>, + <&cru ACLK_ISP0>, <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0>, <&cru HCLK_ISP0_WRAPPER>; + clock-names = "clk_isp", + "aclk_isp", "aclk_isp_wrap", + "hclk_isp", "hclk_isp_wrap"; + power-domains = <&power RK3399_PD_ISP0>; + iommus = <&isp0_mmu>; + phys = <&mipi_dphy_rx0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + }; + }; + isp0_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; -- cgit v1.2.3