diff options
| author | Kaixu Xia <xiakaixu@huawei.com> | 2015-03-30 14:13:39 -0600 |
|---|---|---|
| committer | Mathieu Poirier <mathieu.poirier@linaro.org> | 2015-05-07 09:45:53 -0600 |
| commit | b252e546fb4a4202028a479b800d13405651d789 (patch) | |
| tree | b79439f90616c1b9bac844c9a0a2ae232213c924 | |
| parent | edb5ff252135df120cc2cb50d5ac655152d7f0d4 (diff) | |
coresight: remove the unnecessary configuration coresight-default-sink
The coresight-default-sink configuration option has been
removed from the framework. As such remove it from DT and bindings.
Signed-off-by: Kaixu Xia <xiakaixu@huawei.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 223437c72ae008094e43199dea93c3a144c4e153)
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Conflicts:
arch/arm/boot/dts/omap3-beagle-xm.dts
arch/arm/boot/dts/omap3-beagle.dts
| -rw-r--r-- | Documentation/devicetree/bindings/arm/coresight.txt | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/hip04.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 1 |
3 files changed, 0 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index a3089359aaa6..88602b75418e 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -61,7 +61,6 @@ Example: compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0 0x20010000 0 0x1000>; - coresight-default-sink; clocks = <&oscclk6a>; clock-names = "apb_pclk"; port { diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 238814596a87..44044f275115 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -275,7 +275,6 @@ compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0 0xe3c42000 0 0x1000>; - coresight-default-sink; clocks = <&clk_375m>; clock-names = "apb_pclk"; port { diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 33920df03640..7a2aeacd62c0 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -362,7 +362,6 @@ compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0 0x20010000 0 0x1000>; - coresight-default-sink; clocks = <&oscclk6a>; clock-names = "apb_pclk"; port { |