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| author | Stephen Rothwell <sfr@canb.auug.org.au> | 2017-05-01 11:02:18 +1000 |
|---|---|---|
| committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2017-05-01 11:02:18 +1000 |
| commit | 976d58c212b6ddd5fa9f554e861d67367ae0aaef (patch) | |
| tree | e23cd8c6fc182a7415843d1a88527a4cb2f0c3ea /Documentation | |
| parent | 401085e71f0c4605b615d2febfd9f29fac99244d (diff) | |
| parent | b0d36daa0ab54714e05164f6e21d22f974a5eec1 (diff) | |
Merge remote-tracking branch 'drm-tegra/drm/tegra/for-next'
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 0fad7ed2ea19..74e1e8add5a1 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -249,6 +249,19 @@ of the following host1x client modules: See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information regarding the DPAUX pad controller bindings. +- vic: Video Image Compositor + - compatible : "nvidia,tegra<chip>-vic" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must include the following entries: + - vic: clock input for the VIC hardware + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - vic + Example: / { |