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-rw-r--r--Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt133
-rw-r--r--Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt139
-rw-r--r--Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt158
-rw-r--r--Documentation/devicetree/bindings/remoteproc/st-rproc.txt41
-rw-r--r--Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt133
5 files changed, 604 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
new file mode 100644
index 000000000000..75ad7b8df0b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
@@ -0,0 +1,133 @@
+Qualcomm ADSP Peripheral Image Loader
+
+This document defines the binding for a component that loads and boots firmware
+on the Qualcomm ADSP Hexagon core.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be one of:
+ "qcom,msm8974-adsp-pil"
+ "qcom,msm8996-adsp-pil"
+ "qcom,msm8996-slpi-pil"
+
+- interrupts-extended:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must list the watchdog, fatal IRQs ready, handover and
+ stop-ack IRQs
+
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
+
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: reference to the xo clock and optionally aggre2 clock to be
+ held on behalf of the booting Hexagon core
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "xo" and optionally include "aggre2"
+
+- cx-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the regulator to be held on behalf of the
+ booting Hexagon core
+
+- px-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the px regulator to be held on behalf of the
+ booting Hexagon core
+
+- memory-region:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the reserved-memory for the ADSP
+
+- qcom,smem-states:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the smem state for requesting the ADSP to
+ shut down
+
+- qcom,smem-state-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "stop"
+
+
+= SUBNODES
+The adsp node may have an subnode named "smd-edge" that describes the SMD edge,
+channels and devices related to the ADSP. See ../soc/qcom/qcom,smd.txt for
+details on how to describe the SMD edge.
+
+
+= EXAMPLE
+The following example describes the resources needed to boot control the
+ADSP, as it is found on MSM8974 boards.
+
+ adsp {
+ compatible = "qcom,msm8974-adsp-pil";
+
+ interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmcc RPM_CXO_CLK>;
+ clock-names = "xo";
+
+ cx-supply = <&pm8841_s2>;
+
+ memory-region = <&adsp_region>;
+
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ smd-edge {
+ interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 8>;
+ qcom,smd-edge = <1>;
+ };
+ };
+
+The following example describes the resources needed to boot control the
+SLPI, as it is found on MSM8996 boards.
+
+ slpi {
+ compatible = "qcom,msm8996-slpi-pil";
+ interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmcc MSM8996_RPM_SMD_XO_CLK_SRC>,
+ <&rpmcc MSM8996_RPM_SMD_AGGR2_NOC_CLK>;
+ clock-names = "xo", "aggre2";
+
+ cx-supply = <&pm8994_l26>;
+ px-supply = <&pm8994_lvs2>;
+
+ memory-region = <&slpi_region>;
+ qcom,smem-states = <&slpi_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+ };
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
new file mode 100644
index 000000000000..92347fe6890e
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -0,0 +1,139 @@
+Qualcomm Hexagon Peripheral Image Loader
+
+This document defines the binding for a component that loads and boots firmware
+on the Qualcomm Hexagon core.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be one of:
+ "qcom,q6v5-pil",
+ "qcom,msm8916-mss-pil",
+ "qcom,msm8974-mss-pil"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the qdsp6 and
+ rmb register blocks
+
+- reg-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "q6dsp" and "rmb"
+
+- interrupts-extended:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must list the watchdog, fatal IRQs ready, handover and
+ stop-ack IRQs
+
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
+
+- clocks:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the iface, bus and mem clocks to be held on
+ behalf of the booting of the Hexagon core
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "iface", "bus", "mem"
+
+- resets:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the reset-controller for the modem sub-system
+
+- reset-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "mss_restart"
+
+- cx-supply:
+- mss-supply:
+- mx-supply:
+- pll-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the regulators to be held on behalf of the
+ booting of the Hexagon core
+
+- qcom,smem-states:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the smem state for requesting the Hexagon to
+ shut down
+
+- qcom,smem-state-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "stop"
+
+- qcom,halt-regs:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: a phandle reference to a syscon representing TCSR followed
+ by the three offsets within syscon for q6, modem and nc
+ halt registers.
+
+= SUBNODES:
+The Hexagon node must contain two subnodes, named "mba" and "mpss" representing
+the memory regions used by the Hexagon firmware. Each sub-node must contain:
+
+- memory-region:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the reserved-memory for the region
+
+= EXAMPLE
+The following example describes the resources needed to boot control the
+Hexagon, as it is found on MSM8974 boards.
+
+ modem-rproc@fc880000 {
+ compatible = "qcom,q6v5-pil";
+ reg = <0xfc880000 0x100>,
+ <0xfc820000 0x020>;
+ reg-names = "qdsp6", "rmb";
+
+ interrupts-extended = <&intc 0 24 1>,
+ <&modem_smp2p_in 0 0>,
+ <&modem_smp2p_in 1 0>,
+ <&modem_smp2p_in 2 0>,
+ <&modem_smp2p_in 3 0>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+ <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_BOOT_ROM_AHB_CLK>;
+ clock-names = "iface", "bus", "mem";
+
+ qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
+
+ resets = <&gcc GCC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ cx-supply = <&pm8841_s2>;
+ mss-supply = <&pm8841_s3>;
+ mx-supply = <&pm8841_s1>;
+ pll-supply = <&pm8941_l12>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ mba {
+ memory-region = <&mba_region>;
+ };
+
+ mpss {
+ memory-region = <&mpss_region>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt
new file mode 100644
index 000000000000..d420f84ddfb0
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt
@@ -0,0 +1,158 @@
+Qualcomm WCNSS Peripheral Image Loader
+
+This document defines the binding for a component that loads and boots firmware
+on the Qualcomm WCNSS core.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be one of:
+ "qcom,riva-pil",
+ "qcom,pronto-v1-pil",
+ "qcom,pronto-v2-pil"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must specify the base address and size of the CCU, DXE and
+ PMU register blocks
+
+- reg-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "ccu", "dxe", "pmu"
+
+- interrupts-extended:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: must list the watchdog and fatal IRQs and may specify the
+ ready, handover and stop-ack IRQs
+
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: should be "wdog", "fatal", optionally followed by "ready",
+ "handover", "stop-ack"
+
+- vddmx-supply:
+- vddcx-supply:
+- vddpx-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the regulators to be held on behalf of the
+ booting of the WCNSS core
+
+- qcom,smem-states:
+ Usage: optional
+ Value type: <prop-encoded-array>
+ Definition: reference to the SMEM state used to indicate to WCNSS that
+ it should shut down
+
+- qcom,smem-state-names:
+ Usage: optional
+ Value type: <stringlist>
+ Definition: should be "stop"
+
+- memory-region:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: reference to reserved-memory node for the remote processor
+ see ../reserved-memory/reserved-memory.txt
+
+= SUBNODES
+A required subnode of the WCNSS PIL is used to describe the attached rf module
+and its resource dependencies. It is described by the following properties:
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be one of:
+ "qcom,wcn3620",
+ "qcom,wcn3660",
+ "qcom,wcn3680"
+
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the xo clock and optionally the rf clock
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: should be "xo", optionally followed by "rf"
+
+- vddxo-supply:
+- vddrfa-supply:
+- vddpa-supply:
+- vdddig-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: reference to the regulators to be held on behalf of the
+ booting of the WCNSS core
+
+
+The wcnss node can also have an subnode named "smd-edge" that describes the SMD
+edge, channels and devices related to the WCNSS.
+See ../soc/qcom/qcom,smd.txt for details on how to describe the SMD edge.
+
+= EXAMPLE
+The following example describes the resources needed to boot control the WCNSS,
+with attached WCN3680, as it is commonly found on MSM8974 boards.
+
+pronto@fb204000 {
+ compatible = "qcom,pronto-v2-pil";
+ reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
+ reg-names = "ccu", "dxe", "pmu";
+
+ interrupts-extended = <&intc 0 149 1>,
+ <&wcnss_smp2p_slave 0 0>,
+ <&wcnss_smp2p_slave 1 0>,
+ <&wcnss_smp2p_slave 2 0>,
+ <&wcnss_smp2p_slave 3 0>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ vddmx-supply = <&pm8841_s1>;
+ vddcx-supply = <&pm8841_s2>;
+ vddpx-supply = <&pm8941_s3>;
+
+ qcom,smem-states = <&wcnss_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ memory-region = <&wcnss_region>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcnss_pin_a>;
+
+ iris {
+ compatible = "qcom,wcn3680";
+
+ clocks = <&rpmcc RPM_CXO_CLK_SRC>, <&rpmcc RPM_CXO_A2>;
+ clock-names = "xo", "rf";
+
+ vddxo-supply = <&pm8941_l6>;
+ vddrfa-supply = <&pm8941_l11>;
+ vddpa-supply = <&pm8941_l19>;
+ vdddig-supply = <&pm8941_s3>;
+ };
+
+ smd-edge {
+ interrupts = <0 142 1>;
+
+ qcom,ipc = <&apcs 8 17>;
+ qcom,smd-edge = <6>;
+ qcom,remote-pid = <4>;
+
+ label = "pronto";
+
+ wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+
+ qcom,mmio = <&pronto>;
+
+ bt {
+ compatible = "qcom,wcnss-bt";
+ };
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/remoteproc/st-rproc.txt b/Documentation/devicetree/bindings/remoteproc/st-rproc.txt
new file mode 100644
index 000000000000..1031bcd90a79
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/st-rproc.txt
@@ -0,0 +1,41 @@
+STMicroelectronics Co-Processor Bindings
+----------------------------------------
+
+This binding provides support for adjunct processors found on ST SoCs.
+
+Co-processors can be controlled from the bootloader or the primary OS. If
+the bootloader starts a co-processor, the primary OS must detect its state
+and act accordingly.
+
+Required properties:
+- compatible Should be one of:
+ "st,st231-rproc"
+ "st,st40-rproc"
+- memory-region Reserved memory (See: ../reserved-memory/reserved-memory.txt)
+- resets Reset lines (See: ../reset/reset.txt)
+- reset-names Must be "sw_reset" and "pwr_reset"
+- clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
+- clock-frequency Clock frequency to set co-processor at if the bootloader
+ hasn't already done so
+- st,syscfg System configuration register which holds the boot vector
+ for the co-processor
+ 1st cell: Phandle to syscon block
+ 2nd cell: Boot vector register offset
+
+Example:
+
+ audio_reserved: rproc@42000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x42000000 0x01000000>;
+ no-map;
+ };
+
+ st231-audio {
+ compatible = "st,st231-rproc";
+ memory-region = <&audio_reserved>;
+ resets = <&softreset STIH407_ST231_AUD_SOFTRESET>;
+ reset-names = "sw_reset";
+ clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
+ clock-frequency = <600000000>;
+ st,syscfg = <&syscfg_core 0x228>;
+ };
diff --git a/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt b/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt
new file mode 100644
index 000000000000..2aac1aa4123d
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt
@@ -0,0 +1,133 @@
+TI Keystone DSP devices
+=======================
+
+The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core
+sub-systems that are used to offload some of the processor-intensive tasks or
+algorithms, for achieving various system level goals.
+
+These processor sub-systems usually contain additional sub-modules like L1
+and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller,
+a dedicated local power/sleep controller etc. The DSP processor core in
+Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
+
+DSP Device Node:
+================
+Each DSP Core sub-system is represented as a single DT node, and should also
+have an alias with the stem 'rproc' defined. Each node has a number of required
+or optional properties that enable the OS running on the host processor (ARM
+CorePac) to perform the device management of the remote processor and to
+communicate with the remote processor.
+
+Required properties:
+--------------------
+The following are the mandatory properties:
+
+- compatible: Should be one of the following,
+ "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
+ "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
+ "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
+
+- reg: Should contain an entry for each value in 'reg-names'.
+ Each entry should have the memory region's start address
+ and the size of the region, the representation matching
+ the parent node's '#address-cells' and '#size-cells' values.
+
+- reg-names: Should contain strings with the following names, each
+ representing a specific internal memory region, and
+ should be defined in this order,
+ "l2sram", "l1pram", "l1dram"
+
+- clocks: Should contain the device's input clock, and should be
+ defined as per the bindings in,
+ Documentation/devicetree/bindings/clock/keystone-gate.txt
+
+- ti,syscon-dev: Should be a pair of the phandle to the Keystone Device
+ State Control node, and the register offset of the DSP
+ boot address register within that node's address space.
+
+- resets: Should contain the phandle to the reset controller node
+ managing the resets for this device, and a reset
+ specifier. Please refer to the following reset bindings
+ for the reset argument specifier as per SoC,
+ Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+ for 66AK2HK/66AK2L/66AK2E SoCs
+
+- interrupt-parent: Should contain a phandle to the Keystone 2 IRQ controller
+ IP node that is used by the ARM CorePac processor to
+ receive interrupts from the DSP remote processors. See
+ Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt
+ for details.
+
+- interrupts: Should contain an entry for each value in 'interrupt-names'.
+ Each entry should have the interrupt source number used by
+ the remote processor to the host processor. The values should
+ follow the interrupt-specifier format as dictated by the
+ 'interrupt-parent' node. The purpose of each is as per the
+ description in the 'interrupt-names' property.
+
+- interrupt-names: Should contain strings with the following names, each
+ representing a specific interrupt,
+ "vring" - interrupt for virtio based IPC
+ "exception" - interrupt for exception notification
+
+- kick-gpios: Should specify the gpio device needed for the virtio IPC
+ stack. This will be used to interrupt the remote processor.
+ The gpio device to be used is as per the bindings in,
+ Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
+
+Optional properties:
+--------------------
+
+- memory-region: phandle to the reserved memory node to be associated
+ with the remoteproc device. The reserved memory node
+ can be a CMA memory node, and should be defined as
+ per the bindings in
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+
+
+Example:
+--------
+ /* 66AK2H/K DSP aliases */
+ aliases {
+ rproc0 = &dsp0;
+ rproc1 = &dsp1;
+ rproc2 = &dsp2;
+ rproc3 = &dsp3;
+ rproc4 = &dsp4;
+ rproc5 = &dsp5;
+ rproc6 = &dsp6;
+ rproc7 = &dsp7;
+ };
+
+ /* 66AK2H/K DSP memory node */
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_common_memory: dsp-common-memory@81f800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
+ reusable;
+ };
+ };
+
+ /* 66AK2H/K DSP node */
+ soc {
+ dsp0: dsp@10800000 {
+ compatible = "ti,k2hk-dsp";
+ reg = <0x10800000 0x00100000>,
+ <0x10e00000 0x00008000>,
+ <0x10f00000 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ clocks = <&clkgem0>;
+ ti,syscon-dev = <&devctrl 0x40>;
+ resets = <&pscrst 0>;
+ interrupt-parent = <&kirq0>;
+ interrupts = <0 8>;
+ interrupt-names = "vring", "exception";
+ kick-gpios = <&dspgpio0 27 0>;
+ memory-region = <&dsp_common_memory>;
+ };
+
+ };