diff options
Diffstat (limited to 'drivers/staging/ccree/dx_host.h')
-rw-r--r-- | drivers/staging/ccree/dx_host.h | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/staging/ccree/dx_host.h b/drivers/staging/ccree/dx_host.h index 4e42e748dc5f..3e75dc4d2657 100644 --- a/drivers/staging/ccree/dx_host.h +++ b/drivers/staging/ccree/dx_host.h @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -20,7 +20,7 @@ // -------------------------------------- // BLOCK: HOST_P // -------------------------------------- -#define DX_HOST_IRR_REG_OFFSET 0xA00UL +#define DX_HOST_IRR_REG_OFFSET 0xA00UL #define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL #define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL #define DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL @@ -31,7 +31,7 @@ #define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL #define DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL #define DX_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL -#define DX_HOST_IMR_REG_OFFSET 0xA04UL +#define DX_HOST_IMR_REG_OFFSET 0xA04UL #define DX_HOST_IMR_NOT_USED_MASK_BIT_SHIFT 0x1UL #define DX_HOST_IMR_NOT_USED_MASK_BIT_SIZE 0x1UL #define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL @@ -44,7 +44,7 @@ #define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL #define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT 0x17UL #define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL -#define DX_HOST_ICR_REG_OFFSET 0xA08UL +#define DX_HOST_ICR_REG_OFFSET 0xA08UL #define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL #define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL #define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL @@ -55,10 +55,10 @@ #define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL #define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL #define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL -#define DX_HOST_SIGNATURE_REG_OFFSET 0xA24UL +#define DX_HOST_SIGNATURE_REG_OFFSET 0xA24UL #define DX_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL #define DX_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL -#define DX_HOST_BOOT_REG_OFFSET 0xA28UL +#define DX_HOST_BOOT_REG_OFFSET 0xA28UL #define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL #define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL #define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL @@ -115,40 +115,40 @@ #define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL #define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL #define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_VERSION_REG_OFFSET 0xA40UL +#define DX_HOST_VERSION_REG_OFFSET 0xA40UL #define DX_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL #define DX_HOST_VERSION_VALUE_BIT_SIZE 0x20UL -#define DX_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL +#define DX_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL #define DX_HOST_KFDE0_VALID_VALUE_BIT_SHIFT 0x0UL #define DX_HOST_KFDE0_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL +#define DX_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL #define DX_HOST_KFDE1_VALID_VALUE_BIT_SHIFT 0x0UL #define DX_HOST_KFDE1_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL +#define DX_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL #define DX_HOST_KFDE2_VALID_VALUE_BIT_SHIFT 0x0UL #define DX_HOST_KFDE2_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL +#define DX_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL #define DX_HOST_KFDE3_VALID_VALUE_BIT_SHIFT 0x0UL #define DX_HOST_KFDE3_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_GPR0_REG_OFFSET 0xA70UL +#define DX_HOST_GPR0_REG_OFFSET 0xA70UL #define DX_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL #define DX_HOST_GPR0_VALUE_BIT_SIZE 0x20UL -#define DX_GPR_HOST_REG_OFFSET 0xA74UL +#define DX_GPR_HOST_REG_OFFSET 0xA74UL #define DX_GPR_HOST_VALUE_BIT_SHIFT 0x0UL #define DX_GPR_HOST_VALUE_BIT_SIZE 0x20UL -#define DX_HOST_POWER_DOWN_EN_REG_OFFSET 0xA78UL +#define DX_HOST_POWER_DOWN_EN_REG_OFFSET 0xA78UL #define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT 0x0UL #define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL // -------------------------------------- // BLOCK: HOST_SRAM // -------------------------------------- -#define DX_SRAM_DATA_REG_OFFSET 0xF00UL +#define DX_SRAM_DATA_REG_OFFSET 0xF00UL #define DX_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL #define DX_SRAM_DATA_VALUE_BIT_SIZE 0x20UL -#define DX_SRAM_ADDR_REG_OFFSET 0xF04UL +#define DX_SRAM_ADDR_REG_OFFSET 0xF04UL #define DX_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL #define DX_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL -#define DX_SRAM_DATA_READY_REG_OFFSET 0xF08UL +#define DX_SRAM_DATA_READY_REG_OFFSET 0xF08UL #define DX_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL #define DX_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL |