diff options
| author | Nicola Mazzucato <nicola.mazzucato@arm.com> | 2024-01-09 12:54:53 +0000 |
|---|---|---|
| committer | Nicola Mazzucato <nicola.mazzucato@arm.com> | 2024-01-12 17:09:37 +0000 |
| commit | 97c8905f4c6b2c57ad2aab5ce3f545428e9792bf (patch) | |
| tree | c9a37ce462abdd26f6d2837b6973f70c0558620f | |
| parent | dcd622790378d3f3cb10d23a6b0a8b651cbf4025 (diff) | |
tc0: Remove platform code
TC0 platform was deprecated about a year ago.
Now remove the platform code as per the project's rules.
858076b2363c: (tc0: Deprecate platform)
Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com>
Change-Id: I41b63ead658ee2592c3e422a3cd514c120156e01
94 files changed, 4 insertions, 6039 deletions
diff --git a/Makefile.cmake b/Makefile.cmake index 0a172ad2605d..6bea1d271d3d 100644 --- a/Makefile.cmake +++ b/Makefile.cmake @@ -1,6 +1,6 @@ # # Arm SCP/MCP Software -# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -119,7 +119,7 @@ PRODUCTS := $(shell ls $(PRODUCTS_DIR) 2>/dev/null) # # Deprecated Products/Platforms # -DEPRECATED_PLATFORMS := tc0 +DEPRECATED_PLATFORMS := none PRODUCT_INDEPENDENT_GOALS := clean help test doc fwk_test mod_test diff --git a/maintainers.md b/maintainers.md index 8ca249b7ec0d..82d70f0aac4e 100644 --- a/maintainers.md +++ b/maintainers.md @@ -57,7 +57,7 @@ maintainers. The platforms listed here represent the exceptions to this rule. - [Thomas Abraham](https://github.com/omasab) (thomas.abraham@arm.com) - [Vijayenthiran Subramaniam](https://github.com/vijayenthiran-arm) (Vijayenthiran.Subramaniam@arm.com) -#### Total Compute (tc0, tc1) +#### Total Compute (tc1) - [Vishnu Banavath](https://github.com/visban01) (vishnu.banavath@arm.com) diff --git a/product/tc0/doc/variants.md b/product/tc0/doc/variants.md deleted file mode 100644 index 0b7726cd6ed5..000000000000 --- a/product/tc0/doc/variants.md +++ /dev/null @@ -1,71 +0,0 @@ -# TC0 Platform Variants - -Copyright (c) 2022, Arm Limited. All rights reserved. - - -## Overview - -Documentation for TC0 platform can be found at [1]. - -For the purpose of experimenting some of the software features that have been -introduced in SCP-firmware a new variant of TC0 has been created. -The variant(s) can be chosen at build time by adding: - -```sh - -make -f Makefile.cmake \ - PRODUCT=tc0 \ - MODE=<debug,release> \ - PLATFORM_VARIANT=<0,1> - -``` - - -### Variant 0 (Standard build) - -The standard build provides all the features described in [1]. -For this default variant, it's not required to provide any extra parameters in -the build commands. - - -### Variant 1 (Power/Performance testing) - -This variant adds support for the following software features: -- Traffic Cop -- MPMM (Maximum Power Mitigation Mechanism) -- Thermal Management -and to have the above fully working, the following dependencies are also added: -- Sensor support -- SCMI Performance FastChannels -- Performance Plugins Handler - -Since all the above work on power and performance, to ease evaluating the -features, and to show the configurability options, we split the features among -some of the DVFS domains. - -Once built, the features above will act as: - -+-----------------+-------------------+ -| DVFS domain | Controlled by (*) | -+-----------------+-------------------+ -| KLEIN | TRAFFIC COP | -| | THERMAL MGMT | -+-----------------+-------------------+ -| MATTERHORN | TRAFFIC COP | -| | THERMAL MGMT | -+-----------------+-------------------+ -| MATTERHORN ELP | MPMM | -| | THERMAL MGMT | -+-----------------+-------------------+ - -(*) This is in addition to the standard SCMI Performance interface commands. - - -## Limitations - -- The "variant" option is available only with the CMake build. -- The Thermal functionality is limited at this time cause the constant - temperature being sampled. - -References: -[1] https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/total-compute-solution diff --git a/product/tc0/include/clock_soc.h b/product/tc0/include/clock_soc.h deleted file mode 100644 index 41d1e23afcdc..000000000000 --- a/product/tc0/include/clock_soc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CLOCK_SOC_H -#define CLOCK_SOC_H - -#include <fwk_macros.h> - -#define CLOCK_RATE_REFCLK (100UL * FWK_MHZ) -#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ) - -/* - * PLL clock indexes. - */ -enum clock_pll_idx { - CLOCK_PLL_IDX_CPU_KLEIN, - CLOCK_PLL_IDX_CPU_MATTERHORN, - CLOCK_PLL_IDX_CPU_MATTERHORN_ELP_ARM, - CLOCK_PLL_IDX_SYS, - CLOCK_PLL_IDX_DPU, - CLOCK_PLL_IDX_PIX0, - CLOCK_PLL_IDX_PIX1, - CLOCK_PLL_IDX_COUNT -}; - -/* - * PIK clock indexes. - */ -enum clock_pik_idx { - CLOCK_PIK_IDX_CLUS0_CPU0, - CLOCK_PIK_IDX_CLUS0_CPU1, - CLOCK_PIK_IDX_CLUS0_CPU2, - CLOCK_PIK_IDX_CLUS0_CPU3, - CLOCK_PIK_IDX_CLUS0_CPU4, - CLOCK_PIK_IDX_CLUS0_CPU5, - CLOCK_PIK_IDX_CLUS0_CPU6, - CLOCK_PIK_IDX_CLUS0_CPU7, - CLOCK_PIK_IDX_GIC, - CLOCK_PIK_IDX_PCLKSCP, - CLOCK_PIK_IDX_SYSPERCLK, - CLOCK_PIK_IDX_UARTCLK, - CLOCK_PIK_IDX_DPU, - CLOCK_PIK_IDX_COUNT -}; - -/*! - * \brief Selectable clock sources for TC0 cluster clocks. - */ -enum mod_clusclock_source_tc0 { - /*! The clock is gated */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_GATED = 0x0, - /*! The clock source is set to the system reference clock */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_SYSREFCLK = 0x1, - /*! The clock source is set to a private cluster PLL */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL0 = 0x2, - /*! The clock source is set to a private cluster PLL */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL1 = 0x4, - /*! The clock source is set to a private cluster PLL */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL2 = 0x8, - /*! The clock source is set to a private cluster PLL */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL3 = 0x10, - /*! Number of valid clock sources */ - MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_MAX -}; - -/* - * CSS clock indexes. - */ -enum clock_css_idx { - CLOCK_CSS_IDX_CPU_GROUP_KLEIN, - CLOCK_CSS_IDX_CPU_GROUP_MATTERHORN, - CLOCK_CSS_IDX_CPU_GROUP_MATTERHORN_ELP_ARM, - CLOCK_CSS_IDX_DPU, - CLOCK_CSS_IDX_COUNT -}; - -/* - * Clock indexes. - */ -enum clock_idx { - CLOCK_IDX_CPU_GROUP_KLEIN, - CLOCK_IDX_CPU_GROUP_MATTERHORN, - CLOCK_IDX_CPU_GROUP_MATTERHORN_ELP_ARM, - CLOCK_IDX_DPU, - CLOCK_IDX_PIXEL_0, - CLOCK_IDX_PIXEL_1, - CLOCK_IDX_COUNT -}; - -#endif /* CLOCK_SOC_H */ diff --git a/product/tc0/include/config_power_domain.h b/product/tc0/include/config_power_domain.h deleted file mode 100644 index 980a228a65bb..000000000000 --- a/product/tc0/include/config_power_domain.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CONFIG_POWER_DOMAIN_H -#define CONFIG_POWER_DOMAIN_H - -#include <stdint.h> - -/* - * Power domain indices for the statically defined domains used for: - * - Indexing the domains in the tc0_power_domain_static_element_table - * - Indexing the SYSTOP children in the power domain tree - * - * When calculating a power domain element index, use the formula: - * core_count + cluster_count + pd_static_dev_idx - */ -enum pd_static_dev_idx { - PD_STATIC_DEV_IDX_SYSTOP, - PD_STATIC_DEV_IDX_COUNT, - PD_STATIC_DEV_IDX_NONE = UINT32_MAX -}; - -#endif /* CONFIG_POWER_DOMAIN_H */ diff --git a/product/tc0/include/cpu_pik.h b/product/tc0/include/cpu_pik.h deleted file mode 100644 index a66802706b13..000000000000 --- a/product/tc0/include/cpu_pik.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CPU_PIK_H -#define CPU_PIK_H - -#include "scp_css_mmap.h" - -#include <fwk_macros.h> - -#include <stdint.h> - -/*! - * \brief PE Static Configuration register definitions - */ -struct static_config_reg { - FWK_RW uint32_t STATIC_CONFIG; - FWK_RW uint32_t RVBARADDR_LW; - FWK_RW uint32_t RVBARADDR_UP; - uint32_t RESERVED; -}; - -/*! - * \brief AP cores clock control register definitions - */ -struct coreclk_reg { - FWK_RW uint32_t DIV; - FWK_RW uint32_t CTRL; - FWK_RW uint32_t MOD; - uint32_t RESERVED; -}; -/*! - * \brief CPU PIK register definitions - */ -struct pik_cpu_reg { - FWK_RW uint32_t CLUSTER_CONFIG; - uint8_t RESERVED0[0x100 - 0x4]; - struct static_config_reg STATIC_CONFIG[10]; - uint8_t RESERVED1[0x900 - 0x1a0]; - struct coreclk_reg CORECLK[10]; -}; - -#define CLUSTER_PIK_PTR(IDX) ((struct pik_cpu_reg *)SCP_PIK_CLUSTER_BASE(IDX)) - -#endif /* CPU_PIK_H */ diff --git a/product/tc0/include/dpu_pik.h b/product/tc0/include/dpu_pik.h deleted file mode 100644 index 2e1167517541..000000000000 --- a/product/tc0/include/dpu_pik.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef DPU_PIK_H -#define DPU_PIK_H - -#include "scp_css_mmap.h" - -#include <fwk_macros.h> - -#include <stdint.h> - -/*! - * \brief DPU PIK register definitions - */ -struct pik_dpu_reg { - FWK_R uint8_t RESERVED0[0x830]; - FWK_RW uint32_t ACLKDP_CTRL; - FWK_RW uint32_t ACLKDP_DIV1; - FWK_RW uint32_t ACLKDP_DIV2; - uint8_t RESERVED3[0xA00 - 0x83C]; - FWK_R uint32_t CLKFORCE_STATUS; - FWK_W uint32_t CLKFORCE_SET; - FWK_W uint32_t CLKFORCE_CLR; - uint8_t RESERVED4[0xFC0 - 0xA0C]; - FWK_RW uint32_t PCL_CONFIG; - uint8_t RESERVED5[0xFD0 - 0xFC4]; - FWK_R uint32_t PID4; - FWK_R uint32_t PID5; - FWK_R uint32_t PID6; - FWK_R uint32_t PID7; - FWK_R uint32_t PID0; - FWK_R uint32_t PID1; - FWK_R uint32_t PID2; - FWK_R uint32_t PID3; - FWK_R uint32_t ID0; - FWK_R uint32_t ID1; - FWK_R uint32_t ID2; - FWK_R uint32_t ID3; -}; - -#define DPU_PIK_PTR ((struct pik_dpu_reg *)SCP_PIK_DPU_BASE) - -#endif /* DPU_PIK_H */ diff --git a/product/tc0/include/fmw_cmsis.h b/product/tc0/include/fmw_cmsis.h deleted file mode 100644 index 8c4a1320097e..000000000000 --- a/product/tc0/include/fmw_cmsis.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef FMW_CMSIS_H -#define FMW_CMSIS_H - -#include <stdint.h> - -#define __CHECK_DEVICE_DEFINES -#define __CM3_REV 0x0201 -#define __FPU_PRESENT 0U -#define __MPU_PRESENT 1U -#define __ICACHE_PRESENT 0U -#define __DCACHE_PRESENT 0U -#define __DTCM_PRESENT 0U -#define __NVIC_PRIO_BITS 3U -#define __Vendor_SysTickConfig 0U -#define __VTOR_PRESENT 1U - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ - -typedef enum IRQn { - Reset_IRQn = -15, - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - - SOC_WAKEUP0_IRQ = 16, /* SoC Expansion Wakeup */ - TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ - MHU_AP_NONSEC_HP_IRQ = 34, /* MHU High Priority Non-Secure */ - MHU_AP_NONSEC_LP_IRQ = 35, /* MHU Low Priority Non-Secure */ - MHU_AP_SEC_IRQ = 36, /* MHU Secure */ - PPU_CORES0_IRQ = 64, /* PPU core 0 IRQ */ - PPU_CORES1_IRQ = 65, /* PPU core 1 IRQ */ - PPU_CORES2_IRQ = 66, /* PPU core 2 IRQ */ - PPU_CORES3_IRQ = 67, /* PPU core 3 IRQ */ - PPU_CLUSTERS_IRQ = 54, /* Consolidated clusters PPU */ - - IRQn_MAX = INT16_MAX, -} IRQn_Type; - -#include <core_cm3.h> - -#endif /* FMW_CMSIS_H */ diff --git a/product/tc0/include/fmw_io.h b/product/tc0/include/fmw_io.h deleted file mode 100644 index 90491c6db218..000000000000 --- a/product/tc0/include/fmw_io.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef FMW_IO_H -#define FMW_IO_H - -#include <fwk_id.h> -#include <fwk_module_idx.h> - -#define FMW_IO_STDIN_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) -#define FMW_IO_STDOUT_ID FWK_ID_ELEMENT(FWK_MODULE_IDX_PL011, 0) - -#endif /* FMW_IO_H */ diff --git a/product/tc0/include/scp_css_mmap.h b/product/tc0/include/scp_css_mmap.h deleted file mode 100644 index 7f85353c0507..000000000000 --- a/product/tc0/include/scp_css_mmap.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SCP_CSS_MMAP_H -#define SCP_CSS_MMAP_H - -#include "scp_mmap.h" - -#define SCP_CMN_BOOKER_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x10000000) - -#define SCP_REFCLK_CNTCONTROL_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A430000) -#define SCP_REFCLK_CNTCTL_BASE (SCP_PERIPHERAL_BASE + 0x0000) -#define SCP_REFCLK_CNTBASE0_BASE (SCP_PERIPHERAL_BASE + 0x1000) -#define SCP_UART_BOARD_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x3FF70000) -#define SCP_MHU_AP_BASE (SCP_PERIPHERAL_BASE) - -#define SCP_PIK_SCP_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE) -#define SCP_PIK_CLUSTER_BASE(n) \ - ((SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x60000) + ((n)*0x20000)) -#define SCP_PIK_SYSTEM_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x40000) - -#define SCP_PIK_DPU_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0xE0000) - -#define SCP_UTILITY_BUS_BASE \ - (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x1000000) -#define SCP_PPU_CLUSTER_BASE (SCP_UTILITY_BUS_BASE + 0x30000) -#define SCP_PPU_CORE_BASE(n) (SCP_UTILITY_BUS_BASE + 0x80000 + (n * 0x100000)) - -#define SCP_MPMM_BASE (SCP_UTILITY_BUS_BASE + 0xB0000) -#define SCP_MPMM_CORE_BASE(n) (SCP_MPMM_BASE + ((n)*0x100000)) - -#define SCP_AMU_BASE (SCP_UTILITY_BUS_BASE + 0x90000) -#define SCP_AMU_CORE_BASE(n) (SCP_AMU_BASE + ((n)*0x100000)) -#define SCP_AMU_AMEVCNTR0X(n) (SCP_AMU_CORE_BASE(n) + 0x0) -#define SCP_AMU_AMEVCNTR1X(n) (SCP_AMU_CORE_BASE(n) + 0x100) - -#define SCP_PPU_SYS0_BASE (SCP_PIK_SYSTEM_BASE + 0x1000) -#define SCP_PPU_SYS1_BASE (SCP_PIK_SYSTEM_BASE + 0x5000) - -#define SCP_MHU_SCP_AP_RCV_NS_CLUS0 (SCP_MHU_AP_BASE + 0x2000) -#define SCP_MHU_SCP_AP_SND_NS_CLUS0 (SCP_MHU_AP_BASE + 0x3000) -#define SCP_MHU_SCP_AP_RCV_S_CLUS0 (SCP_MHU_AP_BASE + 0x4000) -#define SCP_MHU_SCP_AP_SND_S_CLUS0 (SCP_MHU_AP_BASE + 0x5000) - -#endif /* SCP_CSS_MMAP_H */ diff --git a/product/tc0/include/scp_mmap.h b/product/tc0/include/scp_mmap.h deleted file mode 100644 index 12c22221f67e..000000000000 --- a/product/tc0/include/scp_mmap.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SCP_MMAP_H -#define SCP_MMAP_H - -#define SCP_BOOT_ROM_BASE 0x00000000 -#define SCP_RAM_BASE 0x10000000 - -#define SCP_SOC_EXPANSION3_BASE UINT32_C(0x40000000) -#define SCP_PERIPHERAL_BASE UINT32_C(0x44000000) -#define SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE UINT32_C(0x50000000) -#define SCP_SYSTEM_ACCESS_PORT0_BASE UINT32_C(0x60000000) -#define SCP_SYSTEM_ACCESS_PORT1_BASE UINT32_C(0xA0000000) - -#endif /* SCP_MMAP_H */ diff --git a/product/tc0/include/scp_pik.h b/product/tc0/include/scp_pik.h deleted file mode 100644 index a965eb504513..000000000000 --- a/product/tc0/include/scp_pik.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * SCP PIK registers - */ - -#ifndef SCP_PIK_H -#define SCP_PIK_H - -#include "scp_css_mmap.h" - -#include <fwk_macros.h> - -#include <stdint.h> - -struct pik_scp_reg { - uint32_t RESERVED0[4]; - FWK_RW uint32_t RESET_SYNDROME; - FWK_RW uint32_t WIC_CTRL; - FWK_R uint32_t WIC_STATUS; - uint8_t RESERVED1[0xA00 - 0x1C]; - FWK_R uint32_t CLKFORCE_STATUS; - FWK_RW uint32_t CLKFORCE_SET; - FWK_RW uint32_t CLKFORCE_CLR; - uint32_t RESERVED2; - FWK_R uint32_t PLL_STATUS[2]; - uint8_t RESERVED3[0xFC0 - 0xA18]; - FWK_R uint32_t PIK_CONFIG; - uint32_t RESERVED4[3]; - FWK_R uint32_t PID4; - FWK_R uint32_t PID5; - FWK_R uint32_t PID6; - FWK_R uint32_t PID7; - FWK_R uint32_t PID0; - FWK_R uint32_t PID1; - FWK_R uint32_t PID2; - FWK_R uint32_t PID3; - FWK_R uint32_t ID0; - FWK_R uint32_t ID1; - FWK_R uint32_t ID2; - FWK_R uint32_t ID3; -}; - -#define PLL_STATUS_0_SYSPLLLOCK UINT32_C(1 << 5) -#define PLL_STATUS_0_DISPLAYPLLLOCK UINT32_C(1 << 6) - -#define PLL_STATUS_CPUPLLLOCK(CPU) ((uint32_t)(1 << (CPU % 32))) - -/* Pointer to SCP PIK */ -#define SCP_PIK_PTR ((struct pik_scp_reg *)SCP_PIK_SCP_BASE) - -#endif /* SCP_PIK_H */ diff --git a/product/tc0/include/scp_soc_mmap.h b/product/tc0/include/scp_soc_mmap.h deleted file mode 100644 index 5edf834a1099..000000000000 --- a/product/tc0/include/scp_soc_mmap.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SCP_SOC_MMAP_H -#define SCP_SOC_MMAP_H - -#include "scp_mmap.h" - -#define SCP_PLL_BASE (SCP_SOC_EXPANSION3_BASE + 0x03000000) - -#define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000) -#define SCP_PLL_DISPLAY (SCP_PLL_BASE + 0x00000014) -#define SCP_PLL_PIX0 (SCP_PLL_BASE + 0x00000018) -#define SCP_PLL_PIX1 (SCP_PLL_BASE + 0x0000001C) -#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020) - -#define SCP_PLL_CPU_TYPE0 (SCP_PLL_BASE + 0x00000100) -#define SCP_PLL_CPU_TYPE1 (SCP_PLL_BASE + 0x00000104) -#define SCP_PLL_CPU_TYPE2 (SCP_PLL_BASE + 0x00000108) - -#endif /* SCP_SOC_MMAP_H */ diff --git a/product/tc0/include/scp_software_mmap.h b/product/tc0/include/scp_software_mmap.h deleted file mode 100644 index 1fbdc0a36a71..000000000000 --- a/product/tc0/include/scp_software_mmap.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SCP_SOFTWARE_MMAP_H -#define SCP_SOFTWARE_MMAP_H - -#include "scp_soc_mmap.h" - -#include <fwk_macros.h> - -/* SCP ROM and RAM firmware size loaded on main memory */ -#define SCP_BOOT_ROM_SIZE (512 * 1024) -#define SCP_RAM_SIZE (512 * 1024) - -/* SCP trusted and non-trusted RAM base address */ -#define SCP_TRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x04000000) -#define SCP_NONTRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x06000000) - -/* Secure Shared memory between AP and SCP */ -#define SCP_AP_SHARED_SECURE_BASE (SCP_TRUSTED_RAM_BASE) -#define SCP_AP_SHARED_SECURE_SIZE (4 * FWK_KIB) - -/* Non-secure Shared memory between AP and SCP */ -#define SCP_AP_SHARED_NONSECURE_BASE (SCP_NONTRUSTED_RAM_BASE) -#define SCP_AP_SHARED_NONSECURE_SIZE (4 * FWK_KIB) - -/* AP Context Area */ -#define SCP_AP_CONTEXT_BASE \ - (SCP_AP_SHARED_SECURE_BASE + SCP_AP_SHARED_SECURE_SIZE - \ - SCP_AP_CONTEXT_SIZE) -#define SCP_AP_CONTEXT_SIZE (64) - -/* SDS Memory Region */ -#define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE) -#define SCP_SDS_MEM_SIZE (3520) - -/* SCMI Secure Payload Areas */ -#define SCP_SCMI_PAYLOAD_SIZE (128) -#define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_MEM_BASE + SCP_SDS_MEM_SIZE) -#define SCP_SCMI_PAYLOAD_S_P2A_BASE \ - (SCP_SCMI_PAYLOAD_S_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE) - -/* SCMI Non-Secure Payload Areas */ - -#define SCP_SCMI_PAYLOAD0_NS_A2P_BASE (SCP_AP_SHARED_NONSECURE_BASE) -#define SCP_SCMI_PAYLOAD0_NS_P2A_BASE \ - (SCP_SCMI_PAYLOAD0_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE) -#define SCP_SCMI_PAYLOAD1_NS_A2P_BASE \ - (SCP_SCMI_PAYLOAD0_NS_P2A_BASE + SCP_SCMI_PAYLOAD_SIZE) -#define SCP_SCMI_PAYLOAD1_NS_P2A_BASE \ - (SCP_SCMI_PAYLOAD1_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE) - -/* SCMIv2 Fast Channels */ -#define SCMI_FAST_CHANNEL_BASE \ - (SCP_SCMI_PAYLOAD1_NS_P2A_BASE + SCP_SCMI_PAYLOAD_SIZE) - -#endif /* SCP_SOFTWARE_MMAP_H */ diff --git a/product/tc0/include/scp_tc0_mhu.h b/product/tc0/include/scp_tc0_mhu.h deleted file mode 100644 index 61a59cd3e7fb..000000000000 --- a/product/tc0/include/scp_tc0_mhu.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * MHU module device indexes. - */ - -#ifndef SCP_TC0_MHU_H -#define SCP_TC0_MHU_H - -enum scp_tc0_mhu_device_idx { - SCP_TC0_MHU_DEVICE_IDX_SCP_AP_S_CLUS0, - SCP_TC0_MHU_DEVICE_IDX_SCP_AP_NS_HP_CLUS0, - SCP_TC0_MHU_DEVICE_IDX_SCP_AP_NS_LP_CLUS0, - SCP_TC0_MHU_DEVICE_IDX_COUNT -}; - -#endif /* SCP_TC0_MHU_H */ diff --git a/product/tc0/include/system_pik.h b/product/tc0/include/system_pik.h deleted file mode 100644 index 152176a0e5b3..000000000000 --- a/product/tc0/include/system_pik.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SYSTEM_PIK_H -#define SYSTEM_PIK_H - -#include "scp_css_mmap.h" - -#include <fwk_macros.h> - -#include <stdint.h> - -/*! - * \brief TCU clock register definitions - */ -struct tcuclk_ctrl_reg { - FWK_RW uint32_t TCUCLK_CTRL; - FWK_RW uint32_t TCUCLK_DIV1; -}; - -/*! - * \brief System PIK register definitions - */ -struct pik_system_reg { - uint8_t RESERVED0[0x800 - 0x0]; - FWK_RW uint32_t PPUCLK_CTRL; - FWK_RW uint32_t PPUCLK_DIV1; - uint8_t RESERVED1[0x820 - 0x808]; - FWK_RW uint32_t INTCLK_CTRL; - FWK_RW uint32_t INTCLK_DIV1; - uint8_t RESERVED2[0x830 - 0x828]; - struct tcuclk_ctrl_reg TCUCLK[4]; - FWK_RW uint32_t GICCLK_CTRL; - FWK_RW uint32_t GICCLK_DIV1; - uint8_t RESERVED3[0x860 - 0x858]; - FWK_RW uint32_t PCLKSCP_CTRL; - FWK_RW uint32_t PCLKSCP_DIV1; - uint8_t RESERVED4[0x870 - 0x868]; - FWK_RW uint32_t SYSPERCLK_CTRL; - FWK_RW uint32_t SYSPERCLK_DIV1; - uint8_t RESERVED5[0x880 - 0x878]; - FWK_RW uint32_t DMCCLK_CTRL; - FWK_RW uint32_t DMCCLK_DIV1; - uint8_t RESERVED6[0x890 - 0x888]; - FWK_RW uint32_t SYSPCLKDBG_CTRL; - FWK_RW uint32_t SYSPCLKDBG_DIV1; - uint8_t RESERVED7[0x8A0 - 0x898]; - FWK_RW uint32_t UARTCLK_CTRL; - FWK_RW uint32_t UARTCLK_DIV1; - uint8_t RESERVED8[0xA00 - 0x8A8]; - FWK_R uint32_t CLKFORCE_STATUS; - FWK_W uint32_t CLKFORCE_SET; - FWK_W uint32_t CLKFORCE_CLR; - uint8_t RESERVED9[0xB0C - 0xA0C]; - FWK_RW uint32_t SYSTOP_RST_DLY; - uint8_t RESERVED10[0xFC0 - 0xB10]; - FWK_R uint32_t PCL_CONFIG; - uint8_t RESERVED11[0xFD0 - 0xFC4]; - FWK_R uint32_t PID4; - FWK_R uint32_t PID5; - FWK_R uint32_t PID6; - FWK_R uint32_t PID7; - FWK_R uint32_t PID0; - FWK_R uint32_t PID1; - FWK_R uint32_t PID2; - FWK_R uint32_t PID3; - FWK_R uint32_t ID0; - FWK_R uint32_t ID1; - FWK_R uint32_t ID2; - FWK_R uint32_t ID3; -}; - -#define SYSTEM_PIK_PTR ((struct pik_system_reg *)SCP_PIK_SYSTEM_BASE) - -#endif /* SYSTEM_PIK_H */ diff --git a/product/tc0/include/tc0_core.h b/product/tc0/include/tc0_core.h deleted file mode 100644 index 41734d3e4c91..000000000000 --- a/product/tc0/include/tc0_core.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef TC0_CORE_H -#define TC0_CORE_H - -#include <fwk_assert.h> - -#define TC0_CORE_PER_CLUSTER_MAX 8 - -#define CORES_PER_CLUSTER 8 -#define NUMBER_OF_CLUSTERS 1 - -static inline unsigned int tc0_core_get_cluster_count(void) -{ - return NUMBER_OF_CLUSTERS; -} - -static inline unsigned int tc0_core_get_core_per_cluster_count( - unsigned int cluster) -{ - fwk_assert(cluster < tc0_core_get_cluster_count()); - - return CORES_PER_CLUSTER; -} - -static inline unsigned int tc0_core_get_core_count(void) -{ - return tc0_core_get_core_per_cluster_count(0) * - tc0_core_get_cluster_count(); -} - -#endif /* TC0_CORE_H */ diff --git a/product/tc0/include/tc0_dvfs.h b/product/tc0/include/tc0_dvfs.h deleted file mode 100644 index bcf8ebf7bbcf..000000000000 --- a/product/tc0/include/tc0_dvfs.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * Definitions for DVFS module configuration. - */ - -#ifndef SCP_TC0_DVFS_H -#define SCP_TC0_DVFS_H - -enum dvfs_element_idx { - DVFS_ELEMENT_IDX_KLEIN, - DVFS_ELEMENT_IDX_MATTERHORN, - DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM, - DVFS_ELEMENT_IDX_COUNT -}; - -#endif /* SCP_TC0_DVFS_H */ diff --git a/product/tc0/include/tc0_mock_psu.h b/product/tc0/include/tc0_mock_psu.h deleted file mode 100644 index ee2af8f611f5..000000000000 --- a/product/tc0/include/tc0_mock_psu.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * Definitions for mock PSU module configuration. - */ - -#ifndef SCP_TC0_MOCK_PSU_H -#define SCP_TC0_MOCK_PSU_H - -enum mock_psu_id { - MOCK_PSU_ELEMENT_IDX_KLEIN, - MOCK_PSU_ELEMENT_IDX_MATTERHORN, - MOCK_PSU_ELEMENT_IDX_MATTERHORN_ELP_ARM, - MOCK_PSU_ELEMENT_IDX_COUNT, -}; - -#endif /* SCP_TC0_MOCK_PSU_H */ diff --git a/product/tc0/include/tc0_power_domain.h b/product/tc0/include/tc0_power_domain.h deleted file mode 100644 index 9a7636d13f1d..000000000000 --- a/product/tc0/include/tc0_power_domain.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef TC0_POWER_DOMAIN_H -#define TC0_POWER_DOMAIN_H - -#include <mod_power_domain.h> - -/*! Mask for the cluster valid power states */ -#define TC0_CLUSTER_VALID_STATE_MASK \ - (MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK) - -/*! Mask for the core valid power states */ -#define TC0_CORE_VALID_STATE_MASK (MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK) - -#endif /* TC0_POWER_DOMAIN_H */ diff --git a/product/tc0/include/tc0_psu.h b/product/tc0/include/tc0_psu.h deleted file mode 100644 index 68af8e913996..000000000000 --- a/product/tc0/include/tc0_psu.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * Definitions for PSU module configuration. - */ - -#ifndef SCP_TC0_PSU_H -#define SCP_TC0_PSU_H - -enum psu_id { - PSU_ELEMENT_IDX_KLEIN, - PSU_ELEMENT_IDX_MATTERHORN, - PSU_ELEMENT_IDX_MATTERHORN_ELP_ARM, - PSU_ELEMENT_IDX_COUNT, -}; - -#endif /* SCP_TC0_PSU_H */ diff --git a/product/tc0/include/tc0_scmi.h b/product/tc0/include/tc0_scmi.h deleted file mode 100644 index c6d92dc4dd03..000000000000 --- a/product/tc0/include/tc0_scmi.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * Definitions for SCMI and TRANSPORT module configurations. - */ - -#ifndef SCP_TC0_SCMI_H -#define SCP_TC0_SCMI_H - -/* SCMI agent identifiers */ -enum scp_tc0_scmi_agent_id { - /* 0 is reserved for the platform */ - SCP_SCMI_AGENT_ID_OSPM = 1, - SCP_SCMI_AGENT_ID_PSCI, - SCP_SCMI_AGENT_ID_COUNT -}; - -/* SCMI service indexes */ -enum scp_tc0_scmi_service_idx { - SCP_TC0_SCMI_SERVICE_IDX_PSCI, - SCP_TC0_SCMI_SERVICE_IDX_OSPM_0, - SCP_TC0_SCMI_SERVICE_IDX_OSPM_1, - SCP_TC0_SCMI_SERVICE_IDX_COUNT, -}; - -#endif /* SCP_TC0_SCMI_H */ diff --git a/product/tc0/include/tc0_sds.h b/product/tc0/include/tc0_sds.h deleted file mode 100644 index 826d7f1ffa02..000000000000 --- a/product/tc0/include/tc0_sds.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef TC0_SDS_H -#define TC0_SDS_H - -#include <mod_sds.h> - -/* - * Structure identifiers. - */ -enum tc0_sds_struct_id { - TC0_SDS_CPU_INFO = 1 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), - TC0_SDS_FEATURE_AVAILABILITY = 6 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), - TC0_SDS_BOOTLOADER = 9 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), -}; - -enum tc0_sds_region_idx { TC0_SDS_REGION_SECURE, TC0_SDS_REGION_COUNT }; - -/* - * Structure sizes. - */ -#define TC0_SDS_CPU_INFO_SIZE 4 -#define TC0_SDS_FEATURE_AVAILABILITY_SIZE 4 -#define TC0_SDS_BOOTLOADER_SIZE 12 - -/* - * Field masks and offsets for TC0_SDS_AP_CPU_INFO structure. - */ -#define TC0_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF -#define TC0_SDS_CPU_INFO_PRIMARY_POS 0 - -/* - * Field masks and offsets for TC0_SDS_FEATURE_AVAILABILITY structure. - */ -#define TC0_SDS_FEATURE_FIRMWARE_MASK 0x1 -#define TC0_SDS_FEATURE_DMC_MASK 0x2 -#define TC0_SDS_FEATURE_MESSAGING_MASK 0x4 - -#define TC0_SDS_FEATURE_FIRMWARE_POS 0 -#define TC0_SDS_FEATURE_DMC_POS 1 -#define TC0_SDS_FEATURE_MESSAGING_POS 2 - -/* - * Field masks and offsets for the TC0_SDS_BOOTLOADER structure. - */ -#define TC0_SDS_BOOTLOADER_VALID_MASK 0x1 -#define TC0_SDS_BOOTLOADER_OFFSET_MASK 0xFFFFFFFF -#define TC0_SDS_BOOTLOADER_SIZE_MASK 0xFFFFFFFF - -#define TC0_SDS_BOOTLOADER_VALID_POS 0 -#define TC0_SDS_BOOTLOADER_OFFSET_POS 0 -#define TC0_SDS_BOOTLOADER_SIZE_POS 0 - -#endif /* TC0_SDS_H */ diff --git a/product/tc0/include/tc0_timer.h b/product/tc0/include/tc0_timer.h deleted file mode 100644 index 62eea68e92bf..000000000000 --- a/product/tc0/include/tc0_timer.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CONFIG_TIMER_H -#define CONFIG_TIMER_H - -enum config_timer_refclk_sub_element_idx { - CONFIG_TIMER_DVFS_CPU_KLEIN, - CONFIG_TIMER_DVFS_CPU_MATTERHORN, - CONFIG_TIMER_DVFS_CPU_MATTERHORN_ELP_ARM, - -#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS - CONFIG_TIMER_FAST_CHANNEL_TIMER_IDX, -#endif - - CONFIG_TIMER_SUB_ELEMENT_IDX_COUNT, -}; - -#endif /* CONFIG_TIMER_H */ diff --git a/product/tc0/module/tc0_power_model/CMakeLists.txt b/product/tc0/module/tc0_power_model/CMakeLists.txt deleted file mode 100644 index 8de67def73f4..000000000000 --- a/product/tc0/module/tc0_power_model/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# -add_library(${SCP_MODULE_TARGET} SCP_MODULE) - -target_include_directories(${SCP_MODULE_TARGET} - PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") - -target_sources(${SCP_MODULE_TARGET} - PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_tc0_power_model.c") - -target_link_libraries(${SCP_MODULE_TARGET} - PRIVATE module-thermal-mgmt module-scmi-perf) diff --git a/product/tc0/module/tc0_power_model/Module.cmake b/product/tc0/module/tc0_power_model/Module.cmake deleted file mode 100644 index adf1aebd90a6..000000000000 --- a/product/tc0/module/tc0_power_model/Module.cmake +++ /dev/null @@ -1,10 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -set(SCP_MODULE "tc0-power-model") - -set(SCP_MODULE_TARGET "module-tc0-power-model") diff --git a/product/tc0/module/tc0_power_model/include/mod_tc0_power_model.h b/product/tc0/module/tc0_power_model/include/mod_tc0_power_model.h deleted file mode 100644 index e6d93a87b758..000000000000 --- a/product/tc0/module/tc0_power_model/include/mod_tc0_power_model.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * TC0 Power Model (Thermal Management Driver) - */ - -#ifndef MOD_TC0_POWER_MODEL_H -#define MOD_TC0_POWER_MODEL_H - -//#include <mod_power_domain.h> - -/*! - * \addtogroup GroupTC0Module TC0 Product Modules - * \{ - */ - -/*! - * \defgroup GroupTC0PowerModel TC0 Power Model - * \{ - */ - -/*! - * \brief TC0 Power Model element configuration - */ -struct mod_tc0_power_model_dev_config { - /*! - * \brief Coefficient to compute the power from level and viceversa. - * - * \details This is an oversimplified example of element configuration. For - * the purpose of code reference, we assume that power and level are - * tied each other by a simple coefficient. - */ - unsigned int coeff; -}; - -/*! - * \brief Number of defined APIs for Power Model. - */ -enum mod_tc0_power_model_api_idx { - /*! API index for the driver interface of the Thermal Management module */ - MOD_TC0_POWER_MODEL_THERMAL_DRIVER_API_IDX, - - /*! Number of exposed interfaces */ - MOD_TC0_POWER_MODEL_API_COUNT, -}; - -/*! - * \} - */ - -/*! - * \} - */ - -#endif /* MOD_TC0_POWER_MODEL_H */ diff --git a/product/tc0/module/tc0_power_model/src/mod_tc0_power_model.c b/product/tc0/module/tc0_power_model/src/mod_tc0_power_model.c deleted file mode 100644 index a4f4cb38d4fa..000000000000 --- a/product/tc0/module/tc0_power_model/src/mod_tc0_power_model.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * TC0 Power Model. - */ - -#include <mod_tc0_power_model.h> -#include <mod_thermal_mgmt.h> - -#include <fwk_id.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <stdint.h> - -uint32_t tc0_pm_level_to_power(fwk_id_t pm_id, const uint32_t level) -{ - const struct mod_tc0_power_model_dev_config *config; - - config = fwk_module_get_data(pm_id); - return (config->coeff * level); -} - -uint32_t tc0_pm_power_to_level(fwk_id_t pm_id, const uint32_t power) -{ - const struct mod_tc0_power_model_dev_config *config; - - config = fwk_module_get_data(pm_id); - return (power / config->coeff); -} - -static const struct mod_thermal_mgmt_driver_api tc0_thermal_mgmt_driver_api = { - .level_to_power = tc0_pm_level_to_power, - .power_to_level = tc0_pm_power_to_level, -}; - -/* - * Framework handlers. - */ - -static int tc0_power_model_mod_init( - fwk_id_t module_id, - unsigned int unused, - const void *data) -{ - return FWK_SUCCESS; -} - -static int tc0_power_model_elem_init( - fwk_id_t element_id, - unsigned int sub_element_count, - const void *data) -{ - return FWK_SUCCESS; -} - -static int tc0_power_model_bind(fwk_id_t id, unsigned int round) -{ - return FWK_SUCCESS; -} - -static int tc0_power_model_process_bind_request( - fwk_id_t requester_id, - fwk_id_t pd_id, - fwk_id_t api_id, - const void **api) -{ - fwk_id_t power_model_api_id = FWK_ID_API( - FWK_MODULE_IDX_TC0_POWER_MODEL, - MOD_TC0_POWER_MODEL_THERMAL_DRIVER_API_IDX); - - if (fwk_id_is_equal(api_id, power_model_api_id)) { - *api = &tc0_thermal_mgmt_driver_api; - - return FWK_SUCCESS; - } - - return FWK_E_ACCESS; -} - -const struct fwk_module module_tc0_power_model = { - .type = FWK_MODULE_TYPE_DRIVER, - .api_count = 1, - .init = tc0_power_model_mod_init, - .element_init = tc0_power_model_elem_init, - .bind = tc0_power_model_bind, - .process_bind_request = tc0_power_model_process_bind_request, -}; diff --git a/product/tc0/module/tc0_system/CMakeLists.txt b/product/tc0/module/tc0_system/CMakeLists.txt deleted file mode 100644 index 336f3352bbc8..000000000000 --- a/product/tc0/module/tc0_system/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# -add_library(${SCP_MODULE_TARGET} SCP_MODULE) - -target_include_directories(${SCP_MODULE_TARGET} - PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include") - -target_sources(${SCP_MODULE_TARGET} - PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/src/mod_tc0_system.c") - -target_link_libraries(${SCP_MODULE_TARGET} - PRIVATE module-clock module-sds module-power-domain module-ppu-v1 - module-scmi module-system-power) diff --git a/product/tc0/module/tc0_system/Module.cmake b/product/tc0/module/tc0_system/Module.cmake deleted file mode 100644 index 4d46ef99c1e4..000000000000 --- a/product/tc0/module/tc0_system/Module.cmake +++ /dev/null @@ -1,10 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -set(SCP_MODULE "tc0-system") - -set(SCP_MODULE_TARGET "module-tc0-system") diff --git a/product/tc0/module/tc0_system/include/mod_tc0_system.h b/product/tc0/module/tc0_system/include/mod_tc0_system.h deleted file mode 100644 index c706f9388b97..000000000000 --- a/product/tc0/module/tc0_system/include/mod_tc0_system.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * TC0 System Support - */ - -#ifndef MOD_TC0_SYSTEM_H -#define MOD_TC0_SYSTEM_H - -#include <mod_power_domain.h> - -/*! - * \addtogroup GroupTC0Module TC0 Product Modules - * \{ - */ - -/*! - * \defgroup GroupTC0System TC0 System Support - * \{ - */ - -/*! - * \brief Additional TC0 system power states. - */ -enum mod_tc0_system_power_states { - MOD_TC0_SYSTEM_POWER_STATE_SLEEP0 = MOD_PD_STATE_COUNT, - MOD_TC0_SYSTEM_POWER_STATE_SLEEP1, - MOD_TC0_SYSTEM_POWER_STATE_COUNT -}; - -/*! - * \brief System power state masks. - */ -enum mod_tc0_system_power_state_masks { - MOD_TC0_SYSTEM_POWER_STATE_SLEEP0_MASK = - (1 << MOD_TC0_SYSTEM_POWER_STATE_SLEEP0), - MOD_TC0_SYSTEM_POWER_STATE_SLEEP1_MASK = - (1 << MOD_TC0_SYSTEM_POWER_STATE_SLEEP1), -}; - -/*! - * \brief Indices of the interfaces exposed by the module. - */ -enum mod_tc0_system_api_idx { - /*! API index for the driver interface of the SYSTEM POWER module */ - MOD_TC0_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER, - - /*! Number of exposed interfaces */ - MOD_TC0_SYSTEM_API_COUNT -}; - -/*! - * \} - */ - -/*! - * \} - */ - -#endif /* MOD_TC0_SYSTEM_H */ diff --git a/product/tc0/module/tc0_system/src/mod_tc0_system.c b/product/tc0/module/tc0_system/src/mod_tc0_system.c deleted file mode 100644 index 741c61faa26d..000000000000 --- a/product/tc0/module/tc0_system/src/mod_tc0_system.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * TC0 System Support. - */ - -#include "clock_soc.h" -#include "scp_pik.h" -#include "tc0_core.h" -#include "tc0_scmi.h" -#include "tc0_sds.h" - -#include <mod_clock.h> -#include <mod_power_domain.h> -#include <mod_ppu_v1.h> -#include <mod_scmi.h> -#include <mod_sds.h> -#include <mod_system_power.h> -#include <mod_tc0_system.h> - -#include <fwk_assert.h> -#include <fwk_id.h> -#include <fwk_interrupt.h> -#include <fwk_log.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> -#include <fwk_notification.h> - -#include <fmw_cmsis.h> - -#include <stdint.h> - -/* SCMI services required to enable the messaging stack */ -static unsigned int scmi_notification_table[] = { - SCP_TC0_SCMI_SERVICE_IDX_PSCI, -}; - -/* Module context */ -struct tc0_system_ctx { - /* Pointer to the Interrupt Service Routine API of the PPU_V1 module */ - const struct ppu_v1_isr_api *ppu_v1_isr_api; - - /* Power domain module restricted API pointer */ - struct mod_pd_restricted_api *mod_pd_restricted_api; - - /* SDS API pointer */ - const struct mod_sds_api *sds_api; -}; - -struct tc0_system_isr { - unsigned int interrupt; - void (*handler)(void); -}; - -static struct tc0_system_ctx tc0_system_ctx; -const struct fwk_module_config config_tc0_system = { 0 }; - -static const uint32_t feature_flags = - (TC0_SDS_FEATURE_FIRMWARE_MASK | TC0_SDS_FEATURE_DMC_MASK | - TC0_SDS_FEATURE_MESSAGING_MASK); - -static fwk_id_t sds_feature_availability_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SDS, 1); - -/* - * SCMI Messaging stack - */ - -static int messaging_stack_ready(void) -{ - const struct mod_sds_structure_desc *sds_structure_desc = - fwk_module_get_data(sds_feature_availability_id); - - /* - * Write SDS Feature Availability to signal the completion of the messaging - * stack - */ - return tc0_system_ctx.sds_api->struct_write( - sds_structure_desc->id, - 0, - (void *)(&feature_flags), - sds_structure_desc->size); -} - -/* - * System power's driver API - */ - -static int tc0_system_shutdown(enum mod_pd_system_shutdown system_shutdown) -{ - NVIC_SystemReset(); - - return FWK_E_DEVICE; -} - -static const struct mod_system_power_driver_api - tc0_system_system_power_driver_api = { - .system_shutdown = tc0_system_shutdown, - }; - -/* - * Functions fulfilling the framework's module interface - */ - -static int tc0_system_mod_init( - fwk_id_t module_id, - unsigned int unused, - const void *unused2) -{ - return FWK_SUCCESS; -} - -static int tc0_system_bind(fwk_id_t id, unsigned int round) -{ - int status; - - if (round > 0) { - return FWK_SUCCESS; - } - - status = fwk_module_bind( - FWK_ID_MODULE(FWK_MODULE_IDX_POWER_DOMAIN), - FWK_ID_API(FWK_MODULE_IDX_POWER_DOMAIN, MOD_PD_API_IDX_RESTRICTED), - &tc0_system_ctx.mod_pd_restricted_api); - if (status != FWK_SUCCESS) { - return status; - } - - status = fwk_module_bind( - FWK_ID_MODULE(FWK_MODULE_IDX_PPU_V1), - FWK_ID_API(FWK_MODULE_IDX_PPU_V1, MOD_PPU_V1_API_IDX_ISR), - &tc0_system_ctx.ppu_v1_isr_api); - if (status != FWK_SUCCESS) { - return status; - } - - return fwk_module_bind( - fwk_module_id_sds, - FWK_ID_API(FWK_MODULE_IDX_SDS, 0), - &tc0_system_ctx.sds_api); -} - -static int tc0_system_process_bind_request( - fwk_id_t requester_id, - fwk_id_t pd_id, - fwk_id_t api_id, - const void **api) -{ - *api = &tc0_system_system_power_driver_api; - return FWK_SUCCESS; -} - -static int tc0_system_start(fwk_id_t id) -{ - int status; - unsigned int i; - - /* - * Subscribe to these SCMI channels in order to know when they have all - * initialized. - * At that point we can consider the SCMI stack to be initialized from - * the point of view of the PSCI agent. - */ - for (i = 0; i < FWK_ARRAY_SIZE(scmi_notification_table); i++) { - status = fwk_notification_subscribe( - mod_scmi_notification_id_initialized, - fwk_id_build_element_id( - fwk_module_id_scmi, scmi_notification_table[i]), - id); - if (status != FWK_SUCCESS) { - return status; - } - } - - /* - * Subscribe to the SDS initialized notification so we can correctly let the - * PSCI agent know that the SCMI stack is initialized. - */ - status = fwk_notification_subscribe( - mod_sds_notification_id_initialized, fwk_module_id_sds, id); - if (status != FWK_SUCCESS) { - return status; - } - - return tc0_system_ctx.mod_pd_restricted_api->set_state( - FWK_ID_ELEMENT(FWK_MODULE_IDX_POWER_DOMAIN, 0), - MOD_PD_SET_STATE_NO_RESP, - MOD_PD_COMPOSITE_STATE( - MOD_PD_LEVEL_2, - 0, - MOD_PD_STATE_ON, - MOD_PD_STATE_OFF, - MOD_PD_STATE_OFF)); -} - -static int tc0_system_process_notification( - const struct fwk_event *event, - struct fwk_event *resp_event) -{ - static unsigned int scmi_notification_count = 0; - static bool sds_notification_received = false; - - fwk_assert(fwk_id_is_type(event->target_id, FWK_ID_TYPE_MODULE)); - - if (fwk_id_is_equal(event->id, mod_scmi_notification_id_initialized)) { - scmi_notification_count++; - } else if (fwk_id_is_equal( - event->id, mod_sds_notification_id_initialized)) { - sds_notification_received = true; - } else { - return FWK_E_PARAM; - } - - if ((scmi_notification_count == FWK_ARRAY_SIZE(scmi_notification_table)) && - sds_notification_received) { - messaging_stack_ready(); - - scmi_notification_count = 0; - sds_notification_received = false; - } - - return FWK_SUCCESS; -} - -const struct fwk_module module_tc0_system = { - .type = FWK_MODULE_TYPE_DRIVER, - .api_count = MOD_TC0_SYSTEM_API_COUNT, - .init = tc0_system_mod_init, - .bind = tc0_system_bind, - .process_bind_request = tc0_system_process_bind_request, - .process_notification = tc0_system_process_notification, - .start = tc0_system_start, -}; diff --git a/product/tc0/product.mk b/product/tc0/product.mk deleted file mode 100644 index 1df906953dea..000000000000 --- a/product/tc0/product.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -BS_PRODUCT_NAME := tc0 -BS_FIRMWARE_LIST := scp_romfw \ - scp_ramfw diff --git a/product/tc0/scp_ramfw/Buildoptions.cmake b/product/tc0/scp_ramfw/Buildoptions.cmake deleted file mode 100644 index dca66d1e1df8..000000000000 --- a/product/tc0/scp_ramfw/Buildoptions.cmake +++ /dev/null @@ -1,17 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -cmake_dependent_option( - SCP_ENABLE_SCMI_PERF_FAST_CHANNELS "Enable the SCMI-perf Fast Channels ?" - "${SCP_ENABLE_SCMI_PERF_FAST_CHANNELS_INIT}" - "DEFINED SCP_ENABLE_SCMI_PERF_FAST_CHANNELS_INIT" - "${SCP_ENABLE_SCMI_PERF_FAST_CHANNELS}") - -cmake_dependent_option( - SCP_ENABLE_PLUGIN_HANDLER "Enable the Performance Plugin Handler ?" - "${SCP_ENABLE_PLUGIN_HANDLER_INIT}" "DEFINED SCP_ENABLE_PLUGIN_HANDLER_INIT" - "${SCP_ENABLE_PLUGIN_HANDLER}") diff --git a/product/tc0/scp_ramfw/CMakeLists.txt b/product/tc0/scp_ramfw/CMakeLists.txt deleted file mode 100644 index f7feab9b3027..000000000000 --- a/product/tc0/scp_ramfw/CMakeLists.txt +++ /dev/null @@ -1,127 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -# -# Create the firmware target. -# - -add_executable(tc0-bl2) - - -# SCP_PLATFORM_VARIANT options: -# - 'TC0_VARIANT_STD' for TC0 standard build -# - 'TC0_VAR_EXPERIMENT_POWER' for TC0 with power/performance plugins used for -# evaluation purposes - - -target_compile_definitions(tc0-bl2 PUBLIC -DTC0_VARIANT_STD=0) -target_compile_definitions(tc0-bl2 PUBLIC -DTC0_VAR_EXPERIMENT_POWER=1) - - -set(SCP_PLATFORM_VARIANT ${SCP_PLATFORM_VARIANT_INIT} CACHE STRING "1") - - -if (SCP_PLATFORM_VARIANT STREQUAL "1") - message(NOTICE "SCP_PLATFORM_VARIANT set to EXPERIMENT_POWER (tc0-bl2)\n") - - target_compile_definitions(tc0-bl2 - PUBLIC -DPLATFORM_VARIANT=TC0_VAR_EXPERIMENT_POWER) - - set(SCP_ENABLE_PLUGIN_HANDLER TRUE PARENT_SCOPE) - set(SCP_ENABLE_SCMI_PERF_FAST_CHANNELS TRUE PARENT_SCOPE) - -# The order of the modules in the following list is appended on the list of -# modules defined in Firmware.cmake. - - list(APPEND SCP_MODULES "traffic-cop") - target_sources(tc0-bl2 PRIVATE "config_traffic_cop.c") - - list(APPEND SCP_MODULES "mpmm") - target_sources(tc0-bl2 PRIVATE "config_mpmm.c") - - list(APPEND SCP_MODULES "sensor") - target_sources(tc0-bl2 PRIVATE "config_sensor.c") - - list(APPEND SCP_MODULES "reg-sensor") - target_sources(tc0-bl2 PRIVATE "config_reg_sensor.c") - - list(APPEND SCP_MODULES "thermal-mgmt") - target_sources(tc0-bl2 PRIVATE "config_thermal_mgmt.c") - - list(APPEND SCP_MODULES "tc0-power-model") - list(PREPEND SCP_MODULE_PATHS - "${CMAKE_CURRENT_LIST_DIR}/../module/tc0_power_model") - target_sources(tc0-bl2 PRIVATE "config_tc0_power_model.c") - -else() - message(NOTICE "SCP_PLATFORM_VARIANT set to STANDARD (tc0-bl2)\n") - - target_compile_definitions(tc0-bl2 - PUBLIC -DPLATFORM_VARIANT=TC0_VARIANT_STD) -endif() - - -target_include_directories( - tc0-bl2 PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/../include" - "${CMAKE_CURRENT_SOURCE_DIR}") - -# cmake-lint: disable=E1122 - -target_sources( - tc0-bl2 - PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_system_power.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_armv7m_mpu.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_pl011.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_power_domain.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_ppu_v1.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_mhu2.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_transport.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_sds.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_system_power.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_clock.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_perf.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_gtimer.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_timer.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_dvfs.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_psu.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_mock_voltage_domain.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_voltage_domain.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_voltage_domain.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_mock_psu.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_system_pll.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_pik_clock.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_css_clock.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_scmi_power_domain.c") - -if(SCP_ENABLE_RESOURCE_PERMISSIONS) - target_sources(tc0-bl2 PRIVATE "config_resource_perms.c") -endif() - - -# -# Some of our firmware includes require CMSIS. -# - -target_link_libraries(tc0-bl2 PUBLIC cmsis::core-m) - -# -# We explicitly add the CMSIS include directories to our interfaceinclude -# directories. Each module target adds these include directories totheir own, -# allowing them to include any firmware includes we expose. -# - -target_include_directories(tc0-bl2 - PUBLIC $<TARGET_PROPERTY:cmsis::core-m,INTERFACE_INCLUDE_DIRECTORIES>) - -if(SCP_ENABLE_RESOURCE_PERMISSIONS) - list(APPEND SCP_MODULES "resource-perms") -endif() - -set(SCP_MODULES ${SCP_MODULES} PARENT_SCOPE) -set(SCP_MODULE_PATHS ${SCP_MODULE_PATHS} PARENT_SCOPE) diff --git a/product/tc0/scp_ramfw/Firmware.cmake b/product/tc0/scp_ramfw/Firmware.cmake deleted file mode 100644 index 0c37c8ad4b80..000000000000 --- a/product/tc0/scp_ramfw/Firmware.cmake +++ /dev/null @@ -1,65 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -# -# Configure the build system. -# - -set(SCP_FIRMWARE "tc0-bl2") - -set(SCP_FIRMWARE_TARGET "tc0-bl2") - -set(SCP_TOOLCHAIN_INIT "GNU") - -set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) - -set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) - -set(SCP_ENABLE_RESOURCE_PERMISSIONS_INIT TRUE) - -set(SCP_ENABLE_IPO_INIT FALSE) - -set(SCP_ENABLE_SCMI_PERF_FAST_CHANNELS_INIT FALSE) - -set(SCP_ENABLE_PLUGIN_HANDLER_INIT FALSE) - -set(SCP_PLATFORM_VARIANT_INIT 0) - -set(SCP_ARCHITECTURE "arm-m") - -list(PREPEND SCP_MODULE_PATHS "${CMAKE_CURRENT_LIST_DIR}/../module/tc0_system") - -# The order of the modules in the following list is the order in which the -# modules are initialized, bound, started during the pre-runtime phase. -# any change in the order will cause firmware initialization errors. - -list(APPEND SCP_MODULES "armv7m-mpu") -list(APPEND SCP_MODULES "pl011") -list(APPEND SCP_MODULES "gtimer") -list(APPEND SCP_MODULES "timer") -list(APPEND SCP_MODULES "ppu-v1") -list(APPEND SCP_MODULES "system-power") -list(APPEND SCP_MODULES "mhu2") -list(APPEND SCP_MODULES "transport") -list(APPEND SCP_MODULES "scmi") -list(APPEND SCP_MODULES "sds") -list(APPEND SCP_MODULES "system-pll") -list(APPEND SCP_MODULES "pik-clock") -list(APPEND SCP_MODULES "css-clock") -list(APPEND SCP_MODULES "clock") -list(APPEND SCP_MODULES "power-domain") -list(APPEND SCP_MODULES "scmi-power-domain") -list(APPEND SCP_MODULES "scmi-system-power") -list(APPEND SCP_MODULES "dvfs") -list(APPEND SCP_MODULES "scmi-clock") -list(APPEND SCP_MODULES "scmi-perf") -list(APPEND SCP_MODULES "mock-psu") -list(APPEND SCP_MODULES "psu") -list(APPEND SCP_MODULES "mock-voltage-domain") -list(APPEND SCP_MODULES "voltage-domain") -list(APPEND SCP_MODULES "scmi-voltage-domain") -list(APPEND SCP_MODULES "tc0-system") diff --git a/product/tc0/scp_ramfw/Toolchain-ArmClang.cmake b/product/tc0/scp_ramfw/Toolchain-ArmClang.cmake deleted file mode 100644 index 538e71a68663..000000000000 --- a/product/tc0/scp_ramfw/Toolchain-ArmClang.cmake +++ /dev/null @@ -1,20 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -# cmake-lint: disable=C0301 - -include_guard() - -set(CMAKE_SYSTEM_PROCESSOR "cortex-m3") - -set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") -set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") -set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") - -include( - "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/ArmClang-Baremetal.cmake" -) diff --git a/product/tc0/scp_ramfw/Toolchain-Clang.cmake b/product/tc0/scp_ramfw/Toolchain-Clang.cmake deleted file mode 100644 index 7598d559f8be..000000000000 --- a/product/tc0/scp_ramfw/Toolchain-Clang.cmake +++ /dev/null @@ -1,17 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -include_guard() - -set(CMAKE_SYSTEM_PROCESSOR "cortex-m3") - -set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") -set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") -set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") - -include( - "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/Clang-Baremetal.cmake") diff --git a/product/tc0/scp_ramfw/Toolchain-GNU.cmake b/product/tc0/scp_ramfw/Toolchain-GNU.cmake deleted file mode 100644 index a1fe8de32777..000000000000 --- a/product/tc0/scp_ramfw/Toolchain-GNU.cmake +++ /dev/null @@ -1,18 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -include_guard() - -set(CMAKE_SYSTEM_PROCESSOR "cortex-m3") -set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") - -set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") -set(CMAKE_C_COMPILER_TARGET "arm-none-eabi") -set(CMAKE_CXX_COMPILER_TARGET "arm-none-eabi") - -include( - "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/GNU-Baremetal.cmake") diff --git a/product/tc0/scp_ramfw/config_armv7m_mpu.c b/product/tc0/scp_ramfw/config_armv7m_mpu.c deleted file mode 100644 index d6b95ebc9ce3..000000000000 --- a/product/tc0/scp_ramfw/config_armv7m_mpu.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "scp_mmap.h" -#include "scp_software_mmap.h" - -#include <mod_armv7m_mpu.h> - -#include <fwk_macros.h> -#include <fwk_module.h> - -#include <fmw_cmsis.h> - -static const ARM_MPU_Region_t regions[] = { - { - /* 0x0000_0000 - 0xFFFF_FFFF */ - .RBAR = ARM_MPU_RBAR(0, 0x00000000), - .RASR = ARM_MPU_RASR( - 1, - ARM_MPU_AP_PRIV, - 0, - 1, - 0, - 1, - 0, - ARM_MPU_REGION_SIZE_4GB), - }, - { - /* 0x1000_0000 - 0x1007_FFFF */ - .RBAR = ARM_MPU_RBAR(1, SCP_RAM_BASE), - .RASR = ARM_MPU_RASR( - 0, - ARM_MPU_AP_PRIV, - 0, - 0, - 1, - 1, - 0, - ARM_MPU_REGION_SIZE_512KB), - }, - { - /* 0xA400_0000 - 0xA400_7FFF*/ - .RBAR = ARM_MPU_RBAR(2, SCP_TRUSTED_RAM_BASE), - .RASR = ARM_MPU_RASR( - 1, - ARM_MPU_AP_PRIV, - 0, - 1, - 1, - 1, - 0, - ARM_MPU_REGION_SIZE_4KB), - }, - { - /* 0xA600_0000 - 0xA600_7FFF */ - .RBAR = ARM_MPU_RBAR(3, SCP_NONTRUSTED_RAM_BASE), - .RASR = ARM_MPU_RASR( - 1, - ARM_MPU_AP_PRIV, - 0, - 1, - 1, - 1, - 0, - ARM_MPU_REGION_SIZE_256B), - }, -}; - -const struct fwk_module_config config_armv7m_mpu = { - .data = &((struct mod_armv7m_mpu_config){ - .region_count = FWK_ARRAY_SIZE(regions), - .regions = regions, - }), -}; diff --git a/product/tc0/scp_ramfw/config_clock.c b/product/tc0/scp_ramfw/config_clock.c deleted file mode 100644 index a11db4f63d3f..000000000000 --- a/product/tc0/scp_ramfw/config_clock.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "config_power_domain.h" -#include "tc0_core.h" - -#include <mod_clock.h> -#include <mod_css_clock.h> -#include <mod_pik_clock.h> -#include <mod_power_domain.h> -#include <mod_system_pll.h> - -#include <fwk_element.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -static const struct fwk_element clock_dev_desc_table[] = { - [CLOCK_IDX_CPU_GROUP_KLEIN] = - { - .name = "CPU_GROUP_KLEIN", - .data = &((struct mod_clock_dev_config){ - .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_KLEIN), - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), - }), - }, - [CLOCK_IDX_CPU_GROUP_MATTERHORN] = - { - .name = "CPU_GROUP_MATTERHORN", - .data = &((struct mod_clock_dev_config){ - .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_MATTERHORN), - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), - }), - }, - [CLOCK_IDX_CPU_GROUP_MATTERHORN_ELP_ARM] = - { - .name = "CPU_GROUP_MATTERHORN_ELP_ARM", - .data = &((struct mod_clock_dev_config){ - .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_MATTERHORN_ELP_ARM), - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), - }), - }, - [CLOCK_IDX_DPU] = - { - .name = "DPU", - .data = &((struct mod_clock_dev_config){ - .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_DPU), - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), - }), - }, - [CLOCK_IDX_PIXEL_0] = - { - .name = "PIXEL_0", - .data = &((struct mod_clock_dev_config){ - .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_PIX0), - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - }), - }, - [CLOCK_IDX_PIXEL_1] = - { - .name = "PIXEL_1", - .data = &((struct mod_clock_dev_config){ - .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_PIX1), - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - }), - }, - { 0 }, /* Termination description. */ -}; - -static const struct fwk_element *clock_get_dev_desc_table(fwk_id_t module_id) -{ - unsigned int i; - struct mod_clock_dev_config *dev_config; - - for (i = 0; i < CLOCK_IDX_COUNT; i++) { - dev_config = - (struct mod_clock_dev_config *)clock_dev_desc_table[i].data; - dev_config->pd_source_id = fwk_id_build_element_id( - fwk_module_id_power_domain, - tc0_core_get_core_count() + tc0_core_get_cluster_count() + - PD_STATIC_DEV_IDX_SYSTOP); - } - - return clock_dev_desc_table; -} - -const struct fwk_module_config config_clock = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(clock_get_dev_desc_table), - .data = &((struct mod_clock_config){ - .pd_transition_notification_id = FWK_ID_NOTIFICATION_INIT( - FWK_MODULE_IDX_POWER_DOMAIN, - MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), - .pd_pre_transition_notification_id = FWK_ID_NOTIFICATION_INIT( - FWK_MODULE_IDX_POWER_DOMAIN, - MOD_PD_NOTIFICATION_IDX_POWER_STATE_PRE_TRANSITION), - }), - -}; diff --git a/product/tc0/scp_ramfw/config_css_clock.c b/product/tc0/scp_ramfw/config_css_clock.c deleted file mode 100644 index 7691b21eed2d..000000000000 --- a/product/tc0/scp_ramfw/config_css_clock.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" - -#include <mod_css_clock.h> -#include <mod_pik_clock.h> -#include <mod_system_pll.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -static const struct mod_css_clock_rate rate_table_cpu_group_klein[] = { - { - /* Super Underdrive */ - .rate = 768 * FWK_MHZ, - .pll_rate = 768 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Underdrive */ - .rate = 1153 * FWK_MHZ, - .pll_rate = 1153 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Nominal */ - .rate = 1537 * FWK_MHZ, - .pll_rate = 1537 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Overdrive */ - .rate = 1844 * FWK_MHZ, - .pll_rate = 1844 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Super Overdrive */ - .rate = 2152 * FWK_MHZ, - .pll_rate = 2152 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, -}; - -static const struct mod_css_clock_rate rate_table_cpu_group_matterhorn[] = { - { - /* Super Underdrive */ - .rate = 946 * FWK_MHZ, - .pll_rate = 946 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL1, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Underdrive */ - .rate = 1419 * FWK_MHZ, - .pll_rate = 1419 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL1, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Nominal */ - .rate = 1893 * FWK_MHZ, - .pll_rate = 1893 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL1, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Overdrive */ - .rate = 2271 * FWK_MHZ, - .pll_rate = 2271 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL1, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Super Overdrive */ - .rate = 2650 * FWK_MHZ, - .pll_rate = 2650 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL1, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, -}; - -static const struct mod_css_clock_rate - rate_table_cpu_group_matterhorn_elp_arm[] = { - { - /* Super Underdrive */ - .rate = 1088 * FWK_MHZ, - .pll_rate = 1088 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL2, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Underdrive */ - .rate = 1632 * FWK_MHZ, - .pll_rate = 1632 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL2, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Nominal */ - .rate = 2176 * FWK_MHZ, - .pll_rate = 2176 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL2, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Overdrive */ - .rate = 2612 * FWK_MHZ, - .pll_rate = 2612 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL2, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Super Overdrive */ - .rate = 3047 * FWK_MHZ, - .pll_rate = 3047 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC0_PLL2, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - }; - -static const fwk_id_t member_table_cpu_group_klein[] = { - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU3), -}; - -static const fwk_id_t member_table_cpu_group_matterhorn[] = { - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU4), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU5), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU6), -}; - -static const fwk_id_t member_table_cpu_group_matterhorn_elp_arm[] = { - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU7), -}; - -static const fwk_id_t member_table_dpu[] = { - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_DPU), -}; - -static const struct fwk_element css_clock_element_table[] = { - [CLOCK_CSS_IDX_CPU_GROUP_KLEIN] = - { - .name = "CPU_GROUP_KLEIN", - .data = &((struct mod_css_clock_dev_config){ - .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), - .clock_switching_source = - MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, - .pll_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_KLEIN), - .pll_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_klein, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_klein), - .member_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 1537 * FWK_MHZ, - .modulation_supported = true, - }), - }, - [CLOCK_CSS_IDX_CPU_GROUP_MATTERHORN] = - { - .name = "CPU_GROUP_MATTERHORN", - .data = &((struct mod_css_clock_dev_config){ - .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_matterhorn, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_matterhorn), - .clock_switching_source = - MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1, - .pll_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_MATTERHORN), - .pll_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_matterhorn, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_matterhorn), - .member_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 1893 * FWK_MHZ, - .modulation_supported = true, - }), - }, - [CLOCK_CSS_IDX_CPU_GROUP_MATTERHORN_ELP_ARM] = - { - .name = "CPU_GROUP_MATTERHORN_ELP_ARM", - .data = &((struct mod_css_clock_dev_config){ - .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_matterhorn_elp_arm, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_matterhorn_elp_arm), - .clock_switching_source = - MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL2, - .pll_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_MATTERHORN_ELP_ARM), - .pll_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_matterhorn_elp_arm, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_matterhorn_elp_arm), - .member_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 2176 * FWK_MHZ, - .modulation_supported = true, - }), - }, - [CLOCK_CSS_IDX_DPU] = - { - .name = "DPU", - .data = &((struct mod_css_clock_dev_config){ - .clock_type = MOD_CSS_CLOCK_TYPE_NON_INDEXED, - .clock_default_source = - MOD_PIK_CLOCK_ACLKDPU_SOURCE_DISPLAYPLLCLK, - .clock_switching_source = - MOD_PIK_CLOCK_ACLKDPU_SOURCE_SYSREFCLK, - .pll_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_DPU), - .pll_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_dpu, - .member_count = FWK_ARRAY_SIZE(member_table_dpu), - .member_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 600 * FWK_MHZ, - .modulation_supported = false, - }), - }, - [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */ -}; - -static const struct fwk_element *css_clock_get_element_table(fwk_id_t module_id) -{ - return css_clock_element_table; -} - -const struct fwk_module_config config_css_clock = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(css_clock_get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_dvfs.c b/product/tc0/scp_ramfw/config_dvfs.c deleted file mode 100644 index 26b3a4c0f765..000000000000 --- a/product/tc0/scp_ramfw/config_dvfs.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "tc0_dvfs.h" -#include "tc0_psu.h" -#include "tc0_timer.h" - -#include <mod_dvfs.h> -#include <mod_scmi_perf.h> - -#include <fwk_element.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -static struct mod_dvfs_opp operating_points_klein[] = { - { - .level = 768 * 1000000UL, - .frequency = 768 * FWK_KHZ, - .voltage = 550, - }, - { - .level = 1153 * 1000000UL, - .frequency = 1153 * FWK_KHZ, - .voltage = 650, - }, - { - .level = 1537 * 1000000UL, - .frequency = 1537 * FWK_KHZ, - .voltage = 750, - }, - { - .level = 1844 * 1000000UL, - .frequency = 1844 * FWK_KHZ, - .voltage = 850, - }, - { - .level = 2152 * 1000000UL, - .frequency = 2152 * FWK_KHZ, - .voltage = 950, - }, - { 0 } -}; - -static struct mod_dvfs_opp operating_points_matterhorn[] = { - { - .level = 946 * 1000000UL, - .frequency = 946 * FWK_KHZ, - .voltage = 550, - }, - { - .level = 1419 * 1000000UL, - .frequency = 1419 * FWK_KHZ, - .voltage = 650, - }, - { - .level = 1893 * 1000000UL, - .frequency = 1893 * FWK_KHZ, - .voltage = 750, - }, - { - .level = 2271 * 1000000UL, - .frequency = 2271 * FWK_KHZ, - .voltage = 850, - }, - { - .level = 2650 * 1000000UL, - .frequency = 2650 * FWK_KHZ, - .voltage = 950, - }, - { 0 } -}; - -static struct mod_dvfs_opp operating_points_matterhorn_elp_arm[] = { - { - .level = 1088 * 1000000UL, - .frequency = 1088 * FWK_KHZ, - .voltage = 550, - }, - { - .level = 1632 * 1000000UL, - .frequency = 1632 * FWK_KHZ, - .voltage = 650, - }, - { - .level = 2176 * 1000000UL, - .frequency = 2176 * FWK_KHZ, - .voltage = 750, - }, - { - .level = 2612 * 1000000UL, - .frequency = 2612 * FWK_KHZ, - .voltage = 850, - }, - { - .level = 3047 * 1000000UL, - .frequency = 3047 * FWK_KHZ, - .voltage = 950, - }, - { 0 } -}; - -static const struct mod_dvfs_domain_config cpu_group_klein = { - .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_KLEIN), - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_KLEIN), - .alarm_id = FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_TIMER, - 0, - CONFIG_TIMER_DVFS_CPU_KLEIN), - .retry_ms = 1, - .latency = 1200, - .sustained_idx = 2, - .opps = operating_points_klein, -}; - -static const struct mod_dvfs_domain_config cpu_group_matterhorn = { - .psu_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, PSU_ELEMENT_IDX_MATTERHORN), - .clock_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_MATTERHORN), - .alarm_id = FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_TIMER, - 0, - CONFIG_TIMER_DVFS_CPU_MATTERHORN), - .retry_ms = 1, - .latency = 1200, - .sustained_idx = 2, - .opps = operating_points_matterhorn, -}; - -static const struct mod_dvfs_domain_config cpu_group_matterhorn_elp_arm = { - .psu_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_PSU, - PSU_ELEMENT_IDX_MATTERHORN_ELP_ARM), - .clock_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_MATTERHORN_ELP_ARM), - .alarm_id = FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_TIMER, - 0, - CONFIG_TIMER_DVFS_CPU_MATTERHORN_ELP_ARM), - .retry_ms = 1, - .latency = 1200, - .sustained_idx = 2, - .opps = operating_points_matterhorn_elp_arm, -}; - -static const struct fwk_element element_table[] = { - [DVFS_ELEMENT_IDX_KLEIN] = - { - .name = "CPU_GROUP_KLEIN", - .data = &cpu_group_klein, - }, - [DVFS_ELEMENT_IDX_MATTERHORN] = - { - .name = "CPU_GROUP_MATTERHORN", - .data = &cpu_group_matterhorn, - }, - [DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM] = - { - .name = "CPU_GROUP_MATTERHORN_ELP_ARM", - .data = &cpu_group_matterhorn_elp_arm, - }, - { 0 }, -}; - -static const struct fwk_element *dvfs_get_element_table(fwk_id_t module_id) -{ - return element_table; -} - -const struct fwk_module_config config_dvfs = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(dvfs_get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_gtimer.c b/product/tc0/scp_ramfw/config_gtimer.c deleted file mode 100644 index ceebb9764c9a..000000000000 --- a/product/tc0/scp_ramfw/config_gtimer.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "scp_css_mmap.h" - -#include <mod_gtimer.h> -#include <mod_timer.h> - -#include <fwk_id.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> -#include <fwk_time.h> - -/* - * Generic timer driver config - */ -static const struct fwk_element gtimer_dev_table[] = { - [0] = { .name = "REFCLK", - .data = &((struct mod_gtimer_dev_config){ - .hw_timer = SCP_REFCLK_CNTBASE0_BASE, - .hw_counter = SCP_REFCLK_CNTCTL_BASE, - .control = SCP_REFCLK_CNTCONTROL_BASE, - .frequency = CLOCK_RATE_REFCLK, - .clock_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_KLEIN) }) }, - [1] = { 0 }, -}; - -const struct fwk_module_config config_gtimer = { - .elements = FWK_MODULE_STATIC_ELEMENTS_PTR(gtimer_dev_table), -}; - -struct fwk_time_driver fmw_time_driver(const void **ctx) -{ - return mod_gtimer_driver(ctx, config_gtimer.elements.table[0].data); -} diff --git a/product/tc0/scp_ramfw/config_mhu2.c b/product/tc0/scp_ramfw/config_mhu2.c deleted file mode 100644 index 1a3e20a2cafe..000000000000 --- a/product/tc0/scp_ramfw/config_mhu2.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "scp_css_mmap.h" -#include "scp_tc0_mhu.h" - -#include <mod_mhu2.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_module.h> - -#include <fmw_cmsis.h> - -static const struct fwk_element mhu_element_table[] = { - [SCP_TC0_MHU_DEVICE_IDX_SCP_AP_S_CLUS0] = { .name = "MHU_SCP_AP_S", - .sub_element_count = 1, - .data = &(( - struct - mod_mhu2_channel_config){ - .irq = MHU_AP_SEC_IRQ, - .recv = - SCP_MHU_SCP_AP_RCV_S_CLUS0, - .send = - SCP_MHU_SCP_AP_SND_S_CLUS0, - .channel = 0, - }) }, - [SCP_TC0_MHU_DEVICE_IDX_SCP_AP_NS_HP_CLUS0] = { .name = "MHU_SCP_AP_NS_HP", - .sub_element_count = 1, - .data = &(( - struct - mod_mhu2_channel_config){ - .irq = - MHU_AP_NONSEC_HP_IRQ, - .recv = - SCP_MHU_SCP_AP_RCV_NS_CLUS0, - .send = - SCP_MHU_SCP_AP_SND_NS_CLUS0, - .channel = 0, - }) }, - [SCP_TC0_MHU_DEVICE_IDX_SCP_AP_NS_LP_CLUS0] = { .name = "MHU_SCP_AP_NS_LP", - .sub_element_count = 1, - .data = &(( - struct - mod_mhu2_channel_config){ - .irq = - MHU_AP_NONSEC_LP_IRQ, - .recv = - SCP_MHU_SCP_AP_RCV_NS_CLUS0, - .send = - SCP_MHU_SCP_AP_SND_NS_CLUS0, - .channel = 1, - }) }, - [SCP_TC0_MHU_DEVICE_IDX_COUNT] = { 0 }, -}; - -static const struct fwk_element *mhu_get_element_table(fwk_id_t module_id) -{ - return mhu_element_table; -} - -const struct fwk_module_config config_mhu2 = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(mhu_get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_mock_psu.c b/product/tc0/scp_ramfw/config_mock_psu.c deleted file mode 100644 index 1aa264e3ed68..000000000000 --- a/product/tc0/scp_ramfw/config_mock_psu.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <tc0_mock_psu.h> - -#include <mod_mock_psu.h> - -#include <fwk_element.h> -#include <fwk_module.h> - -static const struct fwk_element element_table[] = { - [MOCK_PSU_ELEMENT_IDX_KLEIN] = { - .name = "DVFS_GROUP_KLEIN", - .data = - &(const struct mod_mock_psu_element_cfg){ - .async_alarm_id = FWK_ID_NONE_INIT, - .async_alarm_api_id = FWK_ID_NONE_INIT, - - .async_response_id = FWK_ID_NONE_INIT, - .async_response_api_id = FWK_ID_NONE_INIT, - - .default_enabled = true, - .default_voltage = 550, - }, - }, - [MOCK_PSU_ELEMENT_IDX_MATTERHORN] = { - .name = "DVFS_GROUP_MATTERHORN", - .data = - &(const struct mod_mock_psu_element_cfg){ - .async_alarm_id = FWK_ID_NONE_INIT, - .async_alarm_api_id = FWK_ID_NONE_INIT, - - .async_response_id = FWK_ID_NONE_INIT, - .async_response_api_id = FWK_ID_NONE_INIT, - - .default_enabled = true, - .default_voltage = 550, - }, - }, - [MOCK_PSU_ELEMENT_IDX_MATTERHORN_ELP_ARM] = { - .name = "DVFS_GROUP_MATTERHORN_ELP_ARM", - .data = - &(const struct mod_mock_psu_element_cfg){ - .async_alarm_id = FWK_ID_NONE_INIT, - .async_alarm_api_id = FWK_ID_NONE_INIT, - - .async_response_id = FWK_ID_NONE_INIT, - .async_response_api_id = FWK_ID_NONE_INIT, - - .default_enabled = true, - .default_voltage = 550, - }, - }, - { 0 } -}; - -static const struct fwk_element *get_element_table(fwk_id_t module_id) -{ - return element_table; -} - -const struct fwk_module_config config_mock_psu = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_mock_voltage_domain.c b/product/tc0/scp_ramfw/config_mock_voltage_domain.c deleted file mode 100644 index ea3891d72034..000000000000 --- a/product/tc0/scp_ramfw/config_mock_voltage_domain.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include <config_mock_voltage_domain.h> - -#include <mod_mock_voltage_domain.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_module.h> - -#include <stdbool.h> -#include <stddef.h> - -static const int32_t dummy_discrete_voltage_values[] = { - -500000, - 800000, - 10000, -}; - -static const struct fwk_element element_table[] = { - [CONFIG_MOCK_VOLTAGE_DOMAIN_ELEMENT_IDX_DUMMY] = { - .name = "DUMMY_VOLTD", - .data = &(const struct mod_mock_voltage_domain_element_cfg) { - .async_alarm_id = FWK_ID_NONE_INIT, - .async_alarm_api_id = FWK_ID_NONE_INIT, - - .async_response_id = FWK_ID_NONE_INIT, - .async_response_api_id = FWK_ID_NONE_INIT, - - .default_mode_id = MOD_VOLTD_MODE_ID_OFF, - .default_voltage = 500000, - - .level_type = MOD_VOLTD_VOLTAGE_LEVEL_CONTINUOUS, - .level_count = FWK_ARRAY_SIZE(dummy_discrete_voltage_values), - .voltage_levels = dummy_discrete_voltage_values, - }, - }, - { 0 } -}; - -static const struct fwk_element *get_element_table(fwk_id_t module_id) -{ - return element_table; -} - -struct fwk_module_config config_mock_voltage_domain = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_mock_voltage_domain.h b/product/tc0/scp_ramfw/config_mock_voltage_domain.h deleted file mode 100644 index 6c13368279a6..000000000000 --- a/product/tc0/scp_ramfw/config_mock_voltage_domain.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CONFIG_MOCK_VOLTAGE_DOMAIN_H -#define CONFIG_MOCK_VOLTAGE_DOMAIN_H - -enum config_mock_voltage_domain_element_idx { - CONFIG_MOCK_VOLTAGE_DOMAIN_ELEMENT_IDX_DUMMY, - - CONFIG_MOCK_VOLTAGE_DOMAIN_ELEMENT_IDX_COUNT, -}; - -#endif /* CONFIG_MOCK_VOLTAGE_DOMAIN_H */ diff --git a/product/tc0/scp_ramfw/config_mpmm.c b/product/tc0/scp_ramfw/config_mpmm.c deleted file mode 100644 index 3bfe99d39183..000000000000 --- a/product/tc0/scp_ramfw/config_mpmm.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "scp_css_mmap.h" -#include "tc0_core.h" -#include "tc0_dvfs.h" -#include "tc0_timer.h" - -#include <mod_mpmm.h> - -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -enum core_pd_idx { - CORE0_IDX, - CORE1_IDX, - CORE2_IDX, - CORE3_IDX, - CORE4_IDX, - CORE5_IDX, - CORE6_IDX, - CORE7_IDX -}; - -#if defined(PLATFORM_VARIANT) && (PLATFORM_VARIANT == TC0_VARIANT_STD) -static struct mod_mpmm_pct_table k_pct[] = { - { .cores_online = 4, - .default_perf_limit = 1153 * 1000000UL, - .num_perf_limits = 3, - .threshold_perf = { { - .threshold_bitmap = 0x2222, - .perf_limit = 1153 * 1000000UL, - }, - { - .threshold_bitmap = 0x2211, - .perf_limit = 1537 * 1000000UL, - }, - { - .threshold_bitmap = 0x1111, - .perf_limit = 1844 * 1000000UL, - }, - } }, - { .cores_online = 3, - .default_perf_limit = 1844 * 1000000UL, - .num_perf_limits = 2, - .threshold_perf = { { - .threshold_bitmap = 0x222, - .perf_limit = 1844 * 1000000UL, - }, - { - .threshold_bitmap = 0x111, - .perf_limit = 2152 * 1000000UL, - }, - } }, - { .cores_online = 2, - .default_perf_limit = 2152 * 1000000UL, - .num_perf_limits = 1, - .threshold_perf = { { - .threshold_bitmap = 0x22, - .perf_limit = 2152 * 1000000UL, - }, - } }, - - { .cores_online = 1, - .default_perf_limit = 2152 * 1000000UL, - .num_perf_limits = 1, - .threshold_perf = { { - .threshold_bitmap = 0x2, - .perf_limit = 2152 * 1000000UL, - }, - } }, - -}; - -static struct mod_mpmm_pct_table m_pct[] = { - { .cores_online = 3, - .default_perf_limit = 1419 * 1000000UL, - .num_perf_limits = 3, - .threshold_perf = { { - .threshold_bitmap = 0x222, - .perf_limit = 1419 * 1000000UL, - }, - { - .threshold_bitmap = 0x211, - .perf_limit = 1893 * 1000000UL, - }, - { - .threshold_bitmap = 0x110, - .perf_limit = 2271 * 1000000UL, - }, - } }, - { .cores_online = 2, - .default_perf_limit = 2271 * 1000000UL, - .num_perf_limits = 2, - .threshold_perf = { { - .threshold_bitmap = 0x22, - .perf_limit = 2271 * 1000000UL, - }, - { - .threshold_bitmap = 0x11, - .perf_limit = 2650 * 1000000UL, - }, - } }, - { .cores_online = 1, - .default_perf_limit = 2650 * 1000000UL, - .num_perf_limits = 1, - .threshold_perf = { { - .threshold_bitmap = 0x2, - .perf_limit = 2650 * 1000000UL, - }, - } }, -}; -#endif - -static struct mod_mpmm_pct_table m_elp_pct[] = { - { .cores_online = 1, - .default_perf_limit = 2612 * 1000000UL, - .num_perf_limits = 2, - .threshold_perf = { { - .threshold_bitmap = 0x2, - .perf_limit = 2612 * 1000000UL, - }, - { - .threshold_bitmap = 0x1, - .perf_limit = 3047 * 1000000UL, - }, - } }, -}; - -#if defined(PLATFORM_VARIANT) && (PLATFORM_VARIANT == TC0_VARIANT_STD) -static const struct mod_mpmm_core_config k_core_config[] = { - [0] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE0_IDX), - .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE0_IDX), - .amu_aux_reg_base = SCP_AMU_AMEVCNTR1X(CORE0_IDX), - .core_starts_online = true, - }, - [1] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE1_IDX), - .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE1_IDX), - .amu_aux_reg_base = SCP_AMU_AMEVCNTR1X(CORE1_IDX), - .core_starts_online = false, - }, - [2] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE2_IDX), - .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE2_IDX), - .amu_aux_reg_base = SCP_AMU_AMEVCNTR1X(CORE2_IDX), - .core_starts_online = false, - }, - [3] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE3_IDX), - .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE3_IDX), - .amu_aux_reg_base = SCP_AMU_AMEVCNTR1X(CORE3_IDX), - .core_starts_online = false, - }, -}; - -static const struct mod_mpmm_core_config m_core_config[] = { - [0] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE4_IDX), - .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE4_IDX), - .amu_aux_reg_base = SCP_AMU_AMEVCNTR1X(CORE4_IDX), - .core_starts_online = false, - }, - [1] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE5_IDX), - .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE5_IDX), - .amu_aux_reg_base = SCP_AMU_AMEVCNTR1X(CORE5_IDX), - .core_starts_online = false, - }, - [2] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE6_IDX), - .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE6_IDX), - .amu_aux_reg_base = SCP_AMU_AMEVCNTR1X(CORE6_IDX), - .core_starts_online = false, - }, -}; -#endif - -static const struct mod_mpmm_core_config m_elp_core_config[] = { - [0] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE7_IDX), - .mpmm_reg_base = SCP_MPMM_CORE_BASE(CORE7_IDX), - .amu_aux_reg_base = SCP_AMU_AMEVCNTR1X(CORE7_IDX), - .core_starts_online = false, - }, -}; - -#if defined(PLATFORM_VARIANT) && (PLATFORM_VARIANT == TC0_VARIANT_STD) -static const struct mod_mpmm_domain_config k_domain_conf[] = { - [0] = { - .perf_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, - DVFS_ELEMENT_IDX_KLEIN), - .pct = k_pct, - .pct_size = FWK_ARRAY_SIZE(k_pct), - .btc = 10, - .num_threshold_counters = 3, - .core_config = k_core_config, - }, - [1] = {0}, -}; - -static const struct mod_mpmm_domain_config m_domain_conf[] = { - [0] = { - .perf_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, - DVFS_ELEMENT_IDX_MATTERHORN), - .pct = m_pct, - .pct_size = FWK_ARRAY_SIZE(m_pct), - .btc = 10, - .num_threshold_counters = 3, - .core_config = m_core_config, - }, - [1] = {0}, -}; -#endif - -static const struct mod_mpmm_domain_config m_elp_domain_conf[] = { - [0] = { - .perf_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, - DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM), - .pct = m_elp_pct, - .pct_size = FWK_ARRAY_SIZE(m_elp_pct), - .btc = 10, - .num_threshold_counters = 3, - .core_config = m_elp_core_config, - }, - [1] = {0}, -}; - -static const struct fwk_element element_table[] = { -#if defined(PLATFORM_VARIANT) && (PLATFORM_VARIANT == TC0_VAR_EXPERIMENT_POWER) - [0] = { - .name = "MPMM_MATTERHORN_ELP_ARM_ELEM", - .sub_element_count = 1, - .data = m_elp_domain_conf, - }, - [1] = { 0 }, -#else - [0] = { - .name = "MPMM_KLEIN_ELEM", - .sub_element_count = 4, - .data = k_domain_conf, - }, - [1] = { - .name = "MPMM_MATTERHORN_ELEM", - .sub_element_count = 3, - .data = m_domain_conf, - }, - [2] = { - .name = "MPMM_MATTERHORN_ELP_ARM_ELEM", - .sub_element_count = 1, - .data = m_elp_domain_conf, - }, - [3] = { 0 }, -#endif -}; - -static const struct fwk_element *mpmm_get_element_table(fwk_id_t module_id) -{ - return element_table; -} -const struct fwk_module_config config_mpmm = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(mpmm_get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_pik_clock.c b/product/tc0/scp_ramfw/config_pik_clock.c deleted file mode 100644 index fc5c0d01cc18..000000000000 --- a/product/tc0/scp_ramfw/config_pik_clock.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "cpu_pik.h" -#include "dpu_pik.h" -#include "scp_pik.h" -#include "system_pik.h" - -#include <mod_pik_clock.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> - -/* - * Rate lookup tables - */ -static struct mod_pik_clock_rate rate_table_cpu_group_klein[] = { - { - .rate = 1537 * FWK_MHZ, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .divider = 1, /* Rate adjusted via CPU PLL */ - }, -}; - -static struct mod_pik_clock_rate rate_table_cpu_group_matterhorn[] = { - { - .rate = 1893 * FWK_MHZ, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .divider = 1, /* Rate adjusted via CPU PLL */ - }, -}; - -static struct mod_pik_clock_rate rate_table_cpu_group_matterhorn_elp_arm[] = { - { - .rate = 2176 * FWK_MHZ, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL2, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .divider = 1, /* Rate adjusted via CPU PLL */ - }, -}; - -static const struct mod_pik_clock_rate rate_table_gicclk[] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static const struct mod_pik_clock_rate rate_table_pclkscp[] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static const struct mod_pik_clock_rate rate_table_sysperclk[] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static const struct mod_pik_clock_rate rate_table_uartclk[] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static struct mod_pik_clock_rate rate_table_dpu[] = { - { - .rate = 600 * FWK_MHZ, - .source = MOD_PIK_CLOCK_ACLKDPU_SOURCE_DISPLAYPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .divider = 1, /* Rate adjusted via display PLL */ - }, -}; - -static const struct fwk_element pik_clock_element_table[] = { - - [CLOCK_PIK_IDX_CLUS0_CPU0] = { - .name = "CLUS0_CPU0", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU1] = { - .name = "CLUS0_CPU1", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU2] = { - .name = "CLUS0_CPU2", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU3] = { - .name = "CLUS0_CPU3", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU4] = { - .name = "CLUS0_CPU4", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[4].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[4].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[4].MOD, - .rate_table = rate_table_cpu_group_matterhorn, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_matterhorn), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU5] = { - .name = "CLUS0_CPU5", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[5].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[5].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[5].MOD, - .rate_table = rate_table_cpu_group_matterhorn, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_matterhorn), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU6] = { - .name = "CLUS0_CPU6", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[6].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[6].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[6].MOD, - .rate_table = rate_table_cpu_group_matterhorn, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_matterhorn), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU7] = { - .name = "CLUS0_CPU7", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[7].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[7].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[7].MOD, - .rate_table = rate_table_cpu_group_matterhorn_elp_arm, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_matterhorn_elp_arm), - }), - }, - [CLOCK_PIK_IDX_GIC] = { - .name = "GIC", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->GICCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->GICCLK_DIV1, - .rate_table = rate_table_gicclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_gicclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_PCLKSCP] = { - .name = "PCLKSCP", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->PCLKSCP_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->PCLKSCP_DIV1, - .rate_table = rate_table_pclkscp, - .rate_count = FWK_ARRAY_SIZE(rate_table_pclkscp), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_SYSPERCLK] = { - .name = "SYSPERCLK", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->SYSPERCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->SYSPERCLK_DIV1, - .rate_table = rate_table_sysperclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_sysperclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_UARTCLK] = { - .name = "UARTCLK", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->UARTCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->UARTCLK_DIV1, - .rate_table = rate_table_uartclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_uartclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_DPU] = { - .name = "DPU", - .data = &((struct mod_pik_clock_dev_config) { - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = true, - .control_reg = &DPU_PIK_PTR->ACLKDP_CTRL, - .divsys_reg = &DPU_PIK_PTR->ACLKDP_DIV1, - .divext_reg = &DPU_PIK_PTR->ACLKDP_DIV2, - .rate_table = rate_table_dpu, - .rate_count = FWK_ARRAY_SIZE(rate_table_dpu), - .initial_rate = 600 * FWK_MHZ, - .defer_initialization = true, - }), - }, - [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ -}; - -static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id) -{ - return pik_clock_element_table; -} - -const struct fwk_module_config config_pik_clock = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(pik_clock_get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_pl011.c b/product/tc0/scp_ramfw/config_pl011.c deleted file mode 100644 index e82f79767a04..000000000000 --- a/product/tc0/scp_ramfw/config_pl011.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "config_power_domain.h" -#include "scp_css_mmap.h" - -#include <mod_pl011.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> - -const struct fwk_module_config config_pl011 = { - .elements = FWK_MODULE_STATIC_ELEMENTS({ - [0] = { - .name = "uart", - .data = - &(struct mod_pl011_element_cfg){ - .reg_base = SCP_UART_BOARD_BASE, - .baud_rate_bps = 115200, - .clock_rate_hz = 24 * FWK_MHZ, - .clock_id = FWK_ID_NONE_INIT, - .pd_id = FWK_ID_NONE_INIT, - }, - }, - - [1] = { 0 }, - }), -}; diff --git a/product/tc0/scp_ramfw/config_power_domain.c b/product/tc0/scp_ramfw/config_power_domain.c deleted file mode 100644 index e7867fe81b5e..000000000000 --- a/product/tc0/scp_ramfw/config_power_domain.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "config_power_domain.h" -#include "tc0_core.h" -#include "tc0_power_domain.h" - -#include <power_domain_utils.h> - -#include <mod_power_domain.h> -#include <mod_ppu_v1.h> -#include <mod_system_power.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_mm.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <stdint.h> -#include <stdio.h> -#include <string.h> - -/* Maximum power domain name size including the null terminator */ -#define PD_NAME_SIZE 12 - -/* Mask of the allowed states for the systop power domain */ -static const uint32_t systop_allowed_state_mask_table[] = { - [0] = MOD_PD_STATE_ON_MASK -}; - -/* - * Mask of the allowed states for the cluster power domain depending on the - * system states. - */ -static const uint32_t cluster_pd_allowed_state_mask_table[] = { - [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK, - [MOD_PD_STATE_ON] = TC0_CLUSTER_VALID_STATE_MASK, -}; - -/* Mask of the allowed states for a core depending on the cluster states. */ -static const uint32_t core_pd_allowed_state_mask_table[] = { - [MOD_PD_STATE_OFF] = MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_SLEEP_MASK, - [MOD_PD_STATE_ON] = TC0_CORE_VALID_STATE_MASK, -}; - -/* Power module specific configuration data (none) */ -static const struct mod_power_domain_config tc0_power_domain_config = { 0 }; - -static struct fwk_element tc0_power_domain_static_element_table[] = { - [PD_STATIC_DEV_IDX_SYSTOP] = - { - .name = "SYSTOP", - .data = &((struct mod_power_domain_element_config){ - .attributes.pd_type = MOD_PD_TYPE_SYSTEM, - .parent_idx = PD_STATIC_DEV_IDX_NONE, - .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SYSTEM_POWER), - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_POWER, - MOD_SYSTEM_POWER_API_IDX_PD_DRIVER), - .allowed_state_mask_table = systop_allowed_state_mask_table, - .allowed_state_mask_table_size = - FWK_ARRAY_SIZE(systop_allowed_state_mask_table) }), - }, -}; - -/* - * Function definitions with internal linkage - */ -static const struct fwk_element *tc0_power_domain_get_element_table( - fwk_id_t module_id) -{ - return create_power_domain_element_table( - tc0_core_get_core_count(), - tc0_core_get_cluster_count(), - FWK_MODULE_IDX_PPU_V1, - MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER, - core_pd_allowed_state_mask_table, - FWK_ARRAY_SIZE(core_pd_allowed_state_mask_table), - cluster_pd_allowed_state_mask_table, - FWK_ARRAY_SIZE(cluster_pd_allowed_state_mask_table), - tc0_power_domain_static_element_table, - FWK_ARRAY_SIZE(tc0_power_domain_static_element_table)); -} - -/* - * Power module configuration data - */ -const struct fwk_module_config config_power_domain = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(tc0_power_domain_get_element_table), - .data = &tc0_power_domain_config, -}; diff --git a/product/tc0/scp_ramfw/config_ppu_v1.c b/product/tc0/scp_ramfw/config_ppu_v1.c deleted file mode 100644 index 65a07b92a112..000000000000 --- a/product/tc0/scp_ramfw/config_ppu_v1.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "config_power_domain.h" -#include "scp_css_mmap.h" -#include "tc0_core.h" - -#include <mod_power_domain.h> -#include <mod_ppu_v1.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_interrupt.h> -#include <fwk_macros.h> -#include <fwk_mm.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <stdio.h> -#include <string.h> - -/* Maximum PPU core name size including the null terminator */ -#define PPU_CORE_NAME_SIZE 12 - -/* Maximum PPU cluster name size including the null terminator */ -#define PPU_CLUS_NAME_SIZE 6 - -/* Cluster ID for Theodul DSU */ -#define CLUSTER_ID 0 - -/* Module configuration data */ -static struct mod_ppu_v1_config ppu_v1_config_data = { - .pd_notification_id = FWK_ID_NOTIFICATION_INIT( - FWK_MODULE_IDX_POWER_DOMAIN, - MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION), -}; - -static struct fwk_element ppu_v1_system_element_table[] = { - [0] = - { - .name = "SYS0", - .data = &((struct mod_ppu_v1_pd_config){ - .pd_type = MOD_PD_TYPE_SYSTEM, - .ppu.reg_base = SCP_PPU_SYS0_BASE, - .observer_id = FWK_ID_NONE_INIT, - }), - }, - [1] = - { - .name = "SYS1", - .data = &((struct mod_ppu_v1_pd_config){ - .pd_type = MOD_PD_TYPE_SYSTEM, - .ppu.reg_base = SCP_PPU_SYS1_BASE, - .observer_id = FWK_ID_NONE_INIT, - }), - }, -}; - -static const struct fwk_element *ppu_v1_get_element_table(fwk_id_t module_id) -{ - struct fwk_element *element_table, *element; - struct mod_ppu_v1_pd_config *pd_config_table, *pd_config; - unsigned int core_idx; - unsigned int core_count; - unsigned int cluster_count; - unsigned int core_element_count = 0; - - core_count = tc0_core_get_core_count(); - cluster_count = tc0_core_get_cluster_count(); - - /* - * Allocate element descriptors based on: - * Number of cores - * + Number of cluster descriptors - * + Number of system power domain descriptors - * + 1 terminator descriptor - */ - element_table = fwk_mm_calloc( - core_count + cluster_count + - FWK_ARRAY_SIZE(ppu_v1_system_element_table) + 1, - sizeof(struct fwk_element)); - if (element_table == NULL) { - return NULL; - } - - pd_config_table = fwk_mm_calloc( - core_count + cluster_count, sizeof(struct mod_ppu_v1_pd_config)); - if (pd_config_table == NULL) { - return NULL; - } - - for (core_idx = 0; - core_idx < tc0_core_get_core_per_cluster_count(CLUSTER_ID); - core_idx++) { - element = &element_table[core_element_count]; - pd_config = &pd_config_table[core_element_count]; - - element->name = fwk_mm_alloc(PPU_CORE_NAME_SIZE, 1); - if (element->name == NULL) { - return NULL; - } - - snprintf((char *)element->name, PPU_CORE_NAME_SIZE, "CORE%u", core_idx); - - element->data = pd_config; - - pd_config->pd_type = MOD_PD_TYPE_CORE; - pd_config->ppu.reg_base = SCP_PPU_CORE_BASE(core_idx); - pd_config->ppu.irq = FWK_INTERRUPT_NONE; - pd_config->cluster_id = - FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, core_count); - pd_config->observer_id = FWK_ID_NONE; - core_element_count++; - } - - element = &element_table[core_count]; - pd_config = &pd_config_table[core_count]; - - element->name = fwk_mm_alloc(PPU_CLUS_NAME_SIZE, 1); - if (element->name == NULL) { - return NULL; - } - - element->data = pd_config; - - pd_config->pd_type = MOD_PD_TYPE_CLUSTER; - pd_config->ppu.reg_base = SCP_PPU_CLUSTER_BASE; - pd_config->ppu.irq = FWK_INTERRUPT_NONE; - pd_config->observer_id = FWK_ID_NONE; - - memcpy( - &element_table[core_count + cluster_count], - ppu_v1_system_element_table, - sizeof(ppu_v1_system_element_table)); - - /* - * Configure pd_source_id with the SYSTOP identifier from the power domain - * module which is dynamically defined based on the number of cores. - */ - ppu_v1_config_data.pd_source_id = fwk_id_build_element_id( - fwk_module_id_power_domain, - core_count + cluster_count + PD_STATIC_DEV_IDX_SYSTOP); - - return element_table; -} - -/* - * Power module configuration data - */ -const struct fwk_module_config config_ppu_v1 = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(ppu_v1_get_element_table), - .data = &ppu_v1_config_data, -}; diff --git a/product/tc0/scp_ramfw/config_psu.c b/product/tc0/scp_ramfw/config_psu.c deleted file mode 100644 index 96514d095a1f..000000000000 --- a/product/tc0/scp_ramfw/config_psu.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <tc0_mock_psu.h> -#include <tc0_psu.h> - -#include <mod_mock_psu.h> -#include <mod_psu.h> - -#include <fwk_element.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -static const struct fwk_element element_table[] = { - [PSU_ELEMENT_IDX_KLEIN] = { - .name = "DVFS_GROUP_KLEIN", - .data = - &(const struct mod_psu_element_cfg){ - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, MOCK_PSU_ELEMENT_IDX_KLEIN), - .driver_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_MOCK_PSU, - MOD_MOCK_PSU_API_IDX_DRIVER) }, - }, - [PSU_ELEMENT_IDX_MATTERHORN] = { - .name = "DVFS_GROUP_MATTERHORN", - .data = - &(const struct mod_psu_element_cfg){ - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, MOCK_PSU_ELEMENT_IDX_MATTERHORN), - .driver_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_MOCK_PSU, - MOD_MOCK_PSU_API_IDX_DRIVER) }, - }, - [PSU_ELEMENT_IDX_MATTERHORN_ELP_ARM] = { - .name = "DVFS_GROUP_MATTERHORN_ELP_ARM", - .data = - &(const struct mod_psu_element_cfg){ - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, MOCK_PSU_ELEMENT_IDX_MATTERHORN_ELP_ARM), - .driver_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_MOCK_PSU, - MOD_MOCK_PSU_API_IDX_DRIVER) }, - }, - - { 0 } -}; - -static const struct fwk_element *psu_get_element_table(fwk_id_t module_id) -{ - return element_table; -} - -const struct fwk_module_config config_psu = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(psu_get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_reg_sensor.c b/product/tc0/scp_ramfw/config_reg_sensor.c deleted file mode 100644 index 74b23942f87a..000000000000 --- a/product/tc0/scp_ramfw/config_reg_sensor.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <mod_reg_sensor.h> -#include <mod_sensor.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_module.h> - -#include <stddef.h> -#include <stdint.h> - -static uint64_t fake_sensor_register = UINT64_C(0x0); - -/* - * Register Sensor driver config - */ -static struct mod_sensor_info info_fake_temperature = { - .type = MOD_SENSOR_TYPE_DEGREES_C, - .update_interval = 0, - .update_interval_multiplier = 0, - .unit_multiplier = 0, -}; - -static const struct fwk_element reg_sensor_element_table[] = { - [0] = { - .name = "TC0 Fake Temperature Sensor Register", - .data = &((struct mod_reg_sensor_dev_config) { - .reg = (uintptr_t)(&fake_sensor_register), - .info = &info_fake_temperature, - }), - }, - - [1] = { 0 }, /* Termination description */ -}; - -static const struct fwk_element *get_reg_sensor_element_table(fwk_id_t id) -{ - return reg_sensor_element_table; -} - -struct fwk_module_config config_reg_sensor = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_reg_sensor_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_resource_perms.c b/product/tc0/scp_ramfw/config_resource_perms.c deleted file mode 100644 index 08f5107b6588..000000000000 --- a/product/tc0/scp_ramfw/config_resource_perms.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "tc0_scmi.h" - -#include <mod_resource_perms.h> -#include <mod_scmi_std.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -/*! - * If the agent wants to modify permissions at run-time these tables - * must be allocated in writable memory. - */ - -#define AGENT_IDX(agent_id) (agent_id - 1) - -static struct mod_res_agent_protocol_permissions agent_protocol_permissions[] = - { - [AGENT_IDX(SCP_SCMI_AGENT_ID_OSPM)] = - { - .protocols = MOD_RES_PERMS_SCMI_ALL_PROTOCOLS_ALLOWED, - }, - - /* PSCI agent has no access to clock, perf and sensor protocol */ - [AGENT_IDX(SCP_SCMI_AGENT_ID_PSCI)] = - { - .protocols = MOD_RES_PERMS_SCMI_CLOCK_PROTOCOL_DENIED | - MOD_RES_PERMS_SCMI_PERF_PROTOCOL_DENIED | - MOD_RES_PERMS_SCMI_SENSOR_PROTOCOL_DENIED | - MOD_RES_PERMS_SCMI_VOLTAGE_DOMAIN_PROTOCOL_DENIED, - }, - }; - -/* - * Messages have an index offset from 0x3 as all agents can access - * the VERSION/ATTRIBUTES/MSG_ATTRIBUTES messages for all - * protocols, hence message 0x3 maps to bit[0], message 0x4 maps - * to bit[1], etc. - */ -static struct mod_res_agent_msg_permissions - agent_msg_permissions[] = - { - [AGENT_IDX(SCP_SCMI_AGENT_ID_OSPM)] = - { - .messages = { - [MOD_RES_PERMS_SCMI_BASE_MESSAGE_IDX] = 0x0, - [MOD_RES_PERMS_SCMI_POWER_DOMAIN_MESSAGE_IDX] = - 0x0, - [MOD_RES_PERMS_SCMI_SYS_POWER_MESSAGE_IDX] = 0x0, - [MOD_RES_PERMS_SCMI_PERF_MESSAGE_IDX] = 0x0, - [MOD_RES_PERMS_SCMI_CLOCK_MESSAGE_IDX] = 0x0, - [MOD_RES_PERMS_SCMI_SENSOR_MESSAGE_IDX] = 0x0, - [MOD_RES_PERMS_SCMI_RESET_DOMAIN_MESSAGE_IDX] = - 0x0, - [MOD_RES_PERMS_SCMI_VOLTAGE_DOMAIN_MESSAGE_IDX] = - 0x0, - }, - }, - [AGENT_IDX(SCP_SCMI_AGENT_ID_PSCI)] = - { - .messages = { - [MOD_RES_PERMS_SCMI_BASE_MESSAGE_IDX] = 0x0, - [MOD_RES_PERMS_SCMI_POWER_DOMAIN_MESSAGE_IDX] = - 0x0, - [MOD_RES_PERMS_SCMI_SYS_POWER_MESSAGE_IDX] = 0x0, - [MOD_RES_PERMS_SCMI_PERF_MESSAGE_IDX] = - ((1 - << (MOD_SCMI_PERF_DOMAIN_ATTRIBUTES - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - /* DESCRIBE_LEVELS is required for some reason */ - (0 - << (MOD_SCMI_PERF_DESCRIBE_LEVELS - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 - << (MOD_SCMI_PERF_LIMITS_SET - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 - << (MOD_SCMI_PERF_LIMITS_GET - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 - << (MOD_SCMI_PERF_LEVEL_SET - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 - << (MOD_SCMI_PERF_LEVEL_GET - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 - << (MOD_SCMI_PERF_NOTIFY_LIMITS - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 - << (MOD_SCMI_PERF_NOTIFY_LEVEL - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES)) | - (1 - << (MOD_SCMI_PERF_DESCRIBE_FAST_CHANNEL - - MOD_SCMI_PERF_DOMAIN_ATTRIBUTES))), - /* Clocks, no access */ - [MOD_RES_PERMS_SCMI_CLOCK_MESSAGE_IDX] = 0xff, - [MOD_RES_PERMS_SCMI_SENSOR_MESSAGE_IDX] = 0x0, - [MOD_RES_PERMS_SCMI_RESET_DOMAIN_MESSAGE_IDX] = - 0x0, - [MOD_RES_PERMS_SCMI_VOLTAGE_DOMAIN_MESSAGE_IDX] = - 0x0, - }, - }, - }; - -static struct mod_res_agent_permission agent_permissions = { - .agent_protocol_permissions = agent_protocol_permissions, - .agent_msg_permissions = agent_msg_permissions, -}; - -struct fwk_module_config config_resource_perms = { - .data = - &(struct mod_res_resource_perms_config){ - .agent_permissions = (uintptr_t)&agent_permissions, - .agent_count = SCP_SCMI_AGENT_ID_COUNT, - .protocol_count = 8, - }, -}; diff --git a/product/tc0/scp_ramfw/config_scmi.c b/product/tc0/scp_ramfw/config_scmi.c deleted file mode 100644 index 442d090975e3..000000000000 --- a/product/tc0/scp_ramfw/config_scmi.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "tc0_scmi.h" - -#include <mod_scmi.h> -#include <mod_transport.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -static const struct fwk_element service_table[] = { - [SCP_TC0_SCMI_SERVICE_IDX_PSCI] = { - .name = "PSCI", - .data = &((struct mod_scmi_service_config) { - .transport_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_TRANSPORT, - SCP_TC0_SCMI_SERVICE_IDX_PSCI), - .transport_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_TRANSPORT, - MOD_TRANSPORT_API_IDX_SCMI_TO_TRANSPORT), - .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( - FWK_MODULE_IDX_TRANSPORT, - MOD_TRANSPORT_NOTIFICATION_IDX_INITIALIZED), - .scmi_agent_id = SCP_SCMI_AGENT_ID_PSCI, - .scmi_p2a_id = FWK_ID_NONE_INIT, - }), - }, - [SCP_TC0_SCMI_SERVICE_IDX_OSPM_0] = { - .name = "OSPM0", - .data = &((struct mod_scmi_service_config) { - .transport_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_TRANSPORT, - SCP_TC0_SCMI_SERVICE_IDX_OSPM_0), - .transport_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_TRANSPORT, - MOD_TRANSPORT_API_IDX_SCMI_TO_TRANSPORT), - .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( - FWK_MODULE_IDX_TRANSPORT, - MOD_TRANSPORT_NOTIFICATION_IDX_INITIALIZED), - .scmi_agent_id = SCP_SCMI_AGENT_ID_OSPM, - }), - }, - [SCP_TC0_SCMI_SERVICE_IDX_OSPM_1] = { - .name = "OSPM1", - .data = &((struct mod_scmi_service_config) { - .transport_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_TRANSPORT, - SCP_TC0_SCMI_SERVICE_IDX_OSPM_1), - .transport_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_TRANSPORT, - MOD_TRANSPORT_API_IDX_SCMI_TO_TRANSPORT), - .transport_notification_init_id = FWK_ID_NOTIFICATION_INIT( - FWK_MODULE_IDX_TRANSPORT, - MOD_TRANSPORT_NOTIFICATION_IDX_INITIALIZED), - .scmi_agent_id = SCP_SCMI_AGENT_ID_OSPM, - .scmi_p2a_id = FWK_ID_NONE_INIT, - }), - }, - [SCP_TC0_SCMI_SERVICE_IDX_COUNT] = { 0 } -}; - -static const struct fwk_element *get_service_table(fwk_id_t module_id) -{ - return service_table; -} - -#ifndef BUILD_HAS_MOD_RESOURCE_PERMS - -/* PSCI agent has no access to clock, perf and sensor protocol */ -static const uint32_t dis_protocol_list_psci[] = { - MOD_SCMI_PROTOCOL_ID_SENSOR, - MOD_SCMI_PROTOCOL_ID_CLOCK, - MOD_SCMI_PROTOCOL_ID_PERF, - MOD_SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, -}; -#endif - -static struct mod_scmi_agent agent_table[] = { - [SCP_SCMI_AGENT_ID_OSPM] = { - .type = SCMI_AGENT_TYPE_OSPM, - .name = "OSPM", - }, - [SCP_SCMI_AGENT_ID_PSCI] = { - .type = SCMI_AGENT_TYPE_PSCI, - .name = "PSCI", - }, -}; - -const struct fwk_module_config config_scmi = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_service_table), - .data = &((struct mod_scmi_config){ - .protocol_count_max = 9, -#ifndef BUILD_HAS_MOD_RESOURCE_PERMS - .dis_protocol_count_psci = FWK_ARRAY_SIZE(dis_protocol_list_psci), - .dis_protocol_list_psci = dis_protocol_list_psci, -#endif - .agent_count = FWK_ARRAY_SIZE(agent_table) - 1, - .agent_table = agent_table, - .vendor_identifier = "arm", - .sub_vendor_identifier = "arm", - }), -}; diff --git a/product/tc0/scp_ramfw/config_scmi_clock.c b/product/tc0/scp_ramfw/config_scmi_clock.c deleted file mode 100644 index 792d2ec05013..000000000000 --- a/product/tc0/scp_ramfw/config_scmi_clock.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "tc0_scmi.h" - -#include <mod_scmi_clock.h> - -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -static const struct mod_scmi_clock_device agent_device_table_ospm[] = { - { - /* DPU */ - .element_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_DPU), - }, - { - /* PIXEL_0 */ - .element_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_PIXEL_0), - }, - { - /* PIXEL_1 */ - .element_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_PIXEL_1), - }, -}; - -static const struct mod_scmi_clock_agent agent_table[SCP_SCMI_AGENT_ID_COUNT] = - { - [SCP_SCMI_AGENT_ID_PSCI] = { 0 /* No access */ }, - [SCP_SCMI_AGENT_ID_OSPM] = - { - .device_table = agent_device_table_ospm, - .device_count = FWK_ARRAY_SIZE(agent_device_table_ospm), - }, - }; - -const struct fwk_module_config config_scmi_clock = { - .data = &((struct mod_scmi_clock_config){ - .max_pending_transactions = 0, - .agent_table = agent_table, - .agent_count = FWK_ARRAY_SIZE(agent_table), - }), -}; diff --git a/product/tc0/scp_ramfw/config_scmi_perf.c b/product/tc0/scp_ramfw/config_scmi_perf.c deleted file mode 100644 index 2bd235620363..000000000000 --- a/product/tc0/scp_ramfw/config_scmi_perf.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "tc0_dvfs.h" -#include "tc0_scmi.h" -#include "tc0_timer.h" - -#include <scp_mmap.h> -#include <scp_software_mmap.h> - -#include <mod_scmi_perf.h> - -#include <fwk_module.h> - -#include <stdint.h> - -#define FC_LEVEL_SET(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LEVEL_SET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) - -#define FC_LIMIT_SET(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LIMIT_SET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) - -#define FC_LEVEL_GET(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LEVEL_GET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) - -#define FC_LIMIT_GET(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LIMIT_GET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX)) - -#define FC_LEVEL_SET_AP(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LEVEL_SET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX) - \ - SCP_SYSTEM_ACCESS_PORT1_BASE) - -#define FC_LIMIT_SET_AP(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LIMIT_SET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX) - \ - SCP_SYSTEM_ACCESS_PORT1_BASE) - -#define FC_LEVEL_GET_AP(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LEVEL_GET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX) - \ - SCP_SYSTEM_ACCESS_PORT1_BASE) - -#define FC_LIMIT_GET_AP(PERF_IDX) \ - (SCMI_FAST_CHANNEL_BASE + MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_LIMIT_GET + \ - (MOD_SCMI_PERF_FAST_CHANNEL_OFFSET_TOTAL * PERF_IDX) - \ - SCP_SYSTEM_ACCESS_PORT1_BASE) - -static const struct mod_scmi_perf_domain_config domains[] = { - [DVFS_ELEMENT_IDX_KLEIN] = { -#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS - .fast_channels_addr_scp = (uint64_t[]) { - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET(DVFS_ELEMENT_IDX_KLEIN), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET(DVFS_ELEMENT_IDX_KLEIN), - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET(DVFS_ELEMENT_IDX_KLEIN), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET(DVFS_ELEMENT_IDX_KLEIN), - }, - .fast_channels_addr_ap = (uint64_t[]) { - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET_AP(DVFS_ELEMENT_IDX_KLEIN), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET_AP(DVFS_ELEMENT_IDX_KLEIN), - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET_AP(DVFS_ELEMENT_IDX_KLEIN), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET_AP(DVFS_ELEMENT_IDX_KLEIN), - }, -#endif - }, - [DVFS_ELEMENT_IDX_MATTERHORN] = { -#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS - .fast_channels_addr_scp = (uint64_t[]) { - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET(DVFS_ELEMENT_IDX_MATTERHORN), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET(DVFS_ELEMENT_IDX_MATTERHORN), - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET(DVFS_ELEMENT_IDX_MATTERHORN), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET(DVFS_ELEMENT_IDX_MATTERHORN), - }, - .fast_channels_addr_ap = (uint64_t[]) { - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET_AP(DVFS_ELEMENT_IDX_MATTERHORN), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET_AP(DVFS_ELEMENT_IDX_MATTERHORN), - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET_AP(DVFS_ELEMENT_IDX_MATTERHORN), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET_AP(DVFS_ELEMENT_IDX_MATTERHORN), - }, -#endif - }, - [DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM] = { -#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS - .fast_channels_addr_scp = (uint64_t[]) { - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET(DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET(DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM), - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET(DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET(DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM), - }, - .fast_channels_addr_ap = (uint64_t[]) { - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_SET] = - FC_LEVEL_SET_AP(DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_SET] = - FC_LIMIT_SET_AP(DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM), - [MOD_SCMI_PERF_FAST_CHANNEL_LEVEL_GET] = - FC_LEVEL_GET_AP(DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM), - [MOD_SCMI_PERF_FAST_CHANNEL_LIMIT_GET] = - FC_LIMIT_GET_AP(DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM), - }, -#endif - }, -}; - -#if defined(PLATFORM_VARIANT) && (PLATFORM_VARIANT == TC0_VAR_EXPERIMENT_POWER) -static const struct mod_scmi_plugin_config plugins_table[] = { - [0] = { - .id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_TRAFFIC_COP), - .dom_type = PERF_PLUGIN_DOM_TYPE_PHYSICAL, - }, - [1] = { - .id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_MPMM), - .dom_type = PERF_PLUGIN_DOM_TYPE_PHYSICAL, - }, - [2] = { - .id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_THERMAL_MGMT), - .dom_type = PERF_PLUGIN_DOM_TYPE_FULL, - }, -}; -#endif - -const struct fwk_module_config config_scmi_perf = { - .data = &((struct mod_scmi_perf_config) { - .domains = &domains, .perf_doms_count = FWK_ARRAY_SIZE(domains), -#ifdef BUILD_HAS_SCMI_PERF_FAST_CHANNELS - .fast_channels_alarm_id = FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_TIMER, 0, CONFIG_TIMER_FAST_CHANNEL_TIMER_IDX), - .fast_channels_rate_limit = (2 * 1000), -#else - .fast_channels_alarm_id = FWK_ID_NONE_INIT, -#endif -#if defined(PLATFORM_VARIANT) && (PLATFORM_VARIANT == TC0_VAR_EXPERIMENT_POWER) - .plugins = plugins_table, - .plugins_count = FWK_ARRAY_SIZE(plugins_table), -#endif - }) -}; diff --git a/product/tc0/scp_ramfw/config_scmi_power_domain.c b/product/tc0/scp_ramfw/config_scmi_power_domain.c deleted file mode 100644 index 29277afdf288..000000000000 --- a/product/tc0/scp_ramfw/config_scmi_power_domain.c +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <fwk_module.h> - -/* No elements, no module configuration data */ -struct fwk_module_config config_scmi_power_domain = { 0 }; diff --git a/product/tc0/scp_ramfw/config_scmi_system_power.c b/product/tc0/scp_ramfw/config_scmi_system_power.c deleted file mode 100644 index afa5675fcc37..000000000000 --- a/product/tc0/scp_ramfw/config_scmi_system_power.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <mod_scmi_system_power.h> -#include <mod_system_power.h> - -#include <fwk_module.h> - -const struct fwk_module_config config_scmi_system_power = { - .data = &((struct mod_scmi_system_power_config){ - .system_view = MOD_SCMI_SYSTEM_VIEW_FULL, - .system_suspend_state = MOD_SYSTEM_POWER_POWER_STATE_SLEEP0, - .alarm_id = FWK_ID_NONE_INIT }), - -}; diff --git a/product/tc0/scp_ramfw/config_scmi_voltage_domain.c b/product/tc0/scp_ramfw/config_scmi_voltage_domain.c deleted file mode 100644 index 92dfacaf5b77..000000000000 --- a/product/tc0/scp_ramfw/config_scmi_voltage_domain.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "tc0_scmi.h" - -#include <mod_scmi_voltage_domain.h> -#include <mod_voltage_domain.h> - -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <stddef.h> - -static struct mod_scmi_voltd_device scmi_voltd_device[] = { - { - .element_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_VOLTAGE_DOMAIN, 0), - .config = 0, - }, -}; - -static const struct mod_scmi_voltd_agent scmi_voltd_agent_table[SCP_SCMI_AGENT_ID_COUNT] = { - [SCP_SCMI_AGENT_ID_OSPM] = { - .device_table = scmi_voltd_device, - .domain_count = FWK_ARRAY_SIZE(scmi_voltd_device), - }, - [SCP_SCMI_AGENT_ID_PSCI] = { 0 /* No access */ }, -}; - -struct fwk_module_config config_scmi_voltage_domain = { - .data = &((struct mod_scmi_voltd_config){ - .agent_table = scmi_voltd_agent_table, - .agent_count = FWK_ARRAY_SIZE(scmi_voltd_agent_table), - }), -}; diff --git a/product/tc0/scp_ramfw/config_sds.c b/product/tc0/scp_ramfw/config_sds.c deleted file mode 100644 index 76459604a85a..000000000000 --- a/product/tc0/scp_ramfw/config_sds.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "scp_pik.h" -#include "scp_software_mmap.h" -#include "tc0_sds.h" - -#include <mod_sds.h> - -#include <fwk_assert.h> -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <stdbool.h> -#include <stdint.h> - -static const uint32_t feature_flags = TC0_SDS_FEATURE_FIRMWARE_MASK; - -static const struct mod_sds_region_desc sds_module_regions[] = { - [TC0_SDS_REGION_SECURE] = - { - .base = (void *)SCP_SDS_MEM_BASE, - .size = SCP_SDS_MEM_SIZE, - }, -}; - -static_assert( - FWK_ARRAY_SIZE(sds_module_regions) == TC0_SDS_REGION_COUNT, - "Mismatch between number of SDS regions and number of regions " - "provided by the SDS configuration."); - -const struct mod_sds_config sds_module_config = { - .regions = sds_module_regions, - .region_count = TC0_SDS_REGION_COUNT, - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_KLEIN) -}; - -static struct fwk_element sds_element_table[] = { - { - .name = "CPU Info", - .data = &((struct mod_sds_structure_desc){ - .id = TC0_SDS_CPU_INFO, - .size = TC0_SDS_CPU_INFO_SIZE, - .region_id = TC0_SDS_REGION_SECURE, - .finalize = true, - }), - }, - { - .name = "Feature Availability", - .data = &((struct mod_sds_structure_desc){ - .id = TC0_SDS_FEATURE_AVAILABILITY, - .size = TC0_SDS_FEATURE_AVAILABILITY_SIZE, - .payload = &feature_flags, - .region_id = TC0_SDS_REGION_SECURE, - .finalize = true, - }), - }, - { 0 }, /* Termination description. */ -}; - -static_assert( - SCP_SDS_MEM_SIZE > - TC0_SDS_CPU_INFO_SIZE + TC0_SDS_FEATURE_AVAILABILITY_SIZE, - "SDS structures too large for SDS SRAM.\n"); - -static const struct fwk_element *sds_get_element_table(fwk_id_t module_id) -{ - static_assert(BUILD_VERSION_MAJOR < UINT8_MAX, "Invalid version size"); - static_assert(BUILD_VERSION_MINOR < UINT8_MAX, "Invalid version size"); - static_assert(BUILD_VERSION_PATCH < UINT16_MAX, "Invalid version size"); - - return sds_element_table; -} - -struct fwk_module_config config_sds = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(sds_get_element_table), - .data = &sds_module_config, -}; diff --git a/product/tc0/scp_ramfw/config_sensor.c b/product/tc0/scp_ramfw/config_sensor.c deleted file mode 100644 index c59abd04065b..000000000000 --- a/product/tc0/scp_ramfw/config_sensor.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <mod_sensor.h> - -#include <fwk_assert.h> -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_mm.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> -#include <fwk_status.h> - -#include <string.h> - -/* - * When running on a model at least one fake sensor is required to in order to - * properly initialize the entire sensor support. - */ -static const struct fwk_element sensor_element_table_fvp[] = { - [0] = { - .name = "Fake sensor", - .data = &((struct mod_sensor_dev_config) { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_REG_SENSOR, 0), - .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_REG_SENSOR, 0), - }), - }, - - [1] = { 0 } /* Termination description */ -}; - -static const struct fwk_element *get_sensor_element_table(fwk_id_t module_id) -{ - return sensor_element_table_fvp; -} - -struct fwk_module_config config_sensor = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_sensor_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_system_pll.c b/product/tc0/scp_ramfw/config_system_pll.c deleted file mode 100644 index f94740730f05..000000000000 --- a/product/tc0/scp_ramfw/config_system_pll.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "scp_pik.h" -#include "scp_soc_mmap.h" - -#include <mod_system_pll.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> - -static const struct fwk_element system_pll_element_table[] = - { - [CLOCK_PLL_IDX_CPU_KLEIN] = - { - .name = "CPU_PLL_KLEIN", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_CPU_TYPE0, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], - .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0), - .initial_rate = 1537 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_CPU_MATTERHORN] = - { - .name = "CPU_PLL_MATTERHORN", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_CPU_TYPE1, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], - .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(1), - .initial_rate = 1893 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_CPU_MATTERHORN_ELP_ARM] = - { - .name = "CPU_PLL_MATTERHORN_ELP_ARM", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_CPU_TYPE2, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], - .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(2), - .initial_rate = 2176 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_SYS] = - { - .name = "SYS_PLL", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_SYSPLL, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], - .lock_flag_mask = PLL_STATUS_0_SYSPLLLOCK, - .initial_rate = 2000 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_DPU] = - { - .name = "DPU_PLL", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_DISPLAY, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], - .lock_flag_mask = PLL_STATUS_0_DISPLAYPLLLOCK, - .initial_rate = 600 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - .defer_initialization = false, - }), - }, - [CLOCK_PLL_IDX_PIX0] = - { - .name = "PIX0_PLL", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_PIX0, - .status_reg = NULL, - .initial_rate = 594 * FWK_MHZ, - .min_rate = 12500 * FWK_KHZ, - .max_rate = 594 * FWK_MHZ, - .min_step = 25 * FWK_KHZ, - .defer_initialization = false, - }), - }, - [CLOCK_PLL_IDX_PIX1] = - { - .name = "PIX1_PLL", - .data = &( - (struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_PIX1, - .status_reg = NULL, - .initial_rate = 594 * FWK_MHZ, - .min_rate = 12500 * FWK_KHZ, - .max_rate = 594 * FWK_MHZ, - .min_step = 25 * FWK_KHZ, - .defer_initialization = false, - }), - }, - [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ - }; - -static const struct fwk_element *system_pll_get_element_table( - fwk_id_t module_id) -{ - return system_pll_element_table; -} - -const struct fwk_module_config config_system_pll = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(system_pll_get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_system_power.c b/product/tc0/scp_ramfw/config_system_power.c deleted file mode 100644 index 7ae64572cfbf..000000000000 --- a/product/tc0/scp_ramfw/config_system_power.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "tc0_core.h" - -#include <mod_power_domain.h> -#include <mod_ppu_v1.h> -#include <mod_system_power.h> -#include <mod_tc0_system.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <fmw_cmsis.h> - -#include <stdint.h> - -static const uint8_t system_power_to_sys_ppu0_state[] = { - [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, - [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_OFF, - [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, -}; - -static const uint8_t system_power_to_sys_ppu1_state[] = { - [MOD_PD_STATE_ON] = (uint8_t)MOD_PD_STATE_ON, - [MOD_SYSTEM_POWER_POWER_STATE_SLEEP0] = (uint8_t)MOD_PD_STATE_ON, - [MOD_PD_STATE_OFF] = (uint8_t)MOD_PD_STATE_OFF, -}; - -static struct fwk_element system_power_element_table[] = { - [0] = - { - .name = "SYS-PPU-0", - .data = &((struct mod_system_power_dev_config){ - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_PPU_V1, - MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), - .sys_state_table = system_power_to_sys_ppu0_state, - }), - }, - - [1] = - { - .name = "SYS-PPU-1", - .data = &((struct mod_system_power_dev_config){ - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_PPU_V1, - MOD_PPU_V1_API_IDX_POWER_DOMAIN_DRIVER), - .sys_state_table = system_power_to_sys_ppu1_state, - }), - }, - - [2] = { 0 }, /* Termination description */ -}; - -static struct mod_system_power_config system_power_config = { - .soc_wakeup_irq = SOC_WAKEUP0_IRQ, - - /* System driver */ - .driver_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_TC0_SYSTEM), - .driver_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_TC0_SYSTEM, - MOD_TC0_SYSTEM_API_IDX_SYSTEM_POWER_DRIVER), - - /* Initial system state */ - .initial_system_power_state = MOD_PD_STATE_OFF, -}; - -static const struct fwk_element *tc0_system_get_element_table(fwk_id_t unused) -{ - struct mod_system_power_dev_config *dev_config_table; - unsigned int i; - - /* The system PPUs are placed after the core and cluster PPUs */ - unsigned int ppu_idx_base = - tc0_core_get_core_count() + tc0_core_get_cluster_count(); - - for (i = 0; i < (FWK_ARRAY_SIZE(system_power_element_table) - 1); i++) { - dev_config_table = - (struct mod_system_power_dev_config *)system_power_element_table[i] - .data; - dev_config_table->sys_ppu_id = - fwk_id_build_element_id(fwk_module_id_ppu_v1, ppu_idx_base + i); - } - - return system_power_element_table; -} - -const struct fwk_module_config config_system_power = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(tc0_system_get_element_table), - .data = &system_power_config, -}; diff --git a/product/tc0/scp_ramfw/config_tc0_power_model.c b/product/tc0/scp_ramfw/config_tc0_power_model.c deleted file mode 100644 index 8d5d3cdd1b2c..000000000000 --- a/product/tc0/scp_ramfw/config_tc0_power_model.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <mod_tc0_power_model.h> - -#include <fwk_module.h> - -static const struct fwk_element pm_elem_table[] = { - [0] = { - .name = "Power Model 0", - .data = &(struct mod_tc0_power_model_dev_config){ - .coeff = 1, - }, - }, - [1] = { - .name = "Power Model 1", - .data = &(struct mod_tc0_power_model_dev_config){ - .coeff = 1, - }, - }, - [2] = { - .name = "Power Model 2", - .data = &(struct mod_tc0_power_model_dev_config){ - .coeff = 1, - }, - }, - [3] = { 0 } /* Termination description */ -}; - -static const struct fwk_element *get_element_table(fwk_id_t module_id) -{ - return pm_elem_table; -}; - -const struct fwk_module_config config_tc0_power_model = { - .data = NULL, - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_thermal_mgmt.c b/product/tc0/scp_ramfw/config_thermal_mgmt.c deleted file mode 100644 index e9c98a295e2f..000000000000 --- a/product/tc0/scp_ramfw/config_thermal_mgmt.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <tc0_dvfs.h> - -#include <mod_tc0_power_model.h> -#include <mod_thermal_mgmt.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_module.h> - -#include <stddef.h> -#include <stdint.h> - -static struct mod_thermal_mgmt_actor_config actor_table_domain0[3] = { - [0] = { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TC0_POWER_MODEL, 0), - .dvfs_domain_id = - FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_KLEIN), - .weight = 100, - }, - [1] = { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TC0_POWER_MODEL, 1), - .dvfs_domain_id = - FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_MATTERHORN), - .weight = 100, - }, - [2] = { - .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TC0_POWER_MODEL, 2), - .dvfs_domain_id = - FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, DVFS_ELEMENT_IDX_MATTERHORN_ELP_ARM), - .weight = 100, - }, -}; - -static const struct fwk_element thermal_mgmt_domains_elem_table[2] = { - [0] = { - .name = "Thermal Domain 0", - .data = &((struct mod_thermal_mgmt_dev_config){ - .slow_loop_mult = 25, - .tdp = 10, - .pi_controller = { - .switch_on_temperature = 50, - .control_temperature = 60, - .integral_cutoff = 0, - .integral_max = 100, - .k_p_undershoot = 1, - .k_p_overshoot = 1, - .k_integral = 1, - }, - .sensor_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SENSOR, 0), - .driver_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_TC0_POWER_MODEL, - MOD_TC0_POWER_MODEL_THERMAL_DRIVER_API_IDX), - .thermal_actors_table = actor_table_domain0, - .thermal_actors_count = FWK_ARRAY_SIZE(actor_table_domain0), - }), - }, - [1] = { 0 } /* Termination description */ -}; - -static const struct fwk_element *get_element_table(fwk_id_t module_id) -{ - return thermal_mgmt_domains_elem_table; -} - -struct fwk_module_config config_thermal_mgmt = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_timer.c b/product/tc0/scp_ramfw/config_timer.c deleted file mode 100644 index 95ade7ff34c7..000000000000 --- a/product/tc0/scp_ramfw/config_timer.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "tc0_timer.h" - -#include <mod_timer.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <fmw_cmsis.h> - -/* - * Timer HAL config - */ -static const struct fwk_element timer_dev_table[] = { - [0] = - { - .name = "REFCLK", - .data = &((struct mod_timer_dev_config){ - .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), - .timer_irq = TIMREFCLK_IRQ, - }), - /* Number of alarms */ - .sub_element_count = CONFIG_TIMER_SUB_ELEMENT_IDX_COUNT, - }, - [1] = { 0 }, -}; - -static const struct fwk_element *timer_get_dev_table(fwk_id_t module_id) -{ - return timer_dev_table; -} - -const struct fwk_module_config config_timer = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(timer_get_dev_table), -}; diff --git a/product/tc0/scp_ramfw/config_traffic_cop.c b/product/tc0/scp_ramfw/config_traffic_cop.c deleted file mode 100644 index 14c4e2611357..000000000000 --- a/product/tc0/scp_ramfw/config_traffic_cop.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "scp_css_mmap.h" -#include "scp_software_mmap.h" -#include "tc0_core.h" -#include "tc0_dvfs.h" -#include "tc0_timer.h" - -#include <mod_traffic_cop.h> - -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -enum core_pd_idx { - CORE0_PD_IDX, - CORE1_PD_IDX, - CORE2_PD_IDX, - CORE3_PD_IDX, - CORE4_PD_IDX, - CORE5_PD_IDX, - CORE6_PD_IDX, - CORE7_PD_IDX -}; - -static struct mod_tcop_pct_table k_pct[] = { - { - /* - * Perf limit for 3 or 4 cores online. - * The first entry must be the maximum number of cores in this domain. - */ - .cores_online = 4, - .perf_limit = 1153 * 1000000UL, - }, - { - /* Perf limit for 1 or 2 cores online. */ - .cores_online = 2, - .perf_limit = 1844 * 1000000UL, - }, -}; - -static struct mod_tcop_pct_table m_pct[] = { - { - /* - * Perf limit for 3 cores online. - * The first entry must be the maximum number of cores in this domain. - */ - .cores_online = 3, - .perf_limit = 1893 * 1000000UL, - }, - { - /* Perf limit for 2 cores online. */ - .cores_online = 2, - .perf_limit = 2271 * 1000000UL, - }, - { - /* Perf limit for 1 core online. */ - .cores_online = 1, - .perf_limit = 2650 * 1000000UL, - }, -}; - -static const struct mod_tcop_core_config k_core_config[] = { - [0] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE0_PD_IDX), - .core_starts_online = true, - }, - [1] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE1_PD_IDX), - .core_starts_online = false, - }, - [2] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE2_PD_IDX), - .core_starts_online = false, - }, - [3] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE3_PD_IDX), - .core_starts_online = false, - }, -}; - -static const struct mod_tcop_core_config m_core_config[] = { - [0] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE4_PD_IDX), - .core_starts_online = false, - }, - [1] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE5_PD_IDX), - .core_starts_online = false, - }, - [2] = { - .pd_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_POWER_DOMAIN, CORE6_PD_IDX), - .core_starts_online = false, - }, -}; - -static const struct mod_tcop_domain_config k_domain_conf[] = { - [0] = { - .perf_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, - DVFS_ELEMENT_IDX_KLEIN), - .pct = k_pct, - .pct_size = FWK_ARRAY_SIZE(k_pct), - .core_config = k_core_config, - }, - [1] = { { 0 } }, -}; - -static const struct mod_tcop_domain_config m_domain_conf[] = { - [0] = { - .perf_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_DVFS, - DVFS_ELEMENT_IDX_MATTERHORN), - .pct = m_pct, - .pct_size = FWK_ARRAY_SIZE(m_pct), - .core_config = m_core_config, - }, - [1] = { { 0 } }, -}; - -static const struct fwk_element element_table[] = { - [0] = { - .name = "TCOP_KLEIN_ELEM", - .sub_element_count = 4, - .data = k_domain_conf, - }, - [1] = { - .name = "TCOP_MATTERHORN_ELEM", - .sub_element_count = 3, - .data = m_domain_conf, - }, - [2] = { 0 }, -}; - -static const struct fwk_element *tcop_get_element_table(fwk_id_t module_id) -{ - return element_table; -} -const struct fwk_module_config config_traffic_cop = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(tcop_get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_transport.c b/product/tc0/scp_ramfw/config_transport.c deleted file mode 100644 index fee6e50103c2..000000000000 --- a/product/tc0/scp_ramfw/config_transport.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "config_power_domain.h" -#include "scp_software_mmap.h" -#include "scp_tc0_mhu.h" -#include "tc0_core.h" -#include "tc0_scmi.h" - -#include <mod_transport.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <stdint.h> - -static const struct fwk_element transport_element_table[] = { - /* SCP_TC0_SCMI_SERVICE_IDX_PSCI */ - { .name = "PSCI", - .data = &((struct mod_transport_channel_config){ - .channel_type = MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, - .policies = - MOD_TRANSPORT_POLICY_INIT_MAILBOX | MOD_TRANSPORT_POLICY_SECURE, - .out_band_mailbox_address = (uintptr_t)SCP_SCMI_PAYLOAD_S_A2P_BASE, - .out_band_mailbox_size = SCP_SCMI_PAYLOAD_SIZE, - .driver_id = FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_MHU2, - SCP_TC0_MHU_DEVICE_IDX_SCP_AP_S_CLUS0, - 0), - .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MHU2, 0), - }) }, - /* SCP_TC0_SCMI_SERVICE_IDX_OSPM_0 */ - { .name = "OSPM0", - .data = &((struct mod_transport_channel_config){ - .channel_type = MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, - .policies = MOD_TRANSPORT_POLICY_INIT_MAILBOX, - .out_band_mailbox_address = (uintptr_t)SCP_SCMI_PAYLOAD0_NS_A2P_BASE, - .out_band_mailbox_size = SCP_SCMI_PAYLOAD_SIZE, - .driver_id = FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_MHU2, - SCP_TC0_MHU_DEVICE_IDX_SCP_AP_NS_HP_CLUS0, - 0), - .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MHU2, 0), - }) }, - /* SCP_TC0_SCMI_SERVICE_IDX_OSPM_1 */ - { .name = "OSPM1", - .data = &((struct mod_transport_channel_config){ - .channel_type = MOD_TRANSPORT_CHANNEL_TYPE_COMPLETER, - .policies = MOD_TRANSPORT_POLICY_INIT_MAILBOX, - .out_band_mailbox_address = (uintptr_t)SCP_SCMI_PAYLOAD1_NS_A2P_BASE, - .out_band_mailbox_size = SCP_SCMI_PAYLOAD_SIZE, - .driver_id = FWK_ID_SUB_ELEMENT_INIT( - FWK_MODULE_IDX_MHU2, - SCP_TC0_MHU_DEVICE_IDX_SCP_AP_NS_LP_CLUS0, - 0), - .driver_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MHU2, 0), - }) }, - [SCP_TC0_SCMI_SERVICE_IDX_COUNT] = { 0 }, -}; - -static const struct fwk_element *transport_get_element_table(fwk_id_t module_id) -{ - unsigned int idx; - struct mod_transport_channel_config *config; - - for (idx = 0; idx < SCP_TC0_SCMI_SERVICE_IDX_COUNT; idx++) { - config = - (struct mod_transport_channel_config *)(transport_element_table[idx] - .data); - config->pd_source_id = FWK_ID_ELEMENT( - FWK_MODULE_IDX_POWER_DOMAIN, - tc0_core_get_core_count() + tc0_core_get_cluster_count() + - PD_STATIC_DEV_IDX_SYSTOP); - } - - return transport_element_table; -} - -const struct fwk_module_config config_transport = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(transport_get_element_table), -}; diff --git a/product/tc0/scp_ramfw/config_voltage_domain.c b/product/tc0/scp_ramfw/config_voltage_domain.c deleted file mode 100644 index 6f4b0e39d782..000000000000 --- a/product/tc0/scp_ramfw/config_voltage_domain.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <config_mock_voltage_domain.h> - -#include <mod_mock_voltage_domain.h> -#include <mod_voltage_domain.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <stdint.h> - -static const struct fwk_element voltage_domain_element_table[] = { - [0] = { - .name = "DUMMY_VOLTD", - .data = &((const struct mod_voltd_dev_config){ - .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_MOCK_VOLTAGE_DOMAIN, - CONFIG_MOCK_VOLTAGE_DOMAIN_ELEMENT_IDX_DUMMY), - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_MOCK_VOLTAGE_DOMAIN, - MOD_MOCK_VOLTAGE_DOMAIN_API_IDX_VOLTD), - }), - }, - - [1] = { 0 }, /* Termination description */ -}; - -static const struct fwk_element *voltage_domain_get_element_table( - fwk_id_t module_id) -{ - return voltage_domain_element_table; -} - -const struct fwk_module_config config_voltage_domain = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(voltage_domain_get_element_table), -}; diff --git a/product/tc0/scp_ramfw/fmw_memory.h b/product/tc0/scp_ramfw/fmw_memory.h deleted file mode 100644 index 689fc0d3c400..000000000000 --- a/product/tc0/scp_ramfw/fmw_memory.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * RAM firmware memory layout for the linker script. - */ - -#ifndef FMW_MEMORY_H -#define FMW_MEMORY_H - -#include "scp_mmap.h" -#include "scp_software_mmap.h" - -#define FMW_MEM_MODE ARCH_MEM_MODE_SINGLE_REGION - -/* RAM */ -#define FMW_MEM0_BASE SCP_RAM_BASE -#define FMW_MEM0_SIZE SCP_RAM_SIZE - -#endif /* FMW_MEMORY_H */ diff --git a/product/tc0/scp_ramfw/fmw_notification.h b/product/tc0/scp_ramfw/fmw_notification.h deleted file mode 100644 index 33ee50eb933f..000000000000 --- a/product/tc0/scp_ramfw/fmw_notification.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * RAM firmware notification configuration. - */ - -#ifndef FMW_NOTIFICATION_H -#define FMW_NOTIFICATION_H - -#define FMW_NOTIFICATION_MAX 128 - -#endif /* FMW_NOTIFICATION_H */ diff --git a/product/tc0/scp_romfw/CMakeLists.txt b/product/tc0/scp_romfw/CMakeLists.txt deleted file mode 100644 index f9f40ad37e63..000000000000 --- a/product/tc0/scp_romfw/CMakeLists.txt +++ /dev/null @@ -1,53 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -# -# Create the firmware target. -# - -add_executable(tc0-bl1) - -target_include_directories( - tc0-bl1 PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/../include" - "${CMAKE_CURRENT_SOURCE_DIR}") - -# cmake-lint: disable=E1122 - -target_sources( - tc0-bl1 - PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/config_pl011.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_ppu_v1.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_sds.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_cmn_booker.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_system_pll.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_pik_clock.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_css_clock.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_clock.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_gtimer.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_timer.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_msys_rom.c" - "${CMAKE_CURRENT_SOURCE_DIR}/config_bootloader.c") - -# -# Some of our firmware includes require CMSIS. -# - -target_link_libraries(tc0-bl1 PUBLIC cmsis::core-m) - -# -# We explicitly add the CMSIS include directories to our interfaceinclude -# directories. Each module target adds these include directories totheir own, -# allowing them to include any firmware includes we expose. -# - -target_include_directories(tc0-bl1 - PUBLIC $<TARGET_PROPERTY:cmsis::core-m,INTERFACE_INCLUDE_DIRECTORIES>) - -cmake_dependent_option( - SCP_PLATFORM_VARIANT "Choose platform software variant?" - "${SCP_PLATFORM_VARIANT_INIT}" "DEFINED SCP_PLATFORM_VARIANT_INIT" - "${SCP_PLATFORM_VARIANT}") diff --git a/product/tc0/scp_romfw/Firmware.cmake b/product/tc0/scp_romfw/Firmware.cmake deleted file mode 100644 index 7f6586c2b62b..000000000000 --- a/product/tc0/scp_romfw/Firmware.cmake +++ /dev/null @@ -1,45 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -# -# Configure the build system. -# - -set(SCP_FIRMWARE "tc0-bl1") - -set(SCP_FIRMWARE_TARGET "tc0-bl1") - -set(SCP_TOOLCHAIN_INIT "GNU") - -set(SCP_GENERATE_FLAT_BINARY_INIT TRUE) - -set(SCP_ENABLE_NOTIFICATIONS_INIT TRUE) - -set(SCP_ENABLE_IPO_INIT FALSE) - -set(SCP_PLATFORM_VARIANT_INIT 0) - -set(SCP_ARCHITECTURE "arm-m") - -list(PREPEND SCP_MODULE_PATHS "${CMAKE_SOURCE_DIR}/module/cmn_booker") - -# The order of the modules in the following list is the order in which the -# modules are initialized, bound, started during the pre-runtime phase. -# any change in the order will cause firmware initialization errors. - -list(APPEND SCP_MODULES "pl011") -list(APPEND SCP_MODULES "ppu-v1") -list(APPEND SCP_MODULES "msys-rom") -list(APPEND SCP_MODULES "sds") -list(APPEND SCP_MODULES "bootloader") -list(APPEND SCP_MODULES "system-pll") -list(APPEND SCP_MODULES "pik-clock") -list(APPEND SCP_MODULES "css-clock") -list(APPEND SCP_MODULES "clock") -list(APPEND SCP_MODULES "gtimer") -list(APPEND SCP_MODULES "timer") -list(APPEND SCP_MODULES "cmn-booker") diff --git a/product/tc0/scp_romfw/Toolchain-ArmClang.cmake b/product/tc0/scp_romfw/Toolchain-ArmClang.cmake deleted file mode 100644 index 538e71a68663..000000000000 --- a/product/tc0/scp_romfw/Toolchain-ArmClang.cmake +++ /dev/null @@ -1,20 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -# cmake-lint: disable=C0301 - -include_guard() - -set(CMAKE_SYSTEM_PROCESSOR "cortex-m3") - -set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") -set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") -set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") - -include( - "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/ArmClang-Baremetal.cmake" -) diff --git a/product/tc0/scp_romfw/Toolchain-Clang.cmake b/product/tc0/scp_romfw/Toolchain-Clang.cmake deleted file mode 100644 index 7598d559f8be..000000000000 --- a/product/tc0/scp_romfw/Toolchain-Clang.cmake +++ /dev/null @@ -1,17 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -include_guard() - -set(CMAKE_SYSTEM_PROCESSOR "cortex-m3") - -set(CMAKE_ASM_COMPILER_TARGET "arm-arm-none-eabi") -set(CMAKE_C_COMPILER_TARGET "arm-arm-none-eabi") -set(CMAKE_CXX_COMPILER_TARGET "arm-arm-none-eabi") - -include( - "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/Clang-Baremetal.cmake") diff --git a/product/tc0/scp_romfw/Toolchain-GNU.cmake b/product/tc0/scp_romfw/Toolchain-GNU.cmake deleted file mode 100644 index a1fe8de32777..000000000000 --- a/product/tc0/scp_romfw/Toolchain-GNU.cmake +++ /dev/null @@ -1,18 +0,0 @@ -# -# Arm SCP/MCP Software -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -include_guard() - -set(CMAKE_SYSTEM_PROCESSOR "cortex-m3") -set(CMAKE_TOOLCHAIN_PREFIX "arm-none-eabi-") - -set(CMAKE_ASM_COMPILER_TARGET "arm-none-eabi") -set(CMAKE_C_COMPILER_TARGET "arm-none-eabi") -set(CMAKE_CXX_COMPILER_TARGET "arm-none-eabi") - -include( - "${CMAKE_CURRENT_LIST_DIR}/../../../cmake/Toolchain/GNU-Baremetal.cmake") diff --git a/product/tc0/scp_romfw/config_bootloader.c b/product/tc0/scp_romfw/config_bootloader.c deleted file mode 100644 index 5a74f25a0ee7..000000000000 --- a/product/tc0/scp_romfw/config_bootloader.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "scp_software_mmap.h" -#include "tc0_sds.h" - -#include <mod_bootloader.h> - -#include <fwk_module.h> - -static const struct mod_bootloader_config bootloader_module_config = { - .source_base = SCP_TRUSTED_RAM_BASE, - .source_size = 512 * 1024, - .destination_base = SCP_RAM_BASE, - .destination_size = SCP_RAM_SIZE, - .sds_struct_id = TC0_SDS_BOOTLOADER, -}; - -struct fwk_module_config config_bootloader = { - .data = &bootloader_module_config, -}; diff --git a/product/tc0/scp_romfw/config_clock.c b/product/tc0/scp_romfw/config_clock.c deleted file mode 100644 index d2386fae10c9..000000000000 --- a/product/tc0/scp_romfw/config_clock.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "config_power_domain.h" -#include "tc0_core.h" - -#include <mod_clock.h> -#include <mod_css_clock.h> -#include <mod_msys_rom.h> -#include <mod_pik_clock.h> -#include <mod_power_domain.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -static const struct fwk_element clock_dev_desc_table[] = { - [CLOCK_IDX_CPU_GROUP_KLEIN] = - { - .name = "CPU_GROUP_KLEIN", - .data = &((struct mod_clock_dev_config){ - .driver_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - CLOCK_CSS_IDX_CPU_GROUP_KLEIN), - .api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_CSS_CLOCK, - MOD_CSS_CLOCK_API_TYPE_CLOCK), - .pd_source_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_MSYS_ROM), - }), - }, - { 0 }, /* Termination description. */ -}; - -static const struct fwk_element *clock_get_dev_desc_table(fwk_id_t module_id) -{ - return clock_dev_desc_table; -} - -const struct fwk_module_config config_clock = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(clock_get_dev_desc_table), - .data = &((struct mod_clock_config){ - .pd_transition_notification_id = FWK_ID_NOTIFICATION_INIT( - FWK_MODULE_IDX_MSYS_ROM, - MOD_MSYS_ROM_NOTIFICATION_IDX_POWER_SYSTOP), - .pd_pre_transition_notification_id = FWK_ID_NONE_INIT, - }), -}; diff --git a/product/tc0/scp_romfw/config_cmn_booker.c b/product/tc0/scp_romfw/config_cmn_booker.c deleted file mode 100644 index e28c735095d4..000000000000 --- a/product/tc0/scp_romfw/config_cmn_booker.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "scp_css_mmap.h" - -#include <mod_cmn_booker.h> - -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -/* - * CMN_BOOKER nodes - */ -#define MEM_CNTRL0_ID 2 -#define MEM_CNTRL1_ID 14 -#define MEM_CNTRL2_ID 38 -#define MEM_CNTRL3_ID 46 -#define NODE_ID_HND 4 - -static const unsigned int snf_table[] = { - MEM_CNTRL0_ID, /* Maps to HN-F logical node 0 */ - MEM_CNTRL1_ID, /* Maps to HN-F logical node 1 */ - MEM_CNTRL2_ID, /* Maps to HN-F logical node 2 */ - MEM_CNTRL3_ID, /* Maps to HN-F logical node 3 */ -}; - -static const struct mod_cmn_booker_mem_region_map mmap[] = { - { - /* - * System cache backed region - * Map: 0x0000_0000_0000 - 0x003FF_FFFF_FFFF (4 TB) - */ - .base = UINT64_C(0x000000000000), - .size = UINT64_C(1) * FWK_TIB, - .type = MOD_CMN_BOOKER_MEM_REGION_TYPE_SYSCACHE, - }, - { - /* - * Boot region - * Map: 0x0000_0000_0000 - 0x0000_07FF_FFFF (128 MB) - */ - .base = UINT64_C(0x000000000000), - .size = UINT64_C(128) * FWK_MIB, - .type = MOD_CMN_BOOKER_MEM_REGION_TYPE_IO, - .node_id = NODE_ID_HND, - }, - { - /* - * Peripherals - * Map: 0x00_0800_0000 - 0x00_0FFF_FFFF (128 MB) - */ - .base = UINT64_C(0x0008000000), - .size = UINT64_C(128) * FWK_MIB, - .type = MOD_CMN_BOOKER_MEM_REGION_TYPE_IO, - .node_id = NODE_ID_HND, - }, - { - /* - * Peripherals - * Map: 0x00_1000_0000 - 0x00_1FFF_FFFF (256 MB) - */ - .base = UINT64_C(0x0010000000), - .size = UINT64_C(256) * FWK_MIB, - .type = MOD_CMN_BOOKER_MEM_REGION_TYPE_IO, - .node_id = NODE_ID_HND, - }, - { - /* - * Peripherals - * Map: 0x00_2000_0000 - 0x00_3FFF_FFFF (512 MB) - */ - .base = UINT64_C(0x0020000000), - .size = UINT64_C(512) * FWK_MIB, - .type = MOD_CMN_BOOKER_MEM_REGION_TYPE_IO, - .node_id = NODE_ID_HND, - }, - { - /* - * Peripherals - * Map: 0x00_4000_0000 - 0x00_7FFF_FFFF (1 GB) - */ - .base = UINT64_C(0x0040000000), - .size = UINT64_C(1) * FWK_GIB, - .type = MOD_CMN_BOOKER_MEM_REGION_TYPE_IO, - .node_id = NODE_ID_HND, - }, - { - /* - * Peripherals - * Map: 0x01_0000_0000 - 0x01_03FF_FFFF (64 MB) - */ - .base = UINT64_C(0x0100000000), - .size = UINT64_C(64) * FWK_MIB, - .type = MOD_CMN_BOOKER_MEM_REGION_TYPE_IO, - .node_id = NODE_ID_HND, - }, -}; - -const struct fwk_module_config config_cmn_booker = { - .data = &((struct mod_cmn_booker_config){ - .base = SCP_CMN_BOOKER_BASE, - .mesh_size_x = 2, - .mesh_size_y = 2, - .hnd_node_id = NODE_ID_HND, - .snf_table = snf_table, - .snf_count = FWK_ARRAY_SIZE(snf_table), - .mmap_table = mmap, - .mmap_count = FWK_ARRAY_SIZE(mmap), - .clock_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_KLEIN), - .hnf_cal_mode = false, - .ports_per_xp = 4, - }), -}; diff --git a/product/tc0/scp_romfw/config_css_clock.c b/product/tc0/scp_romfw/config_css_clock.c deleted file mode 100644 index a43fb332d229..000000000000 --- a/product/tc0/scp_romfw/config_css_clock.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" - -#include <mod_css_clock.h> -#include <mod_pik_clock.h> -#include <mod_system_pll.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -static const struct mod_css_clock_rate rate_table_cpu_group_klein[] = { - { - /* Super Underdrive */ - .rate = 768 * FWK_MHZ, - .pll_rate = 768 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Underdrive */ - .rate = 1153 * FWK_MHZ, - .pll_rate = 1153 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Nominal */ - .rate = 1537 * FWK_MHZ, - .pll_rate = 1537 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Overdrive */ - .rate = 1844 * FWK_MHZ, - .pll_rate = 1844 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, - { - /* Super Overdrive */ - .rate = 2152 * FWK_MHZ, - .pll_rate = 2152 * FWK_MHZ, - .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, - .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .clock_div = 1, - .clock_mod_numerator = 1, - .clock_mod_denominator = 1, - }, -}; - -static const fwk_id_t member_table_cpu_group_klein[] = { - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2), - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU3), -}; - -static const struct fwk_element css_clock_element_table[] = { - [CLOCK_CSS_IDX_CPU_GROUP_KLEIN] = - { - .name = "CPU_GROUP_KLEIN", - .data = &((struct mod_css_clock_dev_config){ - .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), - .clock_switching_source = - MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, - .pll_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - CLOCK_PLL_IDX_CPU_KLEIN), - .pll_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_SYSTEM_PLL, - MOD_SYSTEM_PLL_API_TYPE_DEFAULT), - .member_table = member_table_cpu_group_klein, - .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_klein), - .member_api_id = FWK_ID_API_INIT( - FWK_MODULE_IDX_PIK_CLOCK, - MOD_PIK_CLOCK_API_TYPE_CSS), - .initial_rate = 1537 * FWK_MHZ, - .modulation_supported = true, - }), - }, - [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */ -}; - -static const struct fwk_element *css_clock_get_element_table(fwk_id_t module_id) -{ - return css_clock_element_table; -} - -const struct fwk_module_config config_css_clock = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(css_clock_get_element_table), -}; diff --git a/product/tc0/scp_romfw/config_gtimer.c b/product/tc0/scp_romfw/config_gtimer.c deleted file mode 100644 index 098e7d108362..000000000000 --- a/product/tc0/scp_romfw/config_gtimer.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "scp_css_mmap.h" - -#include <mod_gtimer.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> -#include <fwk_time.h> - -/* - * Generic timer driver config - */ -static const struct fwk_element gtimer_dev_table[] = { - [0] = { .name = "REFCLK", - .data = &((struct mod_gtimer_dev_config){ - .hw_timer = SCP_REFCLK_CNTBASE0_BASE, - .hw_counter = SCP_REFCLK_CNTCTL_BASE, - .control = SCP_REFCLK_CNTCONTROL_BASE, - .frequency = CLOCK_RATE_REFCLK, - .clock_id = FWK_ID_ELEMENT_INIT( - FWK_MODULE_IDX_CLOCK, - CLOCK_IDX_CPU_GROUP_KLEIN) }) }, - [1] = { 0 }, -}; - -const struct fwk_module_config config_gtimer = { - .elements = FWK_MODULE_STATIC_ELEMENTS_PTR(gtimer_dev_table), -}; - -struct fwk_time_driver fmw_time_driver(const void **ctx) -{ - return mod_gtimer_driver(ctx, config_gtimer.elements.table[0].data); -} diff --git a/product/tc0/scp_romfw/config_msys_rom.c b/product/tc0/scp_romfw/config_msys_rom.c deleted file mode 100644 index 93e0723e3c2d..000000000000 --- a/product/tc0/scp_romfw/config_msys_rom.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "scp_software_mmap.h" - -#include <mod_msys_rom.h> - -#include <fwk_id.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -const struct fwk_module_config config_msys_rom = { - .data = &((struct msys_rom_config){ - .ap_context_base = SCP_AP_CONTEXT_BASE, - .ap_context_size = SCP_AP_CONTEXT_SIZE, - .id_primary_cluster = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, 1), - .id_primary_core = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PPU_V1, 0), - }) -}; diff --git a/product/tc0/scp_romfw/config_pik_clock.c b/product/tc0/scp_romfw/config_pik_clock.c deleted file mode 100644 index 0a29b4675d80..000000000000 --- a/product/tc0/scp_romfw/config_pik_clock.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "cpu_pik.h" -#include "system_pik.h" - -#include <mod_pik_clock.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> -/* - * Rate lookup tables - */ -static struct mod_pik_clock_rate rate_table_cpu_group_klein[] = { - { - .rate = 1537 * FWK_MHZ, - .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT, - .divider = 1, /* Rate adjusted via CPU PLL */ - }, -}; - -static const struct mod_pik_clock_rate rate_table_gicclk[] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static const struct mod_pik_clock_rate rate_table_pclkscp[] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static const struct mod_pik_clock_rate rate_table_sysperclk[] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static const struct mod_pik_clock_rate rate_table_uartclk[] = { - { - .rate = 2000 * FWK_MHZ, - .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK, - .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS, - .divider = CLOCK_RATE_SYSPLLCLK / (2000 * FWK_MHZ), - }, -}; - -static const struct fwk_element - pik_clock_element_table[] = - { - [CLOCK_PIK_IDX_CLUS0_CPU0] = - { - .name = "CLUS0_CPU0", - .data = &((struct mod_pik_clock_dev_config){ - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU1] = - { - .name = "CLUS0_CPU1", - .data = &((struct mod_pik_clock_dev_config){ - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU2] = - { - .name = "CLUS0_CPU2", - .data = &((struct mod_pik_clock_dev_config){ - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), - }), - }, - [CLOCK_PIK_IDX_CLUS0_CPU3] = - { - .name = "CLUS0_CPU3", - .data = &((struct mod_pik_clock_dev_config){ - .type = MOD_PIK_CLOCK_TYPE_CLUSTER, - .is_group_member = true, - .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].CTRL, - .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].MOD, - .rate_table = rate_table_cpu_group_klein, - .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein), - }), - }, - [CLOCK_PIK_IDX_GIC] = - { - .name = "GIC", - .data = &((struct mod_pik_clock_dev_config){ - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->GICCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->GICCLK_DIV1, - .rate_table = rate_table_gicclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_gicclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_PCLKSCP] = - { - .name = "PCLKSCP", - .data = &((struct mod_pik_clock_dev_config){ - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->PCLKSCP_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->PCLKSCP_DIV1, - .rate_table = rate_table_pclkscp, - .rate_count = FWK_ARRAY_SIZE(rate_table_pclkscp), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_SYSPERCLK] = - { - .name = "SYSPERCLK", - .data = - &( - (struct mod_pik_clock_dev_config){ - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->SYSPERCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->SYSPERCLK_DIV1, - .rate_table = rate_table_sysperclk, - .rate_count = - FWK_ARRAY_SIZE(rate_table_sysperclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_UARTCLK] = - { - .name = "UARTCLK", - .data = &( - (struct mod_pik_clock_dev_config){ - .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE, - .is_group_member = false, - .control_reg = &SYSTEM_PIK_PTR->UARTCLK_CTRL, - .divsys_reg = &SYSTEM_PIK_PTR->UARTCLK_DIV1, - .rate_table = rate_table_uartclk, - .rate_count = FWK_ARRAY_SIZE(rate_table_uartclk), - .initial_rate = 2000 * FWK_MHZ, - }), - }, - [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */ - }; - -static const struct fwk_element *pik_clock_get_element_table(fwk_id_t module_id) -{ - return pik_clock_element_table; -} - -const struct fwk_module_config config_pik_clock = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(pik_clock_get_element_table), -}; diff --git a/product/tc0/scp_romfw/config_pl011.c b/product/tc0/scp_romfw/config_pl011.c deleted file mode 100644 index d548a13b8cbd..000000000000 --- a/product/tc0/scp_romfw/config_pl011.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "scp_css_mmap.h" - -#include <mod_pl011.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> - -const struct fwk_module_config config_pl011 = { - .elements = FWK_MODULE_STATIC_ELEMENTS({ - [0] = { - .name = "uart", - .data = - &(struct mod_pl011_element_cfg){ - .reg_base = SCP_UART_BOARD_BASE, - .baud_rate_bps = 115200, - .clock_rate_hz = 24 * FWK_MHZ, - .clock_id = FWK_ID_NONE_INIT, - }, - }, - - [1] = { 0 }, - }), -}; diff --git a/product/tc0/scp_romfw/config_ppu_v1.c b/product/tc0/scp_romfw/config_ppu_v1.c deleted file mode 100644 index 18d1f112a412..000000000000 --- a/product/tc0/scp_romfw/config_ppu_v1.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "config_power_domain.h" -#include "scp_css_mmap.h" -#include "tc0_core.h" - -#include <mod_cmn_booker.h> -#include <mod_msys_rom.h> -#include <mod_power_domain.h> -#include <mod_ppu_v1.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_interrupt.h> -#include <fwk_macros.h> -#include <fwk_mm.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <stdio.h> -#include <string.h> - -/* Maximum PPU core name size including the null terminator */ -#define PPU_CORE_NAME_SIZE 12 - -/* Maximum PPU cluster name size including the null terminator */ -#define PPU_CLUS_NAME_SIZE 6 - -/* Lookup table for translating cluster indicies into CMN_BOOKER node IDs */ -static const unsigned int cluster_idx_to_node_id[] = { 68 }; - -static struct fwk_element ppu_v1_system_element_table[] = { - { - .name = "SYS0", - .data = &((struct mod_ppu_v1_pd_config){ - .pd_type = MOD_PD_TYPE_SYSTEM, - .ppu.reg_base = SCP_PPU_SYS0_BASE, - .observer_id = FWK_ID_NONE_INIT, - .default_power_on = true, - }), - }, - { - .name = "SYS1", - .data = &((struct mod_ppu_v1_pd_config){ - .pd_type = MOD_PD_TYPE_SYSTEM, - .ppu.reg_base = SCP_PPU_SYS1_BASE, - .observer_id = FWK_ID_NONE_INIT, - .default_power_on = true, - }), - }, - { 0 }, /* Termination entry */ -}; - -static const struct fwk_element *tc0_ppu_v1_get_element_table( - fwk_id_t module_id) -{ - struct fwk_element *element_table, *element; - struct mod_ppu_v1_pd_config *pd_config_table, *pd_config; - - /* - * Allocate element descriptors based on: - * Core0 - * + Cluster0 - * + Number of system power domain descriptors - * + 1 terminator descriptor - */ - element_table = fwk_mm_calloc( - 2 + FWK_ARRAY_SIZE(ppu_v1_system_element_table) + 1, - sizeof(struct fwk_element)); - if (element_table == NULL) - return NULL; - - pd_config_table = fwk_mm_calloc(2, sizeof(struct mod_ppu_v1_pd_config)); - if (pd_config_table == NULL) - return NULL; - - // pd_config for core0 - element = &element_table[0]; - pd_config = &pd_config_table[0]; - - element->name = fwk_mm_alloc(PPU_CORE_NAME_SIZE, 1); - if (element->name == NULL) - return NULL; - - snprintf((char *)element->name, PPU_CORE_NAME_SIZE, "CLUS0CORE0"); - - element->data = pd_config; - - pd_config->pd_type = MOD_PD_TYPE_CORE; - pd_config->ppu.reg_base = SCP_PPU_CORE_BASE(0); - pd_config->ppu.irq = FWK_INTERRUPT_NONE; - pd_config->cluster_id = FWK_ID_ELEMENT(FWK_MODULE_IDX_PPU_V1, 1); - pd_config->observer_id = FWK_ID_NONE; - - // pd_config for cluster0 - element = &element_table[1]; - pd_config = &pd_config_table[1]; - - element->name = fwk_mm_alloc(PPU_CLUS_NAME_SIZE, 1); - if (element->name == NULL) - return NULL; - - snprintf((char *)element->name, PPU_CLUS_NAME_SIZE, "CLUS0"); - - element->data = pd_config; - - pd_config->pd_type = MOD_PD_TYPE_CLUSTER; - pd_config->ppu.reg_base = SCP_PPU_CLUSTER_BASE; - pd_config->ppu.irq = FWK_INTERRUPT_NONE; - - pd_config->observer_id = fwk_module_id_cmn_booker; - pd_config->observer_api = FWK_ID_API( - FWK_MODULE_IDX_CMN_BOOKER, MOD_CMN_BOOKER_API_IDX_PPU_OBSERVER); - pd_config->post_ppu_on_param = (void *)&cluster_idx_to_node_id[0]; - - memcpy( - &element_table[2], - ppu_v1_system_element_table, - sizeof(ppu_v1_system_element_table)); - - return element_table; -} - -/* - * Power module configuration data - */ -struct fwk_module_config config_ppu_v1 = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(tc0_ppu_v1_get_element_table), - .data = - &(struct mod_ppu_v1_config){ - .pd_notification_id = FWK_ID_NOTIFICATION_INIT( - FWK_MODULE_IDX_MSYS_ROM, - MOD_MSYS_ROM_NOTIFICATION_IDX_POWER_SYSTOP), - .pd_source_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_MSYS_ROM), - }, -}; diff --git a/product/tc0/scp_romfw/config_sds.c b/product/tc0/scp_romfw/config_sds.c deleted file mode 100644 index dadca5039c63..000000000000 --- a/product/tc0/scp_romfw/config_sds.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "scp_pik.h" -#include "scp_software_mmap.h" -#include "tc0_sds.h" - -#include <mod_sds.h> - -#include <fwk_assert.h> -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <stdbool.h> -#include <stdint.h> - -static const uint32_t feature_flags = 0x00000000; - -static const struct mod_sds_region_desc sds_module_regions[] = { - [TC0_SDS_REGION_SECURE] = - { - .base = (void *)SCP_SDS_MEM_BASE, - .size = SCP_SDS_MEM_SIZE, - }, -}; - -static_assert( - FWK_ARRAY_SIZE(sds_module_regions) == TC0_SDS_REGION_COUNT, - "Mismatch between number of SDS regions and number of regions " - "provided by the SDS configuration."); - -const struct mod_sds_config sds_module_config = { - .regions = sds_module_regions, - .region_count = TC0_SDS_REGION_COUNT, - .clock_id = - FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_KLEIN) -}; - -static struct fwk_element sds_element_table[] = { - { - .name = "CPU Info", - .data = &((struct mod_sds_structure_desc){ - .id = TC0_SDS_CPU_INFO, - .size = TC0_SDS_CPU_INFO_SIZE, - .region_id = TC0_SDS_REGION_SECURE, - .finalize = true, - }), - }, - { - .name = "Feature Availability", - .data = &((struct mod_sds_structure_desc){ - .id = TC0_SDS_FEATURE_AVAILABILITY, - .size = TC0_SDS_FEATURE_AVAILABILITY_SIZE, - .payload = &feature_flags, - .region_id = TC0_SDS_REGION_SECURE, - .finalize = true, - }), - }, - { - .name = "Bootloader", - .data = &((struct mod_sds_structure_desc){ - .id = TC0_SDS_BOOTLOADER, - .size = TC0_SDS_BOOTLOADER_SIZE, - .region_id = TC0_SDS_REGION_SECURE, - .finalize = true, - }), - }, - { 0 }, /* Termination description. */ -}; - -static_assert( - SCP_SDS_MEM_SIZE > TC0_SDS_CPU_INFO_SIZE + - TC0_SDS_FEATURE_AVAILABILITY_SIZE + TC0_SDS_BOOTLOADER_SIZE, - "SDS structures too large for SDS SRAM.\n"); - -static const struct fwk_element *sds_get_element_table(fwk_id_t module_id) -{ - static_assert(BUILD_VERSION_MAJOR < UINT8_MAX, "Invalid version size"); - static_assert(BUILD_VERSION_MINOR < UINT8_MAX, "Invalid version size"); - static_assert(BUILD_VERSION_PATCH < UINT16_MAX, "Invalid version size"); - - return sds_element_table; -} - -struct fwk_module_config config_sds = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(sds_get_element_table), - .data = &sds_module_config, -}; diff --git a/product/tc0/scp_romfw/config_system_pll.c b/product/tc0/scp_romfw/config_system_pll.c deleted file mode 100644 index 5e082d288f39..000000000000 --- a/product/tc0/scp_romfw/config_system_pll.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "clock_soc.h" -#include "scp_pik.h" -#include "scp_soc_mmap.h" - -#include <mod_system_pll.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_macros.h> -#include <fwk_module.h> - -static const struct fwk_element system_pll_element_table[] = { - [CLOCK_PLL_IDX_CPU_KLEIN] = - { - .name = "CPU_PLL_KLEIN", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_CPU_TYPE0, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1], - .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0), - .initial_rate = 1537 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_SYS] = - { - .name = "SYS_PLL", - .data = &((struct mod_system_pll_dev_config){ - .control_reg = (void *)SCP_PLL_SYSPLL, - .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0], - .lock_flag_mask = PLL_STATUS_0_SYSPLLLOCK, - .initial_rate = 2000 * FWK_MHZ, - .min_rate = MOD_SYSTEM_PLL_MIN_RATE, - .max_rate = MOD_SYSTEM_PLL_MAX_RATE, - .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL, - }), - }, - [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */ -}; - -static const struct fwk_element *system_pll_get_element_table( - fwk_id_t module_id) -{ - return system_pll_element_table; -} - -const struct fwk_module_config config_system_pll = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(system_pll_get_element_table), -}; diff --git a/product/tc0/scp_romfw/config_timer.c b/product/tc0/scp_romfw/config_timer.c deleted file mode 100644 index 9d1665582c91..000000000000 --- a/product/tc0/scp_romfw/config_timer.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <mod_timer.h> - -#include <fwk_element.h> -#include <fwk_id.h> -#include <fwk_module.h> -#include <fwk_module_idx.h> - -#include <fmw_cmsis.h> - -/* - * Timer HAL config - */ -static const struct fwk_element timer_dev_table[] = { - [0] = - { - .name = "REFCLK", - .data = &((struct mod_timer_dev_config){ - .id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_GTIMER, 0), - .timer_irq = TIMREFCLK_IRQ, - }), - .sub_element_count = 8, /* Number of alarms */ - }, - [1] = { 0 }, -}; - -static const struct fwk_element *timer_get_dev_table(fwk_id_t module_id) -{ - return timer_dev_table; -} - -const struct fwk_module_config config_timer = { - .elements = FWK_MODULE_DYNAMIC_ELEMENTS(timer_get_dev_table), -}; diff --git a/product/tc0/scp_romfw/fmw_memory.h b/product/tc0/scp_romfw/fmw_memory.h deleted file mode 100644 index 029e6d5483ee..000000000000 --- a/product/tc0/scp_romfw/fmw_memory.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Arm SCP/MCP Software - * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Description: - * ROM firmware memory layout for the linker script. - */ - -#ifndef FMW_MEMORY_H -#define FMW_MEMORY_H - -#include "scp_mmap.h" -#include "scp_software_mmap.h" - -#define FMW_MEM_MODE ARCH_MEM_MODE_DUAL_REGION_RELOCATION - -/* - * ROM memory - */ -#define FMW_MEM0_SIZE SCP_BOOT_ROM_SIZE -#define FMW_MEM0_BASE SCP_BOOT_ROM_BASE - -/* - * RAM memory for scp_romfw (16 KiB block at the top of the RAM) - * - * The last 16 KiB of SCP RAM are used for scp_romfw data regions. - * The start of the RAM is where the scp bootloader places the scp_ramfw - * so the 2 areas don't overlap. - */ -#define FMW_MEM1_SIZE (16 * 1024) -#define FMW_MEM1_BASE (SCP_RAM_BASE + SCP_RAM_SIZE - FMW_MEM1_SIZE) - -#endif /* FMW_MEMORY_H */ diff --git a/readme.md b/readme.md index a084349b71c9..3ef5286284e4 100644 --- a/readme.md +++ b/readme.md @@ -1,7 +1,7 @@ SCP-firmware - version 2.13 =========================== -Copyright (c) 2011-2023, Arm Limited. All rights reserved. +Copyright (c) 2011-2024, Arm Limited. All rights reserved. References ---------- @@ -69,7 +69,6 @@ Virtual Platforms (FVPs or boards where possible): - RD-V1 reference design (Please contact Arm directly to obtain the RD_V1 FVP) - RD-V1-MC reference design (Please contact Arm directly to obtain the RD_V1_Multichip FVP) - Renesas R-Car platform -- Total Compute (tc0) platform (Please contact Arm directly to obtain the TC0 FVP) - Morello (Please see Arm's Ecosystem FVPs Developer page) - Total Compute (tc1) platform (Please contact Arm directly to obtain the TC1 FVP) diff --git a/tools/cppcheck_suppress_list.txt b/tools/cppcheck_suppress_list.txt index 86b4f4f76cf7..8b3ccad8ac0d 100755 --- a/tools/cppcheck_suppress_list.txt +++ b/tools/cppcheck_suppress_list.txt @@ -48,9 +48,6 @@ preprocessorErrorDirective:*arch/arm/armv8-a/src/arch_mm.c:17 // This memory has a static lifetime memleak:*product/rdv1mc/scp_ramfw/config_power_domain.c:156 memleak:*product/rdv1mc/scp_ramfw/config_ppu_v1.c:87 -memleak:*product/tc0/scp_ramfw/config_power_domain.c:114 -memleak:*product/tc0/scp_ramfw/config_ppu_v1.c:87 -memleak:*product/tc0/scp_romfw/config_ppu_v1.c:81 // This memory has static lifetime memleak:*framework/test/fwk_test.c:145 |