diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2024-04-06 11:06:56 -1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-04-09 07:45:09 -1000 |
| commit | e2313450274659a08d9791435766dc43ab388aa9 (patch) | |
| tree | 033d464914cdf47f551158542649c3cd0de0b35c | |
| parent | 8df1ba49d76e30fa5c8889121f4ed206ad6c2098 (diff) | |
target/microblaze: Use insn_start from DisasContextBase
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/microblaze/translate.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4e52ef32db..fc451befae 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -62,9 +62,6 @@ typedef struct DisasContext { DisasContextBase base; const MicroBlazeCPUConfig *cfg; - /* TCG op of the current insn_start. */ - TCGOp *insn_start; - TCGv_i32 r0; bool r0_set; @@ -699,14 +696,14 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) static void record_unaligned_ess(DisasContext *dc, int rd, MemOp size, bool store) { - uint32_t iflags = tcg_get_insn_start_param(dc->insn_start, 1); + uint32_t iflags = tcg_get_insn_start_param(dc->base.insn_start, 1); iflags |= ESR_ESS_FLAG; iflags |= rd << 5; iflags |= store * ESR_S; iflags |= (size == MO_32) * ESR_W; - tcg_set_insn_start_param(dc->insn_start, 1, iflags); + tcg_set_insn_start_param(dc->base.insn_start, 1, iflags); } #endif @@ -1624,7 +1621,6 @@ static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) DisasContext *dc = container_of(dcb, DisasContext, base); tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK); - dc->insn_start = tcg_last_op(); } static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) |