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authorPeter Maydell <peter.maydell@linaro.org>2020-06-22 13:46:46 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-06-22 13:46:46 +0100
commitb0e5a627021f6146b757cb21ea3e6a02d58bf50b (patch)
tree452b6d45747340520e73e5b9aabf4cc3f08884b0
parentf142dc624f8c6347a507d6cf69ae849027df7062 (diff)
downloadrisu-b0e5a627021f6146b757cb21ea3e6a02d58bf50b.tar.gz
arm.risu: Correct VLDR/VSTR U=0 patterns
Correct the VLDR and VSTR patterns, which claimed to be setting U=0 but in fact left it identical to the U=1 pattern due to a cut-and-paste error. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-rw-r--r--arm.risu4
1 files changed, 2 insertions, 2 deletions
diff --git a/arm.risu b/arm.risu
index f8b6deb..43a72ae 100644
--- a/arm.risu
+++ b/arm.risu
@@ -757,7 +757,7 @@ VLDM A1c cond:4 110 p u d 1 1 rn:4 vd:4 101 x imm:8 !constraints { $p == $u; }
VSTR A1a cond:4 1101 1 d 00 rn:4 vd:4 101 x imm:8 \
!memory { reg_plus_imm($rn, $imm * 4); }
# both A1 and A2 encodings, U = 0
-VSTR A1b cond:4 1101 1 d 00 rn:4 vd:4 101 x imm:8 \
+VSTR A1b cond:4 1101 0 d 00 rn:4 vd:4 101 x imm:8 \
!memory { reg_minus_imm($rn, $imm * 4); }
# VLDR
@@ -765,7 +765,7 @@ VSTR A1b cond:4 1101 1 d 00 rn:4 vd:4 101 x imm:8 \
VLDR A1a cond:4 1101 1 d 01 rn:4 vd:4 101 x imm:8 \
!memory { reg_plus_imm($rn, $imm * 4); }
# both A1 and A2 encodings, U = 0
-VLDR A1b cond:4 1101 1 d 01 rn:4 vd:4 101 x imm:8 \
+VLDR A1b cond:4 1101 0 d 01 rn:4 vd:4 101 x imm:8 \
!memory { reg_minus_imm($rn, $imm * 4); }
########### Extension register transfer ###################