diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2018-02-28 08:48:16 -0800 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2018-03-01 11:49:03 +0000 |
commit | f8f6c6aef61a75c1973d7ce23337017b8a72186e (patch) | |
tree | b68877b34cef093f37be566d2cd52b520e1b34bb | |
parent | 1b54495d6608dbe2ee9c31840b9033878b01a430 (diff) |
Add arm and thumb vqrdml[as]h, vcadd, vcmla
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | arm.risu | 25 | ||||
-rw-r--r-- | thumb.risu | 25 |
2 files changed, 50 insertions, 0 deletions
@@ -831,3 +831,28 @@ VCVT_rm_neon A1 1111 00111 d 11 size:2 11 vd:4 00 rm:2 op q m 0 vm:4 # Note that sz == 0b11 is UNPREDICTABLE (either UNDEF, NOP or as if == 0b10) # as is cond != 1110 (either UNDEF, NOP, cond-exec or unconditional exec) CRC32 A1 1110 00010 sz:2 0 rn:4 rd:4 00 c 0 0100 rm:4 !constraints { $sz != 3; } + +# +# ARMv8.1 extensions +# +@v8_1_simd + +VQRDMLAH A1 111100110 d:1 size:2 vn:4 vd:4 1011 n:1 q:1 m:1 1 vm:4 +VQRDMLAH_s A1 1111001 q:1 1 d:1 size:2 vn:4 vd:4 1110 n:1 1 m:1 0 vm:4 + +VQRDMLSH A1 111100110 d:1 size:2 vn:4 vd:4 1100 n:1 q:1 m:1 1 vm:4 +VQRDMLSH_s A1 1111001 q:1 1 d:1 size:2 vn:4 vd:4 1111 n:1 1 m:1 0 vm:4 + +# +# ARMv8.3 extensions +# +@v8_3_compnum + +# Disable fp16 until qemu supports it. +VCADD A1 1111110 rot:1 1 d:1 0 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } + +VCMLA A1 1111110 rot:2 d:1 1 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } +VCMLA_s A1 11111110 s:1 d:1 rot:2 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } @@ -437,3 +437,28 @@ STR T2 11111 000 0100 rn:4 rt:4 000000 imm:2 rm:4 \ # V8 only instructions CRC32 T1 111 1101 011 0 c rn:4 1111 rd:4 10 sz:2 rm:4 !constraints { $sz != 3; } + +# +# ARMv8.1 extensions +# +@v8_1_simd + +VQRDMLAH T1 111111110 d:1 size:2 vn:4 vd:4 1011 n:1 q:1 m:1 1 vm:4 +VQRDMLAH_s T1 111 q:1 11111 d:1 size:2 vn:4 vd:4 1110 n:1 1 m:1 0 vm:4 + +VQRDMLSH T1 111111110 d:1 size:2 vn:4 vd:4 1100 n:1 q:1 m:1 1 vm:4 +VQRDMLSH_s T1 111 q:1 11111 d:1 size:2 vn:4 vd:4 1111 n:1 1 m:1 0 vm:4 + +# +# ARMv8.3 extensions +# +@v8_3_compnum + +# Disable fp16 until qemu supports it. +VCADD T1 1111110 rot:1 1 d:1 0 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } + +VCMLA T1 1111110 rot:2 d:1 1 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } +VCMLA_s T1 11111110 s:1 d:1 rot:2 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \ +!constraints { $s != 0; } |