diff options
Diffstat (limited to 'arm.risu')
| -rw-r--r-- | arm.risu | 21 |
1 files changed, 0 insertions, 21 deletions
@@ -11,27 +11,6 @@ # Input file for risugen defining ARM instructions -# The format here is: -# insnname encodingname bitfield ... [ { eval-block } ] -# (and we'll have a trailing bit for specifying constraints later) -# where each bitfield is either: -# var:sz specifying a variable field of size sz (sz == 0 if :sz omitted) -# [01]* specifying fixed bits -# Field names beginning 'r' are special as they are assumed to be general -# purpose registers. They get an automatic "cannot be 13 or 15" (sp/pc) -# constraint. -# The optional eval-block at the end of the line (which must be -# enclosed in braces) is a perl statement to be evaluated and which -# must return true if the generated statement is OK, false if the -# generator should retry with a fresh random number. It is evaluated -# in a context where variables with the same names as the defined -# variable fields are initialised. The intention is that odd cases -# where you need to apply some sort of constraint to the generated -# instruction can be handled via this mechanism. -# NB that there is no sanity checking that you don't do bad things -# in the eval block, although there is a basic check for syntax -# errors and and we bail out if the constraint returns failure too often. - # Some random patterns #ADD A1 cond:4 0000 100 s rn:4 rd:4 imm:5 type:2 0 rm:4 #RBIT A1 cond:4 0110 1111 1111 rd:4 1111 0011 rm:4 |