aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2023-12-14loongarch: Add LASX instructionsHEADmasterSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Message-id: 20231213081839.4176614-7-gaosong@loongson.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-12-14loongarch: Add LSX instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Message-id: 20231213081839.4176614-6-gaosong@loongson.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-12-14loongarch: Add clean_lsx_result()Song Gao
The result of the LSX instruction is in the low 128 bits of the vreg register. We use clean_lsx_result() to clean up the high 128 bits of the vreg register. Signed-off-by: Song Gao <gaosong@loongson.cn> Message-id: 20231213081839.4176614-5-gaosong@loongson.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-12-14loongarch: init LASX registersSong Gao
Most of LoongArch cpus have LSX and LASX, so we can init LASX registers for risu test. we use $f0-$f31 value to init LASX $vreg0- $vreg31 registers. Signed-off-by: Song Gao <gaosong@loongson.cn> Message-id: 20231213081839.4176614-4-gaosong@loongson.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-12-14loongarch: reginfo suport LSX/LASXSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Message-id: 20231213081839.4176614-3-gaosong@loongson.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-12-14loongarch: Rename block type 'safefloat' to 'post'Song Gao
Rename block type 'safefloat' to 'post', it is the hook for doing things after emitting the instruction. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-id: 20231213081839.4176614-2-gaosong@loongson.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-18build-all-archs: Add s390x to the script that builds all architecturesThomas Huth
To avoid regressions, let's check s390x also via this file. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 20230914113311.379537-7-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-18s390x: Update the configure script for s390x supportThomas Huth
Auto-detect s390x hosts and add s390x information to the help text. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 20230914113311.379537-6-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-18s390x: Add basic risugen perl module for s390xThomas Huth
This implements support for simple 16-bit and 32-bit instructions. Support for 48-bit instructions and support for load/store memory instructions is not implemented yet. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 20230914113311.379537-5-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-18s390x: Add simple s390x.risu fileThomas Huth
This only adds a limited set of s390x instructions for initial testing. More instructions will be added later. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 20230914113311.379537-4-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-18s390x: Add basic s390x support to the C codeThomas Huth
With these changes, it is now possible to compile the "risu" binary for s390x hosts. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 20230914113311.379537-3-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-18Pass siginfo_t->si_addr to the reginfo_init() functionThomas Huth
On s390x, we need the si_addr from the siginfo_t to get to the address of the illegal instruction (the PSW address in the ucontext_t is already pointing to the next instruction there). So let's prepare for that situation and pass the si_addr to the reginfo_init() function everywhere. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 20230914113311.379537-2-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-20loongarch: Add block 'safefloat' and nanbox_s()Song Gao
Some LoongArch instructions don't care the high 32bit, so use nanbox_s() set the high 32bit 0xffffffff. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-id: 20221013082854.878546-6-gaosong@loongson.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-20loongarch: Add risufile with loongarch instructionsSong Gao
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-id: 20221013082854.878546-5-gaosong@loongson.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-20loongarch: Implement risugen moduleSong Gao
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-id: 20221013082854.878546-4-gaosong@loongson.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-20loongarch: Add LoongArch basic test supportSong Gao
This patch adds LoongArch server, client support, and basic test file. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-id: 20221013082854.878546-3-gaosong@loongson.cn [PMM: fixed get_risuop() return type] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-20risu: Use alternate stackSong Gao
We can use alternate stack, so that we can use sp register as intput/ouput register. I had tested aarch64/LoongArch architecture. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-id: 20221013082854.878546-2-gaosong@loongson.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18ppc64: Use uint64_t to represent doubleRichard Henderson
We want to do exact bitwise comparisons of the data, not be held hostage to IEEE comparisons and NaNs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-id: 20220708154700.18682-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18aarch64: Use arch_init to configure sveRichard Henderson
Adjust some of the aarch64 code to look at the reginfo struct instead of looking at test_sve, so that we do not need to pass the --test-sve option in order to dump sve trace files. Diagnose EINVAL as either cpu or kernel does not support SVE. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-22-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18aarch64: Reorg sve reginfo to save spaceRichard Henderson
Mirror the signal frame by storing all of the registers as a lump. Use the signal macros to pull out the values. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220708154700.18682-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18aarch64: Assume system support for SVERichard Henderson
SVE support is no longer new, assume it's present. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220708154700.18682-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Compute reginfo_size based on the reginfoRichard Henderson
This will allow dumping of SVE frames without having to know the SVE vector length beforehand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220708154700.18682-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Add magic and size to the trace headerRichard Henderson
Sanity check that we're not getting out of sync with the trace stream. This will be especially bad with the change in size of the sve save data. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220708154700.18682-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Split out recv_register_infoRichard Henderson
We will want to share this code when dumping. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220708154700.18682-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Rearrange reginfo and memblock buffersRichard Henderson
For send_register_info from master_sigill, do not keep a reginfo buffer on the stack. At the moment, this struct is quite large for aarch64. Put the two reginfo buffers into an array, for the benefit of future dumping. For recv_and_compare_register_info, index this array with constants, so it's a simple rename. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220708154700.18682-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Merge reginfo.c into risu.cRichard Henderson
The distinction between the two is artificial. Following patches will rearrange the functions involved to make it easier for dumping of the trace file. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220708154700.18682-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Split RES_MISMATCH for registers and memoryRichard Henderson
By remembering the specific comparison that failed, we do not have to try again when it comes time to report. This makes the mem_used flag redundant. Also, packet_mismatch is now redundant with RES_BAD_IO. This means that the only thing that report_match_status does is to report on register status, so rename to report_mismatch_reg. Also, we know there is a failure, so don't return a status from the report. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Simplify syncing with masterRichard Henderson
Do not pass status like RES_BAD_IO from apprentice to master. This means that when master reports i/o error that we know it came from master; the apprentice will report its own i/o error. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Always write for --masterRichard Henderson
For trace, master of course must write to the file we create. For sockets, we can report mismatches from either end. At present, we are reporting mismatches from master. Reverse that so that we report mismatches from the apprentice, just as we do for trace. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Pass non-OK result back through siglongjmpRichard Henderson
Rather than doing some work in the signal handler and some work outside, move all of the non-resume work outside. This works because we arranged for RES_OK to be 0, which is the normal return from sigsetjmp. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Unify i/o functions and use RisuResultRichard Henderson
Push the trace check down from the function calling the reginfo function down into the i/o function. This means we don't have to pass a function pointer. Return a RisuResult from the i/o functions. This fixes a minor bug in send_register_info (even before the conversion to RisuResult), which returned the write_fn result directly. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Add enum RisuResultRichard Henderson
Formalize the random set of numbers into an enum. Doing this makes it easy to see that one of the responses in recv_and_compare_register_info was inconsistent. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Add enum RisuOpRichard Henderson
Formalize the set of defines, plus -1, into an enum. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Make some risu.c symbols staticRichard Henderson
These are unused in other translation units. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Use EXIT_FAILURE, EXIT_SUCCESSRichard Henderson
Some of the time we exit via the return value from main. This can make it easier to tell what it is we're returning. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Adjust tracefile open for writeRichard Henderson
Truncate the new output file. Rely on umask to remove group+other file permissions, if desired. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Hoist trace file and socket openingRichard Henderson
We will want to share this code with --dump. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Unify master_fd and apprentice_fd to comm_fdRichard Henderson
Any one invocation cannot be both master and apprentice. Let's use only one variable for the file descriptor. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-18Use bool for tracing variablesRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708154700.18682-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01arm.risu: Add patterns for fp16 insnsPeter Maydell
Add patterns for the fp16 half-precision floating point extension. Where older pre-fp16 patterns used to include UNDEF encodings that now mean fp16, constrain them so that tests generated from those patterns will give the same results on CPUs both with and without fp16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-01arm.risu: Fix typo in VCVT_B_TT pattern namePeter Maydell
Fix typo in VCVT_B_TT pattern name. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2020-06-22arm.risu: Correct VLDR/VSTR U=0 patternsPeter Maydell
Correct the VLDR and VSTR patterns, which claimed to be setting U=0 but in fact left it identical to the U=1 pattern due to a cut-and-paste error. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2020-06-05arm.risu, thumb.risu: Add v8.2 DP and FHM insnsPeter Maydell
Add coverage for the v8.2 DP and v8.2 FHM insns in the Neon extension space. (We already had the v8.1 VQRDMLAH/VQRDLSH and the v8.3 VCADD/VCMLA, so this brings the risu coverage into line with what QEMU has implemented so far.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-02-24aarch64.risu: Add patterns for v8.3-RCPC and v8.4-RCPC insnsPeter Maydell
Add patterns for the new instructions in the v8.3-RCPC and v8.4-RCPC extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-17arm.risu: Avoid VTRN with Vd == VmPeter Maydell
The AArch32 VTRN instruction is specified to give an UNKNOWN result if Vd and Vm are the same register; avoid generating this in risu output, as we already do for VUZP and VZIP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190613143741.15128-1-peter.maydell@linaro.org
2019-06-13arm.risu: Add patterns for VFP<->gpreg transfersPeter Maydell
Add instruction patterns to cover the "transfer between Arm core and extension register" spaces (A7.8 and A7.9 in DDI0406C.c). We omit VMSR/VMRS because they might have side effects (for stores to special regs) or give results dependent on previous execution (for loads). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190606171046.2732-1-peter.maydell@linaro.org
2019-06-13risu: Include <sys/user.h> on ppc64Peter Maydell
To build the C parts of risu for ppc64le with recent glibc/kernel headers, we need to include sys/user.h to avoid a compile error, because sys/ucontext.h defines a struct which includes a pointer to 'struct pt_regs' but does not provide a definition of that struct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Sandipan Das <sandipan@linux.ibm.com> Message-id: 20190607132521.9637-1-peter.maydell@linaro.org
2019-06-07build-all-arches: include x86 triplets in the buildAlex Bennée
There are a couple of minor warts: - 32 bit x86 can be either i386-linux-gnu or i686-linux-gnu - skip looking for x86_64-linux-gnu-gcc in docker cross envs Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07risu_reginfo_i386: rework --xfeatures value parsingJan Bobek
Have the --xfeatures option accept "sse", "avx" and "avx512" in addition to a plain numerical value, purely for users' convenience. Don't fail silently when an incorrect value is specified, to avoid confusion. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07risu_reginfo_i386: replace xfeature constants with symbolic namesJan Bobek
The original code used "magic numbers", which made it unclear in some places. Include a reference to the Intel manual where the constants' meaning is discussed. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jan Bobek <jan.bobek@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-24 09:26:02 +0000