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AgeCommit message (Expand)Author
2020-02-24aarch64.risu: Add patterns for v8.3-RCPC and v8.4-RCPC insnsPeter Maydell
2018-03-01Add aa64 fcadd + fcmlaRichard Henderson
2018-03-01Add aa64 sqrdml[as]hRichard Henderson
2018-03-01aarch64.risu: add cryptographic extensions for v8.2Alex Bennée
2018-02-23aarch64.risu: update Floating-point data-processing (1 source)Alex Bennée
2018-02-23aarch64.risu: clean-up and annotate with groupsAlex Bennée
2017-11-21aarch64.risu: update AdvancedSIMD across lanesAlex Bennée
2017-11-21aarch64.risu: remove duplicate AdvSIMD scalar 2 reg misc blockAlex Bennée
2017-11-21aarch64.risu: remove duplicate AdvSIMD Scalar 3 same blockAlex Bennée
2017-11-21aarch64.risu: document naming conventionsAlex Bennée
2016-11-07Change mode directive of ARM risu filesJose Ricardo Ziviani
2014-11-26aarch64.risu: add EXT_RES caseAlex Bennée
2014-11-26aarch64.risu: add C3.6.12 two miscAlex Bennée
2014-11-26aarch64.risu: add generic C3.6.9 AdvSIMD scalar shift immAlex Bennée
2014-11-26aarch64.risu: complete C3.6.17 AdvSIMD two-reg miscAlex Bennée
2014-11-26aarch64.risu: complete C3.6.16 AdvSIMD three sameAlex Bennée
2014-11-26aarch64.risu: add generic C3.6.14 AdvSIMD shift imm patternAlex Bennée
2014-11-26aarch64.risu: complete C3.6.11 AdvSIMD 3 same patternsAlex Bennée
2014-11-26aarch64.risu: add commentary on C3.5.1 constraintsAlex Bennée
2014-11-26aarch64.risu: fix C6.3.12 constraints on BICivAlex Bennée
2014-11-26aarch64.risu: fix C3.4.5 encoding of hw field for moviAlex Bennée
2014-09-08aarch64.risu: fix ORRiClaudio Fontana
2014-09-08Add crypto extension patternsPeter Maydell
2014-04-25aarch64.risu: More patternsPeter Maydell
2014-04-25aarch64.risu: add C3.6.24 Floating-point conditional selectClaudio Fontana
2014-04-25aarch64.risu: add C3.6.23 Floating-point Conditional CompareClaudio Fontana
2014-04-25aarch64.risu: add C3.6.22 Floating-point compareClaudio Fontana
2014-04-25aarch64.risu: fix logical immediate constraintsClaudio Fontana
2014-04-25aarch64.risu: add C3.6.6 AdvSIMD modified immediateClaudio Fontana
2014-04-25aarch64.risu: add C3.6.30 Floating-point_integer conversionsClaudio Fontana
2014-04-25aarch64.risu: add C3.6.29 Floating-point_fixed-point conversionsClaudio Fontana
2014-04-25aarch64.risu: add C3.6.28 Floating-point immediateClaudio Fontana
2014-04-25aarch64.risu: add C3.6.27 Floating-point data-processing (3 source)Claudio Fontana
2014-04-25aarch64.risu: add C3.6.26 Floating-point data-processing (2 source)Claudio Fontana
2014-04-25aarch64.risu: add C3.6.25 Floating-point data-processing (1 source)Claudio Fontana
2014-04-25aarch64.risu: add ReservedValue encodingsClaudio Fontana
2014-04-25aarch64.risu: implement 3.6.1 to 3.6.5 FP/SIMD insnsClaudio Fontana
2014-04-25aarch64: complete FP/SIMD variants of instructionsClaudio Fontana
2014-04-25aarch64.risu: implement more SIMD/fp insns and variantsClaudio Fontana
2014-04-25aarch64.risu: add LD1, LD2, LD3, LD4 and R formsClaudio Fontana
2014-04-25aarch64.risu: add ST1,ST2,ST3,ST4 and SIMD/fp LDNP/STNPClaudio Fontana
2014-04-25aarch64.risu: update todo listClaudio Fontana
2014-04-25aarch64.risu: add flags-changing instructionsClaudio Fontana
2014-04-25aarch64.risu: remove commentClaudio Fontana
2014-04-25aarch64.risu: add load/store register pairClaudio Fontana
2014-04-25aarch64.risu: add ldr/str unsigned immediate offsetClaudio Fontana
2014-04-25aarch64.risu: add support for pre/post idx unscaled ldr/strClaudio Fontana
2014-04-25aarch64.risu: minor comment formatting changesClaudio Fontana
2014-04-25aarch64.risu: add ld/st reg (register offset)Claudio Fontana
2014-04-25aarch64.risu: reword wrong comment about load/stores limitationClaudio Fontana
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