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risu: random instruction sequence tester for userspace
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risu_reginfo_aarch64.c
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2018-07-02
risu_reginfo_aarch64: handle variable VQ
Alex Bennée
2018-07-02
risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatch
Alex Bennée
2018-07-02
risu_reginfo_aarch64: add support for copying SVE register state
Alex Bennée
2018-07-02
risu_reginfo_aarch64: left justify regnums and drop masks
Alex Bennée
2018-07-02
risu_reginfo: introduce reginfo_size()
Alex Bennée
2018-07-02
risu_reginfo_aarch64: unionify VFP regs
Alex Bennée
2018-07-02
risu_reginfo_aarch64: drop stray ;
Alex Bennée
2018-07-02
risu: add process_arch_opt
Richard Henderson
2018-07-02
risu: move optional args to each architecture
Alex Bennée
2018-07-02
risu_reginfo_aarch64: include signal.h for FPSIMD_MAGIC
Alex Bennée
2017-06-20
all: fix up code consistency
Alex Bennée
2014-04-25
risu_reginfo_aarch64: use Vn as register names for FP/SIMD
Claudio Fontana
2014-04-25
risu_reginfo_aarch64: add FP/SIMD state
Claudio Fontana
2014-04-25
risu_reginfo_aarch64: add NZCV flags to reginfo struct
Claudio Fontana
2014-04-25
risu_reginfo_aarch64: fix output formatting issue
Claudio Fontana
2014-04-25
aarch64: fix signal handling
Claudio Fontana
2014-04-25
risu_aarch64: provide risu initial implementation for aarch64
Claudio Fontana