###############################################################################
# Copyright (c) 2010 Linaro Limited
# All rights reserved. This program and the accompanying materials
# are made available under the terms of the Eclipse Public License v1.0
# which accompanies this distribution, and is available at
# http://www.eclipse.org/legal/epl-v10.html
#
# Contributors:
#     Peter Maydell (Linaro) - initial implementation
###############################################################################

# Input file for risugen defining Thumb instructions

.mode arm.thumb

#ADD T1 000 1100 rm:3 rn:3 rd:3
#ADD T3 11101 01 1000 s rn:4 0 imma:3 rd:4 immb:2 type:2 rm:4

#QDADD T1 11111 010 1000 rn:4 1111 rd:4 1001 rm:4
#QADD T1 11111 010 1000 rn:4 1111 rd:4 1000 rm:4
#QDSUB T1 11111 010 1000 rn:4 1111 rd:4 1011 rm:4
#QSUB T1 11111 010 1000 rn:4 1111 rd:4 1010 rm:4

PKH T1 11101 01 0110 0 rn:4 0 imma:3 rd:4 immb:2 tb 0 rm:4

# 32x32->64 but result is high word only
SMMLA T1 11111 0110 101 rn:4 ra:4 rd:4 000 r rm:4
SMMLS T1 11111 0110 110 rn:4 ra:4 rd:4 000 r rm:4
# Note that this doesn't overlap with SMMLA because of the implicit
# constraints on registers fields (ie not 13 or 15)
SMMUL T1 11111 0110 101 rn:4 1111 rd:4 000 r rm:4

# preload and memory hint space (in the byte and halfword
# load space, where Rt == 15).
# The constraint is to avoid UNPREDICTABLE space
HINTSPACE T1 111 1100 op1:2 0 z 1 y:4 1111 op2:6 any:6 { ($y == 15) || (($op1 & 1) != 0) || !((($op2 & 0x24) == 0x24) || (($op2 & 0x3c) == 0x38)) ; }

# VMLAL, VMLSL, VQDMLAL, VQDMLSL, VMULL, VQDMULL
# NB that enc T1 is actually VMLA/VMLS only, T2 is VMLAL/VMLSL only
VMLAL T2 111 u 1111 1 d sz:2 vn:4 vd:3 0 10 op 0 n 0 m 0 vm:4 { $sz != 3; }
# VQDMLAL and VQDMLSL (not scalar form)
VQDLAL T1 1110 1111 1 d sz:2 vn:4 vd:3 0 10 op 1 n 0 m 0 vm:4 { ($sz != 3) && ($sz != 0); }
# VMULL (excludes the polynomial case!)
VMULL T2 111 u 1111 1 d sz:2 vn:4 vd:3 0 11 0 0 n 0 m 0 vm:4 { ($sz != 3) && ($sz != 0); }
# VQDMULL (not scalar form)
VQDMULL T1 1110 1111 1 d sz:2 vn:4 vd:3 0 1101 n 0 m 0 vm:4 { ($sz != 3) && ($sz != 0); }


MOVS T2 000 00 00000 rm:3 rd:3

# saturating add/sub
UQADD16 T1 11111 010 1001 rn:4 1111 rd:4 0101 rm:4
UQADD8  T1 11111 010 1000 rn:4 1111 rd:4 0101 rm:4
UQSUB16 T1 11111 010 1101 rn:4 1111 rd:4 0101 rm:4
UQSUB8  T1 11111 010 1100 rn:4 1111 rd:4 0101 rm:4
# ditto, signed
QADD16 T1 11111 010 1001 rn:4 1111 rd:4 0001 rm:4
QADD8  T1 11111 010 1000 rn:4 1111 rd:4 0001 rm:4
QSUB16 T1 11111 010 1101 rn:4 1111 rd:4 0001 rm:4
QSUB8  T1 11111 010 1100 rn:4 1111 rd:4 0001 rm:4

# dual multiplies
SMLAD T1 11111 0110 010 rn:4 ra:4 rd:4 000 m rm:4
SMUAD T1 11111 0110 010 rn:4 1111 rd:4 000 m rm:4
SMLSD T1 11111 0110 100 rn:4 ra:4 rd:4 000 m rm:4
SMUSD T1 11111 0110 100 rn:4 1111 rd:4 000 m rm:4
SMLALD T1 11111 0111 100 rn:4 rdlo:4 rdhi:4 110 m rm:4 { $rdhi != $rdlo; }
SMLSLD T1 11111 0111 101 rn:4 rdlo:4 rdhi:4 110 m rm:4 { $rdhi != $rdlo; }

# Basic Thumb-2 data ops
# register ops
AND T1 010000 0000 rm:3 rd:3
AND T2 11101 01 0000 s rn:4 0 imm:3 rd:4 imm2:2 type:2 rm:4
BIC T1 010000 1110 rm:3 rd:3
BIC T2 11101 01 0001 s rn:4 0 imm:3 rd:4 imm2:2 type:2 rm:4

# divide (for A profile, A15 and above only)
SDIV T1 11111 011100 1 rn:4 1111 rd:4 1111 rm:4
UDIV T1 11111 011101 1 rn:4 1111 rd:4 1111 rm:4

##############################################################################
# Loads and stores
##############################################################################

# Not supported:
#  * PC-relative loads and stores (risu limitation)
#  * load/store exclusive (side effects too hard to test with risu)
#  * ldc/stc/ldc2/stc2 (risu doesn't know about copro registers)
# Not yet encoded in this file (but should be doable):
#  * load/store multiple
#  * ldrd/strd
#  * neon and VFP loads and stores

# from table A6-18:
# LDR (imm, thumb)
LDR_imm T1 01101 imm:5 rn:3 rt:3 \
   !memory { reg_plus_imm($rn, $imm << 2, $rt); }

# LDR_imm encoding T2 is sp-relative loads, not supported by risu

LDR_imm T3 11111 000 1101 rn:4 rt:4 imm:12 \
   !memory { reg_plus_imm($rn, $imm, $rt); }

# T4, W=0 case: P=0 UNDEF, P=1 U=1 is LDRT, so PUW=100 is only option (plain negative offset)
LDR_imm T4a 11111 000 0101 rn:4 rt:4 1 1 0 0 imm:8 \
   !memory { reg_minus_imm($rn, $imm, $rt); }
# T4, P=0 W=0 : UNDEF ; note that we mustn't have a !memory block for this
LDR_imm T4b 11111 000 0101 rn:4 rt:4 1 0 u 0 imm:8

# T4, W=1 case: rn == rt is unpredictable. We have to
# split out the various subcase of P and U because the
# addressing modes are different
# P=U=0 : post-indexed, negative
LDR_imm T4c 11111 000 0101 rn:4 rt:4 1 0 0 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg_minus_imm($rn, $imm, $rt); }
# P=0,U=1 : postindexed, positive
LDR_imm T4d 11111 000 0101 rn:4 rt:4 1 0 1 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg_plus_imm($rn, $imm, $rt); }
# P=1 : preindexed
LDR_imm T4e 11111 000 0101 rn:4 rt:4 1 1 u 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg($rn, $rt); }

# LDRT
LDRT T1 11111 000 0101 rn:4 rt:4 1110 imm:8 \
   !memory { reg_plus_imm($rn, $imm, $rt); }

# LDR (reg)
# The constraint that base and index registers be different
# isn't imposed by the architecture but by risugen.
LDR T1 0101 100 rm:3 rn:3 rt:3 \
   !constraints { $rm != $rn; } \
   !memory { reg_plus_reg($rn, $rm, $rt); }
LDR T2 11111 000 0101 rn:4 rt:4 0 00000 imm:2 rm:4 \
   !constraints { $rm != $rn; } \
   !memory { reg_plus_reg_shifted($rn, $rm, $imm, $rt); }

# LDR (literal)
# risugen doesn't support pc-relative loads/stores yet.

# A6-19
# LDRH (lit) -- pc-relative addressing not supported
# LDRH (imm, thumb)
LDRH_imm T1 10001 imm:5 rn:3 rt:3 \
   !memory { reg_plus_imm($rn, $imm << 2, $rt); }

LDRH_imm T2 11111 000 1011 rn:4 rt:4 imm:12 \
   !memory { reg_plus_imm($rn, $imm, $rt); }

# T3, W=0 case: P=0 UNDEF, P=1 U=1 is LDRHT, so PUW=100 is only option (plain negative offset)
LDRH_imm T3a 11111 000 0011 rn:4 rt:4 1 1 0 0 imm:8 \
   !memory { reg_minus_imm($rn, $imm, $rt); }
# T3, P=0 W=0 : UNDEF ; note that we mustn't have a !memory block for this
LDRH_imm T3b 11111 000 0011 rn:4 rt:4 1 0 u 0 imm:8

# T3, W=1 case: rn == rt is unpredictable. We have to
# split out the various subcase of P and U because the
# addressing modes are different
# P=U=0 : post-indexed, negative
LDRH_imm T3c 11111 000 0011 rn:4 rt:4 1 0 0 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg_minus_imm($rn, $imm, $rt); }
# P=0,U=1 : postindexed, positive
LDRH_imm T3d 11111 000 0011 rn:4 rt:4 1 0 1 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg_plus_imm($rn, $imm, $rt); }
# P=1 : preindexed
LDRH_imm T3e 11111 000 0011 rn:4 rt:4 1 1 u 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg($rn, $rt); }

# LDRHT
LDRHT T1 11111 000 0011 rn:4 rt:4 1110 imm:8 \
   !memory { reg_plus_imm($rn, $imm, $rt); }

# LDRH (reg)
# The constraint that base and index registers be different
# isn't imposed by the architecture but by risugen.
LDRH T1 0101 101 rm:3 rn:3 rt:3 \
   !constraints { $rm != $rn; } \
   !memory { reg_plus_reg($rn, $rm, $rt); }
LDRH T2 11111 000 0011 rn:4 rt:4 0 00000 imm:2 rm:4 \
   !constraints { $rm != $rn; } \
   !memory { reg_plus_reg_shifted($rn, $rm, $imm, $rt); }

# LDRSH (imm)
LDRSH_imm T1 11111 001 1011 rn:4 rt:4 imm:12 \
   !memory { reg_plus_imm($rn, $imm, $rt); }
# W=0 case: PUW=100 (others are UNDEF or LDRSHT)
LDRSH_imm T2a 11111 001 0011 rn:4 rt:4 1 1 0 0 imm:8 \
   !memory { reg_minus_imm($rn, $imm, $rt); }
# W=0 P=0 UNDEF case
LDRSH_imm T2b 11111 001 0011 rn:4 rt:4 1 0 u 0 imm:8

# T3, W=1 case: rn == rt is unpredictable. We have to
# split out the various subcase of P and U because the
# addressing modes are different
# P=U=0 : post-indexed, negative
LDRSH_imm T2c 11111 001 0011 rn:4 rt:4 1 0 0 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg_minus_imm($rn, $imm, $rt); }
# P=0,U=1 : postindexed, positive
LDRSH_imm T2d 11111 001 0011 rn:4 rt:4 1 0 1 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg_plus_imm($rn, $imm, $rt); }
# P=1 : preindexed
LDRSH_imm T2e 11111 001 0011 rn:4 rt:4 1 1 u 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg($rn, $rt); }

# LDRSHT
LDRSHT T1  11111 001 0011 rn:4 rt:4 1110 imm:8 \
   !memory { reg_plus_imm($rn, $imm, $rt); }

# LDRSH (reg)
LDRSH T1 0101 111 rm:3 rn:3 rt:3 \
   !constraints { $rm != $rn; } \
   !memory { reg_plus_reg($rn, $rm, $rt); }
LDRSH T2 11111 001 0011 rn:4 rt:4 0 00000 imm:2 rm:4 \
   !constraints { $rm != $rn; } \
   !memory { reg_plus_reg_shifted($rn, $rm, $imm, $rt); }

# A6-20
# LDRB (lit) -- pc-relative addressing not supported
# LDRB (imm, thumb)
LDRB_imm T1 01111 imm:5 rn:3 rt:3 \
   !memory { reg_plus_imm($rn, $imm << 2, $rt); }

LDRB_imm T2 11111 000 1001 rn:4 rt:4 imm:12 \
   !memory { reg_plus_imm($rn, $imm, $rt); }

# T3, W=0 case: P=0 UNDEF, P=1 U=1 is LDRBT, so PUW=100 is only option (plain negative offset)
LDRB_imm T3a 11111 000 0001 rn:4 rt:4 1 1 0 0 imm:8 \
   !memory { reg_minus_imm($rn, $imm, $rt); }
# T3, P=0 W=0 : UNDEF ; note that we mustn't have a !memory block for this
LDRB_imm T3b 11111 000 0001 rn:4 rt:4 1 0 u 0 imm:8

# T3, W=1 case: rn == rt is unpredictable. We have to
# split out the various subcase of P and U because the
# addressing modes are different
# P=U=0 : post-indexed, negative
LDRB_imm T3c 11111 000 0001 rn:4 rt:4 1 0 0 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg_minus_imm($rn, $imm, $rt); }
# P=0,U=1 : postindexed, positive
LDRB_imm T3d 11111 000 0001 rn:4 rt:4 1 0 1 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg_plus_imm($rn, $imm, $rt); }
# P=1 : preindexed
LDRB_imm T3e 11111 000 0001 rn:4 rt:4 1 1 u 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg($rn, $rt); }

# LDRBT
LDRBT T1 11111 000 0001 rn:4 rt:4 1110 imm:8 \
   !memory { reg_plus_imm($rn, $imm, $rt); }

# LDRB (reg)
# The constraint that base and index registers be different
# isn't imposed by the architecture but by risugen.
LDRB T1 0101 110 rm:3 rn:3 rt:3 \
   !constraints { $rm != $rn; } \
   !memory { reg_plus_reg($rn, $rm, $rt); }
LDRB T2 11111 0000 001 rn:4 rt:4 0 00000 imm:2 rm:4 \
   !constraints { $rm != $rn; } \
   !memory { reg_plus_reg_shifted($rn, $rm, $imm, $rt); }

# LDRSB (imm)
LDRSB_imm T1 11111 001 1001 rn:4 rt:4 imm:12 \
   !memory { reg_plus_imm($rn, $imm, $rt); }
# W=0 case: PUW=100 (others are UNDEF or LDRSBT)
LDRSB_imm T2a 11111 001 0001 rn:4 rt:4 1 1 0 0 imm:8 \
   !memory { reg_minus_imm($rn, $imm, $rt); }
# W=0 P=0 UNDEF case
LDRSB_imm T2b 11111 001 0001 rn:4 rt:4 1 0 u 0 imm:8

# T3, W=1 case: rn == rt is unpredictable. We have to
# split out the various subcase of P and U because the
# addressing modes are different
# P=U=0 : post-indexed, negative
LDRSB_imm T2c 11111 001 0001 rn:4 rt:4 1 0 0 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg_minus_imm($rn, $imm, $rt); }
# P=0,U=1 : postindexed, positive
LDRSB_imm T2d 11111 001 0001 rn:4 rt:4 1 0 1 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg_plus_imm($rn, $imm, $rt); }
# P=1 : preindexed
LDRSB_imm T2e 11111 001 0001 rn:4 rt:4 1 1 u 1 imm:8 \
   !constraints { $rn != $rt } \
   !memory { reg($rn, $rt); }

# LDRSBT
LDRSBT T1  11111 001 0001 rn:4 rt:4 1110 imm:8 \
   !memory { reg_plus_imm($rn, $imm, $rt); }

# LDRSB (reg)
LDRSB T1 0101 011 rm:3 rn:3 rt:3 \
   !constraints { $rm != $rn; } \
   !memory { reg_plus_reg($rn, $rm, $rt); }
LDRSB T2 11111 001 0001 rn:4 rt:4 0 00000 imm:2 rm:4 \
   !constraints { $rm != $rn; } \
   !memory { reg_plus_reg_shifted($rn, $rm, $imm, $rt); }

# A6-21 -- stores
# Note that constraints that we can't store the basereg
# are imposed by risu/risugen, not by the architecture.

# STRB (imm, thumb)
STRB_imm T1 01110 imm:5 rn:3 rt:3 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm << 2); }
STRB_imm T2 11111 000 1000 rn:4 rt:4 imm:12 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm); }
# PUW=110 is STRBT and PUW=0x0 is UNDEF, so W=0 means PUW=100
STRB_imm T3a 11111 000 0000 rn:4 rt:4 1 1 0 0 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_minus_imm($rn, $imm); }
# PUW=0x0 undef case
STRB_imm T3b 11111 000 0000 rn:4 rt:4 1 0 u 0 imm:8
# Writeback cases: rn==rt is unpredictable here
# P=U=0 : postindexed, negative
STRB_imm T3c 11111 000 0000 rn:4 rt:4 1 0 0 1 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_minus_imm($rn, $imm); }
# P=0,U=1 : postindexed, positive
STRB_imm T3d 11111 000 0000 rn:4 rt:4 1 0 1 1 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm); }
# P=1 : preindexed
STRB_imm T3e 11111 000 0000 rn:4 rt:4 1 1 u 1 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg($rn); }

# STRBT
STRBT T1 11111 000 0000 rn:4 rt:4 1110 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm, $rt); }

# STRB (reg)
STRB T1 0101 010 rm:3 rn:3 rt:3 \
   !constraints { $rn != $rt && $rn != $rm; } \
   !memory { reg_plus_reg($rn, $rm); }
# both the constraints here are risugen-imposed, not architectural
STRB T2 11111 000 0000 rn:4 rt:4 000000 imm:2 rm:4 \
   !constraints { $rn != $rt && $rm != $rn; } \
   !memory { reg_plus_reg_shifted($rn, $rm, $imm); }


# STRH (imm, thumb)
STRH_imm T1 10000 imm:5 rn:3 rt:3 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm << 2); }
STRH_imm T2 11111 000 1010 rn:4 rt:4 imm:12 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm); }
# PUW=110 is STRHT and PUW=0x0 is UNDEF, so W=0 means PUW=100
STRH_imm T3a 11111 000 0010 rn:4 rt:4 1 1 0 0 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_minus_imm($rn, $imm); }
# PUW=0x0 undef case
STRH_imm T3b 11111 000 0010 rn:4 rt:4 1 0 u 0 imm:8
# Writeback cases: rn==rt is unpredictable here
# P=U=0 : postindexed, negative
STRH_imm T3c 11111 000 0010 rn:4 rt:4 1 0 0 1 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_minus_imm($rn, $imm); }
# P=0,U=1 : postindexed, positive
STRH_imm T3d 11111 000 0010 rn:4 rt:4 1 0 1 1 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm); }
# P=1 : preindexed
STRH_imm T3e 11111 000 0010 rn:4 rt:4 1 1 u 1 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg($rn); }

# STRHT
STRHT T1 11111 000 0010 rn:4 rt:4 1110 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm, $rt); }

# STRH (reg)
STRH T1 0101 001 rm:3 rn:3 rt:3 \
   !constraints { $rn != $rt && $rn != $rm; } \
   !memory { reg_plus_reg($rn, $rm); }
# both the constraints here are risugen-imposed, not architectural
STRH T2 11111 000 0010 rn:4 rt:4 000000 imm:2 rm:4 \
   !constraints { $rn != $rt && $rm != $rn; } \
   !memory { reg_plus_reg_shifted($rn, $rm, $imm); }

# STR (imm, thumb)
STR_imm T1 01100 imm:5 rn:3 rt:3 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm << 2); }
# STR imm T2 is sp-relative
STR_imm T3 11111 000 1100 rn:4 rt:4 imm:12 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm); }
# PUW=110 is STRT and PUW=0x0 is UNDEF, so W=0 means PUW=100
STR_imm T4a 11111 000 0100 rn:4 rt:4 1 1 0 0 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_minus_imm($rn, $imm); }
# PUW=0x0 undef case
STR_imm T4b 11111 000 0100 rn:4 rt:4 1 0 u 0 imm:8
# Writeback cases: rn==rt is unpredictable here
# P=U=0 : postindexed, negative
STR_imm T4c 11111 000 0100 rn:4 rt:4 1 0 0 1 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_minus_imm($rn, $imm); }
# P=0,U=1 : postindexed, positive
STR_imm T4d 11111 000 0100 rn:4 rt:4 1 0 1 1 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm); }
# P=1 : preindexed
STR_imm T4e 11111 000 0100 rn:4 rt:4 1 1 u 1 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg($rn); }

# STRT
STRT T1 11111 000 0100 rn:4 rt:4 1110 imm:8 \
   !constraints { $rn != $rt; } \
   !memory { reg_plus_imm($rn, $imm, $rt); }

# STR (reg)
STR T1 0101 000 rm:3 rn:3 rt:3 \
   !constraints { $rn != $rt && $rn != $rm; } \
   !memory { reg_plus_reg($rn, $rm); }
# both the constraints here are risugen-imposed, not architectural
STR T2 11111 000 0100 rn:4 rt:4 000000 imm:2 rm:4 \
   !constraints { $rn != $rt && $rm != $rn; } \
   !memory { reg_plus_reg_shifted($rn, $rm, $imm); }

##############################################################################

# V8 only instructions
CRC32 T1 111 1101 011 0 c rn:4 1111 rd:4 10 sz:2 rm:4 !constraints { $sz != 3; }

#
# ARMv8.1 extensions
#
@v8_1_simd

VQRDMLAH    T1  111111110 d:1 size:2 vn:4 vd:4 1011 n:1 q:1 m:1 1 vm:4
VQRDMLAH_s  T1  111 q:1 11111 d:1 size:2 vn:4 vd:4 1110 n:1 1 m:1 0 vm:4

VQRDMLSH    T1  111111110 d:1 size:2 vn:4 vd:4 1100 n:1 q:1 m:1 1 vm:4
VQRDMLSH_s  T1  111 q:1 11111 d:1 size:2 vn:4 vd:4 1111 n:1 1 m:1 0 vm:4

#
# ARMv8.2 extensions
#
@v8_2_dp

VUDOT       A1 1111110 00 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 1 vm:4
VSDOT       A1 1111110 00 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 0 vm:4

VUDOT_s     A1 11111110 0 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 1 vm:4
VSDOT_s     A1 11111110 0 d:1 10 vn:4 vd:4 1101 n:1 q:1 m:1 0 vm:4

@v8_2_fhm

VFMAL       A1 1111110 00 d:1 10 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4
VFMSL       A1 1111110 01 d:1 10 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4
VFMAL_s     A1 11111110 0 d:1 00 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4
VFMSL_s     A1 11111110 1 d:1 00 vn:4 vd:4 1000 n:1 q:1 m:1 1 vm:4

#
# ARMv8.3 extensions
#
@v8_3_compnum

# Disable fp16 until qemu supports it.
VCADD       T1  1111110 rot:1 1 d:1 0 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \
!constraints { $s != 0; }

VCMLA       T1  1111110 rot:2 d:1 1 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \
!constraints { $s != 0; }
VCMLA_s     T1  11111110 s:1 d:1 rot:2 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \
!constraints { $s != 0; }