diff options
| author | Grant Likely <grant.likely@linaro.org> | 2015-03-02 12:51:17 +0000 |
|---|---|---|
| committer | Grant Likely <grant.likely@linaro.org> | 2015-03-02 12:51:17 +0000 |
| commit | 8eea08668455d5cb86fc2033e91882c9216d81f4 (patch) | |
| tree | c15b5caaeaee9218de40296ca9942017df44c6a9 | |
| parent | e7c36b3690719648d40464892e1eb813259c245b (diff) | |
Rework schematic to use dedicated components
The schematic was using generic pin rows for the 96board expansion and
cp2401 eval kit. Rework to use the new dedicated schematics and
footprints so that the schematic and PCB are easier to work with.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
| -rw-r--r-- | 96boards-uart-cache.lib | 177 | ||||
| -rw-r--r-- | 96boards-uart.kicad_pcb | 798 | ||||
| -rw-r--r-- | 96boards-uart.net | 142 | ||||
| -rw-r--r-- | 96boards-uart.pro | 79 | ||||
| -rw-r--r-- | 96boards-uart.sch | 269 |
5 files changed, 747 insertions, 718 deletions
diff --git a/96boards-uart-cache.lib b/96boards-uart-cache.lib index 9985412..7d21709 100644 --- a/96boards-uart-cache.lib +++ b/96boards-uart-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Tue 24 Feb 2015 21:35:01 GMT +EESchema-LIBRARY Version 2.3 Date: Mon 02 Mar 2015 11:34:39 GMT #encoding utf-8 # # +1.8V @@ -16,87 +16,83 @@ C 0 60 20 0 1 0 N ENDDRAW ENDDEF # -# CONN_20X2 +# 96BOARD_LS_EXPANSION # -DEF CONN_20X2 P 0 10 Y N 1 F N +DEF 96BOARD_LS_EXPANSION P 0 10 Y Y 1 F N F0 "P" 0 1050 60 H V C CNN -F1 "CONN_20X2" 0 0 50 V V C CNN +F1 "96BOARD_LS_EXPANSION" 0 -1050 50 H V C CNN F2 "~" 0 0 60 H V C CNN F3 "~" 0 0 60 H V C CNN DRAW -S -100 1000 100 -1000 0 1 0 N -X P1 1 -400 950 300 R 60 30 1 1 P I -X P2 2 400 950 300 L 60 30 1 1 P I -X P3 3 -400 850 300 R 60 30 1 1 P I -X P4 4 400 850 300 L 60 30 1 1 P I -X P5 5 -400 750 300 R 60 30 1 1 P I -X P6 6 400 750 300 L 60 30 1 1 P I -X P7 7 -400 650 300 R 60 30 1 1 P I -X P8 8 400 650 300 L 60 30 1 1 P I -X P9 9 -400 550 300 R 60 30 1 1 P I -X P10 10 400 550 300 L 60 30 1 1 P I -X P20 20 400 50 300 L 60 30 1 1 P I -X P30 30 400 -450 300 L 60 30 1 1 P I -X P40 40 400 -950 300 L 60 30 1 1 P I -X P11 11 -400 450 300 R 60 30 1 1 P I -X P21 21 -400 -50 300 R 60 30 1 1 P I -X P31 31 -400 -550 300 R 60 30 1 1 P I -X P12 12 400 450 300 L 60 30 1 1 P I -X P22 22 400 -50 300 L 60 30 1 1 P I -X P32 32 400 -550 300 L 60 30 1 1 P I -X P13 13 -400 350 300 R 60 30 1 1 P I -X P23 23 -400 -150 300 R 60 30 1 1 P I -X P33 33 -400 -650 300 R 60 30 1 1 P I -X P14 14 400 350 300 L 60 30 1 1 P I -X P24 24 400 -150 300 L 60 30 1 1 P I -X P34 34 400 -650 300 L 60 30 1 1 P I -X P15 15 -400 250 300 R 60 30 1 1 P I -X ~ 25 -400 -250 300 R 60 30 1 1 P I -X P35 35 -400 -750 300 R 60 30 1 1 P I -X P16 16 400 250 300 L 60 30 1 1 P I -X P26 26 400 -250 300 L 60 30 1 1 P I -X P36 36 400 -750 300 L 60 30 1 1 P I -X P17 17 -400 150 300 R 60 30 1 1 P I -X P27 27 -400 -350 300 R 60 30 1 1 P I -X P37 37 -400 -850 300 R 60 30 1 1 P I -X P18 18 400 150 300 L 60 30 1 1 P I -X P28 28 400 -350 300 L 60 30 1 1 P I -X P38 38 400 -850 300 L 60 30 1 1 P I -X P19 19 -400 50 300 R 60 30 1 1 P I -X P29 29 -400 -450 300 R 60 30 1 1 P I -X P39 39 -400 -950 300 R 60 30 1 1 P I +S -900 1000 850 -1000 0 1 0 N +X GND 1 -1200 950 300 R 60 60 1 1 P I +X GND 2 1150 950 300 L 60 60 1 1 P I +X UART0_CTS 3 -1200 850 300 R 60 60 1 1 P I +X PWR_BTN_N 4 1150 850 300 L 60 60 1 1 P I +X UART0_TXD 5 -1200 750 300 R 60 60 1 1 P I +X RST_BTN_N 6 1150 750 300 L 60 60 1 1 P I +X UART0_RXD 7 -1200 650 300 R 60 60 1 1 P I +X SPI0_SCLK 8 1150 650 300 L 60 60 1 1 P I +X UART0_RTS 9 -1200 550 300 R 60 60 1 1 P I +X SPI0_DIN 10 1150 550 300 L 60 60 1 1 P I +X PCM_DO 20 1150 50 300 L 60 60 1 1 P I +X GPIO-H 30 1150 -450 300 L 60 60 1 1 P I +X GND 40 1150 -950 300 L 60 60 1 1 P I +X UART1_TXD 11 -1200 450 300 R 60 60 1 1 P I +X I2C1_SDA 21 -1200 -50 300 R 60 60 1 1 P I +X GPIO-I 31 -1200 -550 300 R 60 60 1 1 P I +X SPI0_CS 12 1150 450 300 L 60 60 1 1 P I +X PCM_DI 22 1150 -50 300 L 60 60 1 1 P I +X GPIO-J 32 1150 -550 300 L 60 60 1 1 P I +X UART1_RXD 13 -1200 350 300 R 60 60 1 1 P I +X GPIO-A/WKUP 23 -1200 -150 300 R 60 60 1 1 P I +X GPIO-K 33 -1200 -650 300 R 60 60 1 1 P I +X SPI0_DOUT 14 1150 350 300 L 60 60 1 1 P I +X GPIO-B 24 1150 -150 300 L 60 60 1 1 P I +X GPIO-L 34 1150 -650 300 L 60 60 1 1 P I +X I2C0_SCL 15 -1200 250 300 R 60 60 1 1 P I +X GPIO-C 25 -1200 -250 300 R 60 60 1 1 P I +X +1.8V 35 -1200 -750 300 R 60 60 1 1 P I +X PCM_FS 16 1150 250 300 L 60 60 1 1 P I +X GPIO-D 26 1150 -250 300 L 60 60 1 1 P I +X SYS_DCIN 36 1150 -750 300 L 60 60 1 1 P I +X I2C0_SDA 17 -1200 150 300 R 60 60 1 1 P I +X GPIO-E 27 -1200 -350 300 R 60 60 1 1 P I +X +5V 37 -1200 -850 300 R 60 60 1 1 P I +X PCM_CLK 18 1150 150 300 L 60 60 1 1 P I +X GPIO-F 28 1150 -350 300 L 60 60 1 1 P I +X SYS_DCIN 38 1150 -850 300 L 60 60 1 1 P I +X I2C1_SCL 19 -1200 50 300 R 60 60 1 1 P I +X GPIO-G 29 -1200 -450 300 R 60 60 1 1 P I +X GND 39 -1200 -950 300 R 60 60 1 1 P I ENDDRAW ENDDEF # -# CONN_3 +# CP2104_MINI # -DEF CONN_3 K 0 40 Y N 1 F N -F0 "K" -50 0 50 V V C CNN -F1 "CONN_3" 50 0 40 V V C CNN +DEF CP2104_MINI P 0 40 Y Y 1 F N +F0 "P" 0 300 50 H V C CNN +F1 "CP2104_MINI" 0 -600 50 H V C CNN F2 "~" 0 0 60 H V C CNN F3 "~" 0 0 60 H V C CNN DRAW -S -100 150 100 -150 0 1 0 N -X P1 1 -350 100 250 R 60 60 1 1 P I -X PM 2 -350 0 250 R 60 60 1 1 P I -X P3 3 -350 -100 250 R 60 60 1 1 P I -ENDDRAW -ENDDEF -# -# CONN_5 -# -DEF CONN_5 P 0 40 Y Y 1 F N -F0 "P" -50 0 50 V V C CNN -F1 "CONN_5" 50 0 50 V V C CNN -F2 "~" 0 0 60 H V C CNN -F3 "~" 0 0 60 H V C CNN -DRAW -S -100 250 100 -250 0 1 0 f -X ~ 1 -400 200 300 R 60 60 1 1 P I -X ~ 2 -400 100 300 R 60 60 1 1 P I -X ~ 3 -400 0 300 R 60 60 1 1 P I -X ~ 4 -400 -100 300 R 60 60 1 1 P I -X ~ 5 -400 -200 300 R 60 60 1 1 P I +S -500 250 500 -550 0 1 0 f +X VIO 1 -800 200 300 R 60 60 1 1 P I +X VDD 2 -800 100 300 R 60 60 1 1 P I +X VREGIN 3 -800 0 300 R 60 60 1 1 P I +X GPIO.0_TXT 4 -800 -100 300 R 60 60 1 1 P I +X GPIO.1_RXT 5 -800 -200 300 R 60 60 1 1 P I +X GPIO.2 6 -800 -300 300 R 60 60 1 1 P I +X GPIO.3 7 -800 -400 300 R 60 60 1 1 P I +X /RESET 8 -800 -500 300 R 60 60 1 1 P I +X GND 9 800 200 300 L 60 60 1 1 P I +X TXD 10 800 100 300 L 60 60 1 1 P I +X RXD 11 800 0 300 L 60 60 1 1 P I +X RTS 12 800 -100 300 L 60 60 1 1 P I +X CTS 13 800 -200 300 L 60 60 1 1 P I +X VBUS 14 800 -300 300 L 60 60 1 1 P I +X /SUSPEND 15 800 -400 300 L 60 60 1 1 P I +X SUSPEND 16 800 -500 300 L 60 60 1 1 P I ENDDRAW ENDDEF # @@ -113,6 +109,27 @@ X GND 1 0 0 0 U 30 30 1 1 W N ENDDRAW ENDDEF # +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 40 V V C CNN +F1 "R" 7 1 40 V V C CNN +F2 "~" -70 0 30 V V C CNN +F3 "~" 0 0 30 H V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* + SM1206 +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# # SW_PUSH # DEF SW_PUSH SW 0 40 N N 1 F N @@ -128,17 +145,23 @@ X 2 2 300 0 200 L 60 60 0 1 P I ENDDRAW ENDDEF # -# VCC +# ZENER # -DEF VCC #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 100 30 H I C CNN -F1 "VCC" 0 100 30 H V C CNN +DEF ZENER D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "ZENER" 0 -100 40 H V C CNN F2 "~" 0 0 60 H V C CNN F3 "~" 0 0 60 H V C CNN +$FPLIST + D? + SO* + SM* +$ENDFPLIST DRAW -X VCC 1 0 0 0 U 20 20 0 0 W N -C 0 50 20 0 1 0 N -P 3 0 1 0 0 0 0 30 0 30 N +P 5 0 1 0 50 0 -50 50 -50 -50 50 0 50 0 F +P 5 0 1 8 70 50 50 30 50 -30 30 -50 30 -50 N +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P ENDDRAW ENDDEF # diff --git a/96boards-uart.kicad_pcb b/96boards-uart.kicad_pcb index 53b289d..41a5bde 100644 --- a/96boards-uart.kicad_pcb +++ b/96boards-uart.kicad_pcb @@ -1,14 +1,14 @@ (kicad_pcb (version 3) (host pcbnew "(22-Jun-2014 BZR 4027)-stable") (general - (links 19) - (no_connects 1) + (links 20) + (no_connects 0) (area 96.949999 90.449999 141.050001 122.050001) (thickness 1.6) (drawings 10) - (tracks 39) + (tracks 56) (zones 0) - (modules 7) + (modules 4) (nets 10) ) @@ -53,8 +53,8 @@ (mod_edge_width 0.15) (mod_text_size 1 1) (mod_text_width 0.15) - (pad_size 2.1 1.4) - (pad_drill 0) + (pad_size 1.397 1.397) + (pad_drill 0.8128) (pad_to_mask_clearance 0) (aux_axis_origin 97 108) (visible_elements FFFFFFFF) @@ -95,7 +95,7 @@ (net 6 /UART0_RXD_LV) (net 7 /UART0_TXD_LV) (net 8 GND) - (net 9 VCC) + (net 9 N-000023) (net_class Default "This is the default net class." (clearance 0.24) @@ -113,18 +113,18 @@ (add_net /UART0_RXD_LV) (add_net /UART0_TXD_LV) (add_net GND) - (add_net VCC) + (add_net N-000023) ) (module PIN_ARRAY_2MM_20X2 (layer F.Cu) (tedit 54EE0AB2) (tstamp 54E8C3B0) (at 119 112) (descr "Double rangee de contacts 2 x 12 pins") (tags CONN) - (path /54E6538C) + (path /54F0AFFF) (fp_text reference P1 (at 20 -4) (layer F.SilkS) (effects (font (size 1.016 1.016) (thickness 0.27432))) ) - (fp_text value CONN_20X2 (at 0 3.81) (layer F.SilkS) hide + (fp_text value 96BOARD_LS_EXPANSION (at 0 3.81) (layer F.SilkS) hide (effects (font (size 1.016 1.016) (thickness 0.2032))) ) (fp_line (start 21.5 3.25) (end -21.5 3.25) (layer F.SilkS) (width 0.3048)) @@ -179,6 +179,7 @@ ) (pad 23 thru_hole circle (at 3 1) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 9 N-000023) ) (pad 16 thru_hole circle (at -5 -1) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS) @@ -234,7 +235,6 @@ ) (pad 37 thru_hole circle (at 17 1) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS) - (net 9 VCC) ) (pad 3 thru_hole circle (at -17 1) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS) @@ -265,138 +265,10 @@ ) ) - (module SIL-5 (layer F.Cu) (tedit 54EE0AA6) (tstamp 54ECA58F) - (at 105.41 107.65) - (descr "Connecteur 5 pins") - (tags "CONN DEV") - (path /54EC9AA7) - (fp_text reference J5 (at -6.41 -2.65) (layer F.SilkS) - (effects (font (size 1.72974 1.08712) (thickness 0.3048))) - ) - (fp_text value CONN_5 (at 0 -2.54) (layer F.SilkS) hide - (effects (font (size 1.524 1.016) (thickness 0.3048))) - ) - (fp_line (start -7.62 1.27) (end -7.62 -1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start -7.62 -1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start 5.08 -1.27) (end 5.08 1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start 5.08 1.27) (end -7.62 1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start -5.08 1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048)) - (pad 1 thru_hole rect (at -6.35 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - (net 1 +1.8V) - ) - (pad 2 thru_hole circle (at -3.81 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - ) - (pad 3 thru_hole circle (at -1.27 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - ) - (pad 4 thru_hole circle (at 1.27 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - ) - (pad 5 thru_hole circle (at 3.81 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - ) - ) - - (module SIL-5 (layer F.Cu) (tedit 54EE0A9B) (tstamp 54ECA59D) - (at 105.41 92.41) - (descr "Connecteur 5 pins") - (tags "CONN DEV") - (path /54EC9AB4) - (fp_text reference J2 (at -6.41 2.59) (layer F.SilkS) - (effects (font (size 1.72974 1.08712) (thickness 0.3048))) - ) - (fp_text value CONN_5 (at 0 -2.54) (layer F.SilkS) hide - (effects (font (size 1.524 1.016) (thickness 0.3048))) - ) - (fp_line (start -7.62 1.27) (end -7.62 -1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start -7.62 -1.27) (end 5.08 -1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start 5.08 -1.27) (end 5.08 1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start 5.08 1.27) (end -7.62 1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start -5.08 1.27) (end -5.08 -1.27) (layer F.SilkS) (width 0.3048)) - (pad 1 thru_hole rect (at -6.35 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - (net 8 GND) - ) - (pad 2 thru_hole circle (at -3.81 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - (net 6 /UART0_RXD_LV) - ) - (pad 3 thru_hole circle (at -1.27 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - (net 7 /UART0_TXD_LV) - ) - (pad 4 thru_hole circle (at 1.27 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - (net 4 /UART0_CTS_LV) - ) - (pad 5 thru_hole circle (at 3.81 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - (net 5 /UART0_RTS_LV) - ) - ) - - (module SIL-3 (layer F.Cu) (tedit 54EE0AA9) (tstamp 54ECA5A9) - (at 114.3 107.65) - (descr "Connecteur 3 pins") - (tags "CONN DEV") - (path /54EC9ACC) - (fp_text reference J6 (at -2.3 -2.65) (layer F.SilkS) - (effects (font (size 1.7907 1.07696) (thickness 0.3048))) - ) - (fp_text value CONN_3 (at 0 -2.54) (layer F.SilkS) hide - (effects (font (size 1.524 1.016) (thickness 0.3048))) - ) - (fp_line (start -3.81 1.27) (end -3.81 -1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start -3.81 -1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.81 -1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.81 1.27) (end -3.81 1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.3048)) - (pad 1 thru_hole rect (at -2.54 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - (net 2 /PWR_BTN) - ) - (pad 2 thru_hole circle (at 0 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - (net 3 /RST_BTN) - ) - (pad 3 thru_hole circle (at 2.54 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - ) - ) - - (module SIL-3 (layer F.Cu) (tedit 54EE0AA1) (tstamp 54ECA5B5) - (at 114.3 92.41) - (descr "Connecteur 3 pins") - (tags "CONN DEV") - (path /54EC9AD9) - (fp_text reference J3 (at -2.3 2.59) (layer F.SilkS) - (effects (font (size 1.7907 1.07696) (thickness 0.3048))) - ) - (fp_text value CONN_3 (at 0 -2.54) (layer F.SilkS) hide - (effects (font (size 1.524 1.016) (thickness 0.3048))) - ) - (fp_line (start -3.81 1.27) (end -3.81 -1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start -3.81 -1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.81 -1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start 3.81 1.27) (end -3.81 1.27) (layer F.SilkS) (width 0.3048)) - (fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.3048)) - (pad 1 thru_hole rect (at -2.54 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - ) - (pad 2 thru_hole circle (at 0 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - ) - (pad 3 thru_hole circle (at 2.54 0) (size 1.397 1.397) (drill 0.8128) - (layers *.Cu *.Mask F.SilkS) - ) - ) - - (module SW_PUSH_SM (layer F.Cu) (tedit 54EE0D8C) (tstamp 54EE0D99) - (at 124 98.5 90) + (module SW_PUSH_SM (layer F.Cu) (tedit 54EE0CCF) (tstamp 54F1A9C9) + (at 124 98 90) (path /54EBBD3A) - (fp_text reference SW1-PWR (at 0 -4.5 90) (layer F.SilkS) + (fp_text reference SW1 (at 0 -4.5 90) (layer F.SilkS) (effects (font (size 1.016 1.016) (thickness 0.2032))) ) (fp_text value SW_PUSH (at 0 1.016 90) (layer F.SilkS) @@ -425,10 +297,10 @@ ) ) - (module SW_PUSH_SM (layer F.Cu) (tedit 54EE0D91) (tstamp 54EE0D12) - (at 136 98.5 90) + (module SW_PUSH_SM (layer F.Cu) (tedit 54F1AAC2) (tstamp 54F1A9D6) + (at 136 98 90) (path /54EBBD47) - (fp_text reference SW2-RST (at 0 -4.5 90) (layer F.SilkS) + (fp_text reference SW2 (at 0 -4.5 90) (layer F.SilkS) (effects (font (size 1.016 1.016) (thickness 0.2032))) ) (fp_text value SW_PUSH (at 0 1.016 90) (layer F.SilkS) @@ -457,6 +329,92 @@ ) ) + (module CP2104_MINI (layer F.Cu) (tedit 54F10340) (tstamp 54F1AA9D) + (at 108.5 100.5) + (descr "Connecteur 5 pins") + (tags "CONN DEV") + (path /54F0A1F1) + (fp_text reference P2 (at -8.89 0) (layer F.SilkS) + (effects (font (size 1.72974 1.08712) (thickness 0.3048))) + ) + (fp_text value CP2104_MINI (at 5.08 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.016) (thickness 0.254))) + ) + (fp_line (start -10.16 7.62) (end 10.16 7.62) (layer F.SilkS) (width 0.3048)) + (fp_line (start -10.16 5.08) (end 10.16 5.08) (layer F.SilkS) (width 0.3048)) + (fp_line (start -10.16 -8.89) (end 10.16 -8.89) (layer F.SilkS) (width 0.3048)) + (fp_line (start 5.08 7.62) (end 5.08 5.08) (layer F.SilkS) (width 0.3048)) + (fp_line (start 10.16 5.08) (end 10.16 7.62) (layer F.SilkS) (width 0.3048)) + (fp_line (start 2.54 7.62) (end 2.54 5.08) (layer F.SilkS) (width 0.3048)) + (fp_line (start 2.54 -6.35) (end 2.54 -8.89) (layer F.SilkS) (width 0.3048)) + (fp_line (start 10.16 -8.89) (end 10.16 -6.35) (layer F.SilkS) (width 0.3048)) + (fp_line (start 5.08 -6.35) (end 5.08 -8.89) (layer F.SilkS) (width 0.3048)) + (fp_line (start -7.62 -6.35) (end -7.62 -8.89) (layer F.SilkS) (width 0.3048)) + (fp_line (start 2.54 -8.89) (end 2.54 -6.35) (layer F.SilkS) (width 0.3048)) + (fp_line (start -10.16 -6.35) (end 10.16 -6.35) (layer F.SilkS) (width 0.3048)) + (fp_line (start -10.16 -6.35) (end -10.16 -8.89) (layer F.SilkS) (width 0.3048)) + (fp_line (start -10.16 7.62) (end -10.16 5.08) (layer F.SilkS) (width 0.3048)) + (fp_line (start 2.54 5.08) (end 2.54 7.62) (layer F.SilkS) (width 0.3048)) + (fp_line (start -7.62 7.62) (end -7.62 5.08) (layer F.SilkS) (width 0.3048)) + (pad 8 thru_hole circle (at 8.89 6.35) (size 1.397 1.397) (drill 0.8128) + (layers *.Cu *.Mask F.SilkS) + ) + (pad 7 thru_hole circle (at 6.35 6.35) (size 1.397 1.397) (drill 0.8128) + (layers *.Cu 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Netlist Version 1.1 created Tue 24 Feb 2015 15:48:28 GMT +# EESchema Netlist Version 1.1 created Mon 02 Mar 2015 10:31:51 GMT ( - ( /54E6538C $noname P1 CONN_20X2 {Lib=CONN_20X2} + ( /54EBBD3A $noname SW1 SW_PUSH {Lib=SW_PUSH} + ( 1 /PWR_BTN ) + ( 2 GND ) + ) + ( /54EBBD47 $noname SW2 SW_PUSH {Lib=SW_PUSH} + ( 1 /RST_BTN ) + ( 2 GND ) + ) + ( /54F0A1F1 CP2104_MINI P2 CP2104_MINI {Lib=CP2104_MINI} + ( 1 N-000025 ) + ( 2 N-000026 ) + ( 3 ? ) + ( 4 +1.8V ) + ( 5 N-000024 ) + ( 6 /PWR_BTN ) + ( 7 /RST_BTN ) + ( 8 ? ) + ( 9 GND ) + ( 10 /UART0_RXD_LV ) + ( 11 /UART0_TXD_LV ) + ( 12 /UART0_CTS_LV ) + ( 13 /UART0_RTS_LV ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ) + ( /54F0AFFF PIN_ARRAY_2MM_20X2 P1 96BOARD_LS_EXPANSION {Lib=96BOARD_LS_EXPANSION} ( 1 GND ) ( 2 GND ) ( 3 /UART0_CTS_LV ) @@ -23,7 +49,7 @@ ( 20 ? ) ( 21 ? ) ( 22 ? ) - ( 23 ? ) + ( 23 N-000024 ) ( 24 ? ) ( 25 ? ) ( 26 ? ) @@ -37,76 +63,78 @@ ( 34 ? ) ( 35 +1.8V ) ( 36 ? ) - ( 37 VCC ) + ( 37 ? ) ( 38 ? ) ( 39 GND ) ( 40 GND ) ) - ( /54EBBD3A $noname SW1 SW_PUSH {Lib=SW_PUSH} - ( 1 /PWR_BTN ) - ( 2 GND ) - ) - ( /54EBBD47 $noname SW2 SW_PUSH {Lib=SW_PUSH} - ( 1 /RST_BTN ) - ( 2 GND ) - ) - ( /54EC9AA7 $noname J5 CONN_5 {Lib=CONN_5} - ( 1 +1.8V ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ) - ( /54EC9AB4 $noname J2 CONN_5 {Lib=CONN_5} + ( /54F37856 SOD-123 D1 ZENER {Lib=ZENER} ( 1 GND ) - ( 2 /UART0_RXD_LV ) - ( 3 /UART0_TXD_LV ) - ( 4 /UART0_CTS_LV ) - ( 5 /UART0_RTS_LV ) - ) - ( /54EC9ACC $noname J6 CONN_3 {Lib=CONN_3} - ( 1 /PWR_BTN ) - ( 2 /RST_BTN ) - ( 3 ? ) + ( 2 N-000025 ) ) - ( /54EC9AD9 $noname J3 CONN_3 {Lib=CONN_3} - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) + ( /54F378F7 $noname R1 R {Lib=R} + ( 1 N-000025 ) + ( 2 N-000026 ) ) ) * +{ Allowed footprints by component: +$component D1 + D? + SO* + SM* +$endlist +$component R1 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$endfootprintlist +} { Pin List by Nets -Net 6 "GND" "GND" +Net 22 "GND" "GND" + D1 1 + SW2 2 + SW1 2 + P1 39 P1 40 + P2 9 P1 1 P1 2 - P1 39 - J2 1 - SW1 2 - SW2 2 -Net 7 "+1.8V" "+1.8V" - P1 35 - J5 1 -Net 28 "/UART0_TXD_LV" "UART0_TXD_LV" - J2 3 - P1 5 -Net 29 "/UART0_RXD_LV" "UART0_RXD_LV" - J2 2 - P1 7 -Net 31 "/UART0_CTS_LV" "UART0_CTS_LV" +Net 23 "/UART0_CTS_LV" "UART0_CTS_LV" P1 3 - J2 4 -Net 32 "/RST_BTN" "RST_BTN" - J6 2 - SW2 1 + P2 12 +Net 24 "" "" + P1 23 + P2 5 +Net 25 "" "" + R1 1 + P2 1 + D1 2 +Net 26 "" "" + P2 2 + R1 2 +Net 38 "/RST_BTN" "RST_BTN" P1 6 -Net 34 "/UART0_RTS_LV" "UART0_RTS_LV" - P1 9 - J2 5 -Net 35 "/PWR_BTN" "PWR_BTN" + SW2 1 + P2 7 +Net 39 "/PWR_BTN" "PWR_BTN" P1 4 + P2 6 SW1 1 - J6 1 +Net 40 "/UART0_TXD_LV" "UART0_TXD_LV" + P2 11 + P1 5 +Net 41 "/UART0_RXD_LV" "UART0_RXD_LV" + P2 10 + P1 7 +Net 42 "+1.8V" "+1.8V" + P1 35 + P2 4 +Net 43 "/UART0_RTS_LV" "UART0_RTS_LV" + P1 9 + P2 13 } #End diff --git a/96boards-uart.pro b/96boards-uart.pro index 9c7557f..bbb8ad1 100644 --- a/96boards-uart.pro +++ b/96boards-uart.pro @@ -1,4 +1,4 @@ -update=Mon 23 Feb 2015 14:54:49 GMT +update=Mon 02 Mar 2015 11:33:29 GMT version=1 last_client=eeschema [cvpcb] @@ -8,6 +8,44 @@ NetIExt=net EquName1=devcms [general] version=1 +[pcbnew] +version=1 +LastNetListRead=96boards-uart.net +UseCmpFile=1 +PadDrill=1.016000000000 +PadDrillOvalY=1.016000000000 +PadSizeH=1.524000000000 +PadSizeV=1.524000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[pcbnew/libraries] +LibDir= +LibName1=sockets +LibName2=connect +LibName3=discret +LibName4=pin_array +LibName5=divers +LibName6=smd_capacitors +LibName7=smd_resistors +LibName8=smd_crystal&oscillator +LibName9=smd_dil +LibName10=smd_transistors +LibName11=libcms +LibName12=display +LibName13=led +LibName14=dip_sockets +LibName15=pga_sockets +LibName16=valves +LibName17=96boards-uart [eeschema] version=1 LibDir= @@ -48,41 +86,4 @@ LibName28=atmel LibName29=contrib LibName30=valves LibName31=mosfet -[pcbnew] -version=1 -LastNetListRead=96boards-uart.net -UseCmpFile=1 -PadDrill=1.016000000000 -PadDrillOvalY=1.016000000000 -PadSizeH=1.524000000000 -PadSizeV=1.524000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[pcbnew/libraries] -LibDir= -LibName1=sockets -LibName2=connect -LibName3=discret -LibName4=pin_array -LibName5=divers -LibName6=smd_capacitors -LibName7=smd_resistors -LibName8=smd_crystal&oscillator -LibName9=smd_dil -LibName10=smd_transistors -LibName11=libcms -LibName12=display -LibName13=led -LibName14=dip_sockets -LibName15=pga_sockets -LibName16=valves -LibName17=96boards-uart +LibName32=96boards-uart diff --git a/96boards-uart.sch b/96boards-uart.sch index 0548b07..695c929 100644 --- a/96boards-uart.sch +++ b/96boards-uart.sch @@ -30,6 +30,7 @@ LIBS:atmel LIBS:contrib LIBS:valves LIBS:mosfet +LIBS:96boards-uart LIBS:96boards-uart-cache EELAYER 27 0 EELAYER END @@ -37,7 +38,7 @@ $Descr A4 11693 8268 encoding utf-8 Sheet 1 1 Title "" -Date "24 feb 2015" +Date "2 mar 2015" Rev "" Comp "" Comment1 "" @@ -46,10 +47,10 @@ Comment3 "" Comment4 "" $EndDescr $Comp -L GND #PWR5 +L GND #PWR4 U 1 1 54E654DB P 4900 3200 -F 0 "#PWR5" H 4900 3200 30 0001 C CNN +F 0 "#PWR4" H 4900 3200 30 0001 C CNN F 1 "GND" H 4900 3130 30 0001 C CNN F 2 "" H 4900 3200 60 0000 C CNN F 3 "" H 4900 3200 60 0000 C CNN @@ -57,48 +58,37 @@ F 3 "" H 4900 3200 60 0000 C CNN 1 0 0 -1 $EndComp Wire Wire Line - 3650 3300 3450 3300 -Text Label 2950 3500 0 60 ~ 0 + 2100 3300 1500 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