Add resister between 1.8V sense and 1.8V rail

Don't want to accidentally burn out the USB->UART chip by attempting to
drive 1.8V to ground.

Signed-off-by: Grant Likely <grant.likely@linaro.org>

5 files changed, 389 insertions, 294 deletions

diff --git a/96boards-uart-cache.lib b/96boards-uart-cache.lib
index 622ea8b..4e61878 100644
--- a/96boards-uart-cache.lib
+++ b/96boards-uart-cache.lib
@@ -1,4 +1,4 @@
-EESchema-LIBRARY Version 2.3  Date: Mon 02 Mar 2015 13:22:11 GMT
+EESchema-LIBRARY Version 2.3  Date: Mon 09 Mar 2015 15:58:31 GMT
 #encoding utf-8
 #
 # +1.8V
diff --git a/96boards-uart.cmp b/96boards-uart.cmp
index 07e2a03..13a48e8 100644
--- a/96boards-uart.cmp
+++ b/96boards-uart.cmp
@@ -1,4 +1,4 @@
-Cmp-Mod V01 Created by CvPcb (22-Jun-2014 BZR 4027)-stable date = Mon 02 Mar 2015 22:25:58 GMT
+Cmp-Mod V01 Created by CvPcb (22-Jun-2014 BZR 4027)-stable date = Mon 16 Mar 2015 12:59:11 GMT
 
 BeginCmp
 TimeStamp = /54F37856;
@@ -29,6 +29,13 @@ IdModule  = SM0402_r;
 EndCmp
 
 BeginCmp
+TimeStamp = /54FDBF43;
+Reference = R2;
+ValeurCmp = 10K;
+IdModule  = SM0402_r;
+EndCmp
+
+BeginCmp
 TimeStamp = /54EBBD3A;
 Reference = SW1;
 ValeurCmp = SW_PUSH;
diff --git a/96boards-uart.kicad_pcb b/96boards-uart.kicad_pcb
index 3f13c4e..6e30619 100644
--- a/96boards-uart.kicad_pcb
+++ b/96boards-uart.kicad_pcb
@@ -1,15 +1,15 @@
 (kicad_pcb (version 3) (host pcbnew "(22-Jun-2014 BZR 4027)-stable")
 
   (general
-    (links 24)
+    (links 25)
     (no_connects 0)
     (area 96.949999 90.449999 141.050001 122.050001)
     (thickness 1.6)
     (drawings 18)
-    (tracks 63)
+    (tracks 67)
     (zones 0)
-    (modules 6)
-    (nets 12)
+    (modules 7)
+    (nets 13)
   )
 
   (page A3)
@@ -88,16 +88,17 @@
 
   (net 0 "")
   (net 1 +1.8V)
-  (net 2 /PWR_BTN)
-  (net 3 /RST_BTN)
-  (net 4 /UART0_CTS_LV)
-  (net 5 /UART0_RTS_LV)
-  (net 6 /UART0_RXD_LV)
-  (net 7 /UART0_TXD_LV)
-  (net 8 GND)
-  (net 9 N-000006)
-  (net 10 VDD)
-  (net 11 VIO)
+  (net 2 /1_8V_SENSE)
+  (net 3 /PWR_BTN)
+  (net 4 /RST_BTN)
+  (net 5 /UART0_CTS_LV)
+  (net 6 /UART0_RTS_LV)
+  (net 7 /UART0_RXD_LV)
+  (net 8 /UART0_TXD_LV)
+  (net 9 GND)
+  (net 10 N-000006)
+  (net 11 VDD)
+  (net 12 VIO)
 
   (net_class Default "This is the default net class."
     (clearance 0.24)
@@ -108,6 +109,7 @@
     (uvia_drill 0.127)
     (add_net "")
     (add_net +1.8V)
+    (add_net /1_8V_SENSE)
     (add_net /PWR_BTN)
     (add_net /RST_BTN)
     (add_net /UART0_CTS_LV)
@@ -126,7 +128,7 @@
     (fp_text reference SW1 (at -2.25 -4.5 90) (layer F.SilkS)
       (effects (font (size 1.016 1.016) (thickness 0.2032)))
     )
-    (fp_text value PWR (at 2.25 -4.5 90) (layer F.SilkS)
+    (fp_text value SW_PUSH (at 2.25 -4.5 90) (layer F.SilkS)
       (effects (font (size 1.016 1.016) (thickness 0.2032)))
     )
     (fp_circle (center 0 0) (end 0 -2.54) (layer F.SilkS) (width 0.127))
@@ -136,19 +138,19 @@
     (fp_line (start -3.81 -3.81) (end -3.81 3.81) (layer F.SilkS) (width 0.127))
     (pad 1 smd rect (at 4.55 -2.25 90) (size 2.1 1.4)
       (layers F.Cu F.Paste F.Mask)
-      (net 2 /PWR_BTN)
+      (net 3 /PWR_BTN)
     )
     (pad 2 smd rect (at 4.55 2.25 90) (size 2.1 1.4)
       (layers F.Cu F.Paste F.Mask)
-      (net 8 GND)
+      (net 9 GND)
     )
     (pad 1 smd rect (at -4.55 -2.25 90) (size 2.1 1.4)
       (layers F.Cu F.Paste F.Mask)
-      (net 2 /PWR_BTN)
+      (net 3 /PWR_BTN)
     )
     (pad 2 smd rect (at -4.55 2.25 90) (size 2.1 1.4)
       (layers F.Cu F.Paste F.Mask)
-      (net 8 GND)
+      (net 9 GND)
     )
   )
 
@@ -158,7 +160,7 @@
     (fp_text reference SW2 (at -2.25 -4.5 90) (layer F.SilkS)
       (effects (font (size 1.016 1.016) (thickness 0.2032)))
     )
-    (fp_text value RST (at 2.5 -4.5 90) (layer F.SilkS)
+    (fp_text value SW_PUSH (at 2.5 -4.5 90) (layer F.SilkS)
       (effects (font (size 1.016 1.016) (thickness 0.2032)))
     )
     (fp_circle (center 0 0) (end 0 -2.54) (layer F.SilkS) (width 0.127))
@@ -168,19 +170,19 @@
     (fp_line (start -3.81 -3.81) (end -3.81 3.81) (layer F.SilkS) (width 0.127))
     (pad 1 smd rect (at 4.55 -2.25 90) (size 2.1 1.4)
       (layers F.Cu F.Paste F.Mask)
-      (net 3 /RST_BTN)
+      (net 4 /RST_BTN)
     )
     (pad 2 smd rect (at 4.55 2.25 90) (size 2.1 1.4)
       (layers F.Cu F.Paste F.Mask)
-      (net 8 GND)
+      (net 9 GND)
     )
     (pad 1 smd rect (at -4.55 -2.25 90) (size 2.1 1.4)
       (layers F.Cu F.Paste F.Mask)
-      (net 3 /RST_BTN)
+      (net 4 /RST_BTN)
     )
     (pad 2 smd rect (at -4.55 2.25 90) (size 2.1 1.4)
       (layers F.Cu F.Paste F.Mask)
-      (net 8 GND)
+      (net 9 GND)
     )
   )
 
@@ -216,11 +218,11 @@
     )
     (pad 7 thru_hole circle (at 6.35 6.35) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
-      (net 3 /RST_BTN)
+      (net 4 /RST_BTN)
     )
     (pad 6 thru_hole rect (at 3.81 6.35) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
-      (net 2 /PWR_BTN)
+      (net 3 /PWR_BTN)
     )
     (pad 14 thru_hole rect (at 3.81 -7.62) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
@@ -233,42 +235,42 @@
     )
     (pad 13 thru_hole circle (at 1.27 -7.62) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
-      (net 5 /UART0_RTS_LV)
+      (net 6 /UART0_RTS_LV)
     )
     (pad 12 thru_hole circle (at -1.27 -7.62) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
-      (net 4 /UART0_CTS_LV)
+      (net 5 /UART0_CTS_LV)
     )
     (pad 11 thru_hole circle (at -3.81 -7.62) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
-      (net 7 /UART0_TXD_LV)
+      (net 8 /UART0_TXD_LV)
     )
     (pad 10 thru_hole circle (at -6.35 -7.62) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
-      (net 6 /UART0_RXD_LV)
+      (net 7 /UART0_RXD_LV)
     )
     (pad 9 thru_hole rect (at -8.89 -7.62) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
-      (net 8 GND)
+      (net 9 GND)
     )
     (pad 1 thru_hole rect (at -8.89 6.35) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
-      (net 11 VIO)
+      (net 12 VIO)
     )
     (pad 2 thru_hole circle (at -6.35 6.35) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
-      (net 10 VDD)
+      (net 11 VDD)
     )
     (pad 3 thru_hole circle (at -3.81 6.35) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
     )
     (pad 4 thru_hole circle (at -1.27 6.35) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
-      (net 1 +1.8V)
+      (net 2 /1_8V_SENSE)
     )
     (pad 5 thru_hole circle (at 1.27 6.35) (size 1.397 1.397) (drill 0.8128)
       (layers *.Cu *.Mask F.SilkS)
-      (net 9 N-000006)
+      (net 10 N-000006)
     )
   )
 
@@ -288,11 +290,11 @@
     (fp_line (start -1.27 1.27) (end -1.27 -1.27) (layer F.SilkS) (width 0.15))
     (pad 1 smd rect (at -1.635 0 270) (size 0.91 1.22)
       (layers F.Cu F.Paste F.Mask)
-      (net 8 GND)
+      (net 9 GND)
     )
     (pad 2 smd rect (at 1.635 0 270) (size 0.91 1.22)
       (layers F.Cu F.Paste F.Mask)
-      (net 11 VIO)
+      (net 12 VIO)
     )
   )
 
@@ -314,11 +316,11 @@
     (fp_line (start 0.762 0.381) (end 0.254 0.381) (layer F.SilkS) (width 0.07112))
     (pad 1 smd rect (at -0.44958 0) (size 0.39878 0.59944)
       (layers F.Cu F.Paste F.Mask)
-      (net 11 VIO)
+      (net 12 VIO)
     )
     (pad 2 smd rect (at 0.44958 0) (size 0.39878 0.59944)
       (layers F.Cu F.Paste F.Mask)
-      (net 10 VDD)
+      (net 11 VDD)
     )
     (model smd/resistors/R0402.wrl
       (at (xyz 0 0 0))
@@ -532,25 +534,25 @@
     (fp_line (start -21.5 -3.25) (end -21.5 3.25) (layer F.SilkS) (width 0.3048))
     (pad 1 thru_hole rect (at -19 1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
-      (net 8 GND)
+      (net 9 GND)
     )
     (pad 2 thru_hole circle (at -19 -1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
-      (net 8 GND)
+      (net 9 GND)
     )
     (pad 11 thru_hole circle (at -9 1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
     )
     (pad 4 thru_hole circle (at -17 -1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
-      (net 2 /PWR_BTN)
+      (net 3 /PWR_BTN)
     )
     (pad 13 thru_hole circle (at -7 1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
     )
     (pad 6 thru_hole circle (at -15 -1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
-      (net 3 /RST_BTN)
+      (net 4 /RST_BTN)
     )
     (pad 15 thru_hole circle (at -5 1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
@@ -578,7 +580,7 @@
     )
     (pad 23 thru_hole circle (at 3 1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
-      (net 9 N-000006)
+      (net 10 N-000006)
     )
     (pad 16 thru_hole circle (at -5 -1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
@@ -637,27 +639,27 @@
     )
     (pad 3 thru_hole circle (at -17 1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
-      (net 4 /UART0_CTS_LV)
+      (net 5 /UART0_CTS_LV)
     )
     (pad 5 thru_hole circle (at -15 1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
-      (net 7 /UART0_TXD_LV)
+      (net 8 /UART0_TXD_LV)
     )
     (pad 7 thru_hole circle (at -13 1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
-      (net 6 /UART0_RXD_LV)
+      (net 7 /UART0_RXD_LV)
     )
     (pad 9 thru_hole circle (at -11 1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
-      (net 5 /UART0_RTS_LV)
+      (net 6 /UART0_RTS_LV)
     )
     (pad 39 thru_hole circle (at 19 1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
-      (net 8 GND)
+      (net 9 GND)
     )
     (pad 40 thru_hole circle (at 19 -1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
-      (net 8 GND)
+      (net 9 GND)
     )
     (pad 30 thru_hole circle (at 9 -1) (size 1.2 1.2) (drill 0.8)
       (layers *.Cu *.Mask F.SilkS)
@@ -669,6 +671,37 @@
     )
   )
 
+  (module SM0402_r (layer F.Cu) (tedit 5141C458) (tstamp 5506D3B5)
+    (at 110.5 103.25 180)
+    (path /54FDBF43)
+    (attr smd)
+    (fp_text reference R2 (at 0 0 180) (layer F.SilkS)
+      (effects (font (size 0.35052 0.3048) (thickness 0.07112)))
+    )
+    (fp_text value 10K (at 0.09906 0 180) (layer F.SilkS) hide
+      (effects (font (size 0.35052 0.3048) (thickness 0.07112)))
+    )
+    (fp_line (start -0.254 -0.381) (end -0.762 -0.381) (layer F.SilkS) (width 0.07112))
+    (fp_line (start -0.762 -0.381) (end -0.762 0.381) (layer F.SilkS) (width 0.07112))
+    (fp_line (start -0.762 0.381) (end -0.254 0.381) (layer F.SilkS) (width 0.07112))
+    (fp_line (start 0.254 -0.381) (end 0.762 -0.381) (layer F.SilkS) (width 0.07112))
+    (fp_line (start 0.762 -0.381) (end 0.762 0.381) (layer F.SilkS) (width 0.07112))
+    (fp_line (start 0.762 0.381) (end 0.254 0.381) (layer F.SilkS) (width 0.07112))
+    (pad 1 smd rect (at -0.44958 0 180) (size 0.39878 0.59944)
+      (layers F.Cu F.Paste F.Mask)
+      (net 1 +1.8V)
+    )
+    (pad 2 smd rect (at 0.44958 0 180) (size 0.39878 0.59944)
+      (layers F.Cu F.Paste F.Mask)
+      (net 2 /1_8V_SENSE)
+    )
+    (model smd/resistors/R0402.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 0.27 0.27 0.27))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
   (gr_text RST (at 114.808 105.156) (layer F.SilkS)
     (effects (font (size 0.5 0.5) (thickness 0.1)))
   )
@@ -714,71 +747,75 @@
   (gr_line (start 141 122) (end 141 121.5) (angle 90) (layer Edge.Cuts) (width 0.1))
   (gr_line (start 97 115.5) (end 141 115.5) (angle 90) (layer Edge.Cuts) (width 0.1))
 
-  (segment (start 107.23 106.85) (end 107.23 109.77) (width 0.254) (layer B.Cu) (net 1))
-  (segment (start 133 114) (end 134 113) (width 0.254) (layer B.Cu) (net 1) (tstamp 54F32685))
-  (segment (start 107.5 114) (end 133 114) (width 0.254) (layer B.Cu) (net 1) (tstamp 54F32681))
-  (segment (start 107 113.5) (end 107.5 114) (width 0.254) (layer B.Cu) (net 1) (tstamp 54F32680))
-  (segment (start 107 110) (end 107 113.5) (width 0.254) (layer B.Cu) (net 1) (tstamp 54F3267E))
-  (segment (start 107.23 109.77) (end 107 110) (width 0.254) (layer B.Cu) (net 1) (tstamp 54F3267B))
-  (segment (start 121.75 93.45) (end 121.75 102.55) (width 0.254) (layer F.Cu) (net 2))
-  (segment (start 112.31 106.85) (end 112.65 106.85) (width 0.254) (layer F.Cu) (net 2))
-  (segment (start 119.8 104.5) (end 121.75 102.55) (width 0.254) (layer F.Cu) (net 2) (tstamp 54F32503))
-  (segment (start 115 104.5) (end 119.8 104.5) (width 0.254) (layer F.Cu) (net 2) (tstamp 54F32501))
-  (segment (start 112.65 106.85) (end 115 104.5) (width 0.254) (layer F.Cu) (net 2) (tstamp 54F324F8))
-  (segment (start 102 111) (end 104.5 108.5) (width 0.254) (layer F.Cu) (net 2))
-  (segment (start 110.66 108.5) (end 112.31 106.85) (width 0.254) (layer F.Cu) (net 2) (tstamp 54F324F3))
-  (segment (start 104.5 108.5) (end 110.66 108.5) (width 0.254) (layer F.Cu) (net 2) (tstamp 54F324EE))
-  (segment (start 133.75 102.55) (end 133.75 93.45) (width 0.254) (layer F.Cu) (net 3))
-  (segment (start 130.8 105.5) (end 133.75 102.55) (width 0.254) (layer F.Cu) (net 3) (tstamp 54F32552))
-  (segment (start 116 105.5) (end 130.8 105.5) (width 0.254) (layer F.Cu) (net 3) (tstamp 54F3254E))
-  (segment (start 104 111) (end 105.5 109.5) (width 0.254) (layer F.Cu) (net 3))
-  (segment (start 105.5 109.5) (end 112.2 109.5) (width 0.254) (layer F.Cu) (net 3) (tstamp 54F32536))
-  (segment (start 114.85 106.85) (end 114.85 106.65) (width 0.254) (layer F.Cu) (net 3))
-  (segment (start 114.85 106.65) (end 116 105.5) (width 0.254) (layer F.Cu) (net 3) (tstamp 54F32542))
-  (segment (start 112.2 109.5) (end 114.85 106.85) (width 0.254) (layer F.Cu) (net 3) (tstamp 54F3253B))
-  (segment (start 102 113) (end 101 112) (width 0.254) (layer F.Cu) (net 4))
-  (segment (start 101 112) (end 101 110.5) (width 0.254) (layer F.Cu) (net 4) (tstamp 54F32449))
-  (segment (start 101 110.5) (end 103.5 108) (width 0.254) (layer F.Cu) (net 4) (tstamp 54F3244B))
-  (segment (start 103.5 108) (end 103.5 106.5) (width 0.254) (layer F.Cu) (net 4) (tstamp 54F32454))
-  (segment (start 103.5 106.5) (end 107.23 102.77) (width 0.254) (layer F.Cu) (net 4) (tstamp 54F32456))
-  (segment (start 107.23 102.77) (end 107.23 92.88) (width 0.254) (layer F.Cu) (net 4) (tstamp 54F3245A))
-  (segment (start 108 113) (end 109 112) (width 0.254) (layer B.Cu) (net 5))
-  (segment (start 108.5 94.15) (end 109.77 92.88) (width 0.254) (layer B.Cu) (net 5) (tstamp 54F32672))
-  (segment (start 108.5 109) (end 108.5 94.15) (width 0.254) (layer B.Cu) (net 5) (tstamp 54F32670))
-  (segment (start 109 109.5) (end 108.5 109) (width 0.254) (layer B.Cu) (net 5) (tstamp 54F3266E))
-  (segment (start 109 112) (end 109 109.5) (width 0.254) (layer B.Cu) (net 5) (tstamp 54F3266D))
-  (segment (start 106 113) (end 105.5 113) (width 0.254) (layer B.Cu) (net 6))
-  (segment (start 102.15 103.15) (end 102.15 92.88) (width 0.254) (layer B.Cu) (net 6) (tstamp 54F32656))
-  (segment (start 103.5 104.5) (end 102.15 103.15) (width 0.254) (layer B.Cu) (net 6) (tstamp 54F3264F))
-  (segment (start 103.5 108.5) (end 103.5 104.5) (width 0.254) (layer B.Cu) (net 6) (tstamp 54F3264C))
-  (segment (start 103 109) (end 103.5 108.5) (width 0.254) (layer B.Cu) (net 6) (tstamp 54F32649))
-  (segment (start 103 113.5) (end 103 109) (width 0.254) (layer B.Cu) (net 6) (tstamp 54F32646))
-  (segment (start 103.5 114) (end 103 113.5) (width 0.254) (layer B.Cu) (net 6) (tstamp 54F32644))
-  (segment (start 104.5 114) (end 103.5 114) (width 0.254) (layer B.Cu) (net 6) (tstamp 54F32642))
-  (segment (start 105.5 113) (end 104.5 114) (width 0.254) (layer B.Cu) (net 6) (tstamp 54F3263F))
-  (segment (start 105.25 109.25) (end 106 108.5) (width 0.254) (layer B.Cu) (net 7))
-  (segment (start 104.69 103.69) (end 104.69 92.88) (width 0.254) (layer B.Cu) (net 7) (tstamp 54F32492))
-  (segment (start 106 105) (end 104.69 103.69) (width 0.254) (layer B.Cu) (net 7) (tstamp 54F3248F))
-  (segment (start 106 108.5) (end 106 105) (width 0.254) (layer B.Cu) (net 7) (tstamp 54F3248E))
-  (segment (start 104 113) (end 105 112) (width 0.254) (layer B.Cu) (net 7))
-  (segment (start 105 109.5) (end 105.25 109.25) (width 0.254) (layer B.Cu) (net 7) (tstamp 54EE0E4D))
-  (segment (start 105.25 109.25) (end 105.5 109) (width 0.254) (layer B.Cu) (net 7) (tstamp 54F3248C))
-  (segment (start 105 112) (end 105 109.5) (width 0.254) (layer B.Cu) (net 7) (tstamp 54EE0E4C))
-  (segment (start 109.77 106.85) (end 109.77 109.27) (width 0.254) (layer B.Cu) (net 9))
-  (segment (start 121 112) (end 122 113) (width 0.254) (layer B.Cu) (net 9) (tstamp 54F3276F))
-  (segment (start 121 110.5) (end 121 112) (width 0.254) (layer B.Cu) (net 9) (tstamp 54F3276E))
-  (segment (start 120.5 110) (end 121 110.5) (width 0.254) (layer B.Cu) (net 9) (tstamp 54F3276D))
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-  (zone (net 8) (net_name GND) (layer B.Cu) (tstamp 54EE0E99) (hatch edge 0.508)
+  (zone (net 9) (net_name GND) (layer B.Cu) (tstamp 54EE0E99) (hatch edge 0.508)
     (connect_pads (clearance 0.508))
     (min_thickness 0.254)
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@@ -1055,17 +1105,28 @@
         (xy 101.138013 113.960168) (xy 101.160177 113.906789) (xy 101.299515 114.046371) (xy 101.753266 114.234785) (xy 102.244579 114.235214)
         (xy 102.536828 114.114458) (xy 102.961184 114.538815) (xy 102.961185 114.538815) (xy 103.208395 114.703996) (xy 103.499999 114.761999)
         (xy 103.5 114.762) (xy 104.5 114.762) (xy 104.5 114.761999) (xy 104.791604 114.703996) (xy 104.791605 114.703996)
-        (xy 105.038815 114.538815) (xy 105.463264 114.114365) (xy 105.753266 114.234785) (xy 106.244579 114.235214) (xy 106.536828 114.114458)
-        (xy 106.961184 114.538815) (xy 106.961185 114.538815) (xy 107.208395 114.703996) (xy 107.499999 114.761999) (xy 107.5 114.762)
-        (xy 133 114.762) (xy 133 114.761999) (xy 133.291604 114.703996) (xy 133.291605 114.703996) (xy 133.538815 114.538815)
-        (xy 133.842767 114.234863) (xy 134.244579 114.235214) (xy 134.698657 114.047592) (xy 135.000221 113.746554) (xy 135.299515 114.046371)
-        (xy 135.753266 114.234785) (xy 136.244579 114.235214) (xy 136.698657 114.047592) (xy 137.046371 113.700485) (xy 137.060571 113.666285)
-        (xy 137.137265 113.68313) (xy 137.820395 113) (xy 137.820395 113.35921) (xy 137.31687 113.862735) (xy 137.366383 114.088164)
-        (xy 137.831036 114.247807) (xy 138.321413 114.217482) (xy 138.633617 114.088164) (xy 138.68313 113.862735) (xy 138.68313 114.815)
-        (xy 99.873 114.815) (xy 99.873 114.07625) (xy 99.873 113.127) (xy 98.92375 113.127) (xy 98.765 113.28575)
-        (xy 98.76489 113.474245) (xy 98.765111 113.726864) (xy 98.861987 113.960168) (xy 99.040771 114.138641) (xy 99.274245 114.23511)
-        (xy 99.71425 114.235) (xy 99.873 114.07625) (xy 99.873 114.815) (xy 97.685 114.815) (xy 97.685 91.185)
-        (xy 140.315 91.185) (xy 140.315 114.815)
+        (xy 105.038815 114.538815) (xy 105.463264 114.114365) (xy 105.753266 114.234785) (xy 106.244579 114.235214) (xy 106.698657 114.047592)
+        (xy 107.000221 113.746554) (xy 107.299515 114.046371) (xy 107.753266 114.234785) (xy 108.244579 114.235214) (xy 108.698657 114.047592)
+        (xy 109.000221 113.746554) (xy 109.299515 114.046371) (xy 109.753266 114.234785) (xy 110.244579 114.235214) (xy 110.698657 114.047592)
+        (xy 111.000221 113.746554) (xy 111.299515 114.046371) (xy 111.753266 114.234785) (xy 112.244579 114.235214) (xy 112.698657 114.047592)
+        (xy 113.000221 113.746554) (xy 113.299515 114.046371) (xy 113.753266 114.234785) (xy 114.244579 114.235214) (xy 114.698657 114.047592)
+        (xy 115.000221 113.746554) (xy 115.299515 114.046371) (xy 115.753266 114.234785) (xy 116.244579 114.235214) (xy 116.698657 114.047592)
+        (xy 117.000221 113.746554) (xy 117.299515 114.046371) (xy 117.753266 114.234785) (xy 118.244579 114.235214) (xy 118.698657 114.047592)
+        (xy 119.000221 113.746554) (xy 119.299515 114.046371) (xy 119.753266 114.234785) (xy 120.244579 114.235214) (xy 120.698657 114.047592)
+        (xy 121.000221 113.746554) (xy 121.299515 114.046371) (xy 121.753266 114.234785) (xy 122.244579 114.235214) (xy 122.698657 114.047592)
+        (xy 123.000221 113.746554) (xy 123.299515 114.046371) (xy 123.753266 114.234785) (xy 124.244579 114.235214) (xy 124.698657 114.047592)
+        (xy 125.000221 113.746554) (xy 125.299515 114.046371) (xy 125.753266 114.234785) (xy 126.244579 114.235214) (xy 126.698657 114.047592)
+        (xy 127.000221 113.746554) (xy 127.299515 114.046371) (xy 127.753266 114.234785) (xy 128.244579 114.235214) (xy 128.698657 114.047592)
+        (xy 129.000221 113.746554) (xy 129.299515 114.046371) (xy 129.753266 114.234785) (xy 130.244579 114.235214) (xy 130.698657 114.047592)
+        (xy 131.000221 113.746554) (xy 131.299515 114.046371) (xy 131.753266 114.234785) (xy 132.244579 114.235214) (xy 132.698657 114.047592)
+        (xy 133.000221 113.746554) (xy 133.299515 114.046371) (xy 133.753266 114.234785) (xy 134.244579 114.235214) (xy 134.698657 114.047592)
+        (xy 135.000221 113.746554) (xy 135.299515 114.046371) (xy 135.753266 114.234785) (xy 136.244579 114.235214) (xy 136.698657 114.047592)
+        (xy 137.046371 113.700485) (xy 137.060571 113.666285) (xy 137.137265 113.68313) (xy 137.820395 113) (xy 137.820395 113.35921)
+        (xy 137.31687 113.862735) (xy 137.366383 114.088164) (xy 137.831036 114.247807) (xy 138.321413 114.217482) (xy 138.633617 114.088164)
+        (xy 138.68313 113.862735) (xy 138.68313 114.815) (xy 99.873 114.815) (xy 99.873 114.07625) (xy 99.873 113.127)
+        (xy 98.92375 113.127) (xy 98.765 113.28575) (xy 98.76489 113.474245) (xy 98.765111 113.726864) (xy 98.861987 113.960168)
+        (xy 99.040771 114.138641) (xy 99.274245 114.23511) (xy 99.71425 114.235) (xy 99.873 114.07625) (xy 99.873 114.815)
+        (xy 97.685 114.815) (xy 97.685 91.185) (xy 140.315 91.185) (xy 140.315 114.815)
       )
     )
   )
diff --git a/96boards-uart.net b/96boards-uart.net
index 6c061db..5ed952b 100644
--- a/96boards-uart.net
+++ b/96boards-uart.net
@@ -1,4 +1,4 @@
-# EESchema Netlist Version 1.1 created  Mon 02 Mar 2015 13:19:42 GMT
+# EESchema Netlist Version 1.1 created  Mon 09 Mar 2015 15:58:13 GMT
 (
  ( /54EBBD3A $noname  SW1 SW_PUSH {Lib=SW_PUSH}
   (    1 /PWR_BTN )
@@ -12,7 +12,7 @@
   (    1 VIO )
   (    2 VDD )
   (    3 ? )
-  (    4 +1.8V )
+  (    4 /1_8V_SENSE )
   (    5 N-000006 )
   (    6 /PWR_BTN )
   (    7 /RST_BTN )
@@ -26,7 +26,7 @@
   (   15 ? )
   (   16 ? )
  )
- ( /54F0AFFF PIN_ARRAY_2MM_20X2  P1 96BOARD_LS_EXPANSION {Lib=96BOARD_LS_EXPANSION}
+ ( /54F0AFFF 96BOARD_LS_EXPANSION  P1 96BOARD_LS_EXPANSION {Lib=96BOARD_LS_EXPANSION}
   (    1 GND )
   (    2 GND )
   (    3 /UART0_CTS_LV )
@@ -76,6 +76,10 @@
   (    1 VIO )
   (    2 VDD )
  )
+ ( /54FDBF43 $noname  R2 10K {Lib=R}
+  (    1 +1.8V )
+  (    2 /1_8V_SENSE )
+ )
 )
 *
 { Allowed footprints by component:
@@ -91,48 +95,58 @@ $component R1
  R?-*
  SM1206
 $endlist
+$component R2
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$endlist
 $endfootprintlist
 }
 { Pin List by Nets
 Net 1 "VDD" "VDD"
  P2 2
  R1 2
-Net 2 "GND" "GND"
- P1 2
- P1 1
- P2 9
- SW2 2
- SW1 2
- P1 39
- D1 1
- P1 40
+Net 2 "/UART0_CTS_LV" "UART0_CTS_LV"
+ P1 3
+ P2 12
 Net 3 "VIO" "VIO"
  D1 2
  R1 1
  P2 1
 Net 4 "+1.8V" "+1.8V"
- P2 4
  P1 35
-Net 5 "/UART0_CTS_LV" "UART0_CTS_LV"
- P1 3
- P2 12
+ R2 1
+Net 5 "/1_8V_SENSE" "1_8V_SENSE"
+ P2 4
+ R2 2
 Net 6 "" ""
  P2 5
  P1 23
-Net 12 "/UART0_TXD_LV" "UART0_TXD_LV"
+Net 7 "GND" "GND"
+ P1 40
+ D1 1
+ P1 2
+ SW2 2
+ SW1 2
+ P1 1
+ P1 39
+ P2 9
+Net 13 "/UART0_TXD_LV" "UART0_TXD_LV"
  P2 11
  P1 5
-Net 13 "/UART0_RXD_LV" "UART0_RXD_LV"
- P1 7
+Net 14 "/UART0_RXD_LV" "UART0_RXD_LV"
  P2 10
-Net 14 "/UART0_RTS_LV" "UART0_RTS_LV"
+ P1 7
+Net 15 "/UART0_RTS_LV" "UART0_RTS_LV"
  P1 9
  P2 13
-Net 15 "/PWR_BTN" "PWR_BTN"
- P2 6
+Net 16 "/PWR_BTN" "PWR_BTN"
  P1 4
  SW1 1
-Net 16 "/RST_BTN" "RST_BTN"
+ P2 6
+Net 17 "/RST_BTN" "RST_BTN"
  P1 6
  SW2 1
  P2 7
diff --git a/96boards-uart.sch b/96boards-uart.sch
index 80d5e0a..aa2e670 100644
--- a/96boards-uart.sch
+++ b/96boards-uart.sch
@@ -38,7 +38,7 @@ $Descr A4 11693 8268
 encoding utf-8
 Sheet 1 1
 Title ""
-Date "2 mar 2015"
+Date "9 mar 2015"
 Rev ""
 Comp ""
 Comment1 ""
@@ -47,10 +47,10 @@ Comment3 ""
 Comment4 ""
 $EndDescr
 $Comp
-L GND #PWR01
+L GND #PWR4
 U 1 1 54E654DB
 P 4900 3200
-F 0 "#PWR01" H 4900 3200 30  0001 C CNN
+F 0 "#PWR4" H 4900 3200 30  0001 C CNN
 F 1 "GND" H 4900 3130 30  0001 C CNN
 F 2 "" H 4900 3200 60  0000 C CNN
 F 3 "" H 4900 3200 60  0000 C CNN
@@ -62,10 +62,10 @@ UART0_TXD_LV
 Text Label 1400 3600 0    60   ~ 0
 UART0_RXD_LV
 $Comp
-L +1.8V #PWR02
+L +1.8V #PWR1
 U 1 1 54E79659
 P 1300 4850
-F 0 "#PWR02" H 1300 4990 20  0001 C CNN
+F 0 "#PWR1" H 1300 4990 20  0001 C CNN
 F 1 "+1.8V" H 1300 4960 30  0000 C CNN
 F 2 "" H 1300 4850 60  0000 C CNN
 F 3 "" H 1300 4850 60  0000 C CNN
@@ -73,10 +73,10 @@ F 3 "" H 1300 4850 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L GND #PWR03
+L GND #PWR3
 U 1 1 54EB8F4C
 P 4750 5450
-F 0 "#PWR03" H 4750 5450 30  0001 C CNN
+F 0 "#PWR3" H 4750 5450 30  0001 C CNN
 F 1 "GND" H 4750 5380 30  0001 C CNN
 F 2 "" H 4750 5450 60  0000 C CNN
 F 3 "" H 4750 5450 60  0000 C CNN
@@ -84,10 +84,10 @@ F 3 "" H 4750 5450 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L GND #PWR04
+L GND #PWR2
 U 1 1 54EB8F88
 P 1550 5450
-F 0 "#PWR04" H 1550 5450 30  0001 C CNN
+F 0 "#PWR2" H 1550 5450 30  0001 C CNN
 F 1 "GND" H 1550 5380 30  0001 C CNN
 F 2 "" H 1550 5450 60  0000 C CNN
 F 3 "" H 1550 5450 60  0000 C CNN
@@ -125,10 +125,10 @@ F 3 "~" H 6000 5750 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L GND #PWR05
+L GND #PWR8
 U 1 1 54EBBDBB
 P 6450 5950
-F 0 "#PWR05" H 6450 5950 30  0001 C CNN
+F 0 "#PWR8" H 6450 5950 30  0001 C CNN
 F 1 "GND" H 6450 5880 30  0001 C CNN
 F 2 "" H 6450 5950 60  0000 C CNN
 F 3 "" H 6450 5950 60  0000 C CNN
@@ -136,10 +136,10 @@ F 3 "" H 6450 5950 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L GND #PWR06
+L GND #PWR9
 U 1 1 54EC9B62
 P 9000 3800
-F 0 "#PWR06" H 9000 3800 30  0001 C CNN
+F 0 "#PWR9" H 9000 3800 30  0001 C CNN
 F 1 "GND" H 9000 3730 30  0001 C CNN
 F 2 "" H 9000 3800 60  0000 C CNN
 F 3 "" H 9000 3800 60  0000 C CNN
@@ -163,7 +163,7 @@ U 1 1 54F0AFFF
 P 3300 4250
 F 0 "P1" H 3300 5300 60  0000 C CNN
 F 1 "96BOARD_LS_EXPANSION" H 3300 3200 50  0000 C CNN
-F 2 "PIN_ARRAY_2MM_20X2" H 3300 4250 60  0000 C CNN
+F 2 "96BOARD_LS_EXPANSION" H 3300 4250 60  0000 C CNN
 F 3 "" H 3300 4250 60  0000 C CNN
 	1    3300 4250
 	1    0    0    -1  
@@ -182,23 +182,23 @@ $EndComp
 $Comp
 L R R1
 U 1 1 54F378F7
-P 5600 3450
-F 0 "R1" V 5680 3450 40  0000 C CNN
-F 1 "10K" V 5607 3451 40  0000 C CNN
-F 2 "~" V 5530 3450 30  0000 C CNN
-F 3 "~" H 5600 3450 30  0000 C CNN
-	1    5600 3450
+P 6350 3450
+F 0 "R1" V 6430 3450 40  0000 C CNN
+F 1 "10K" V 6357 3451 40  0000 C CNN
+F 2 "~" V 6280 3450 30  0000 C CNN
+F 3 "~" H 6350 3450 30  0000 C CNN
+	1    6350 3450
 	1    0    0    -1  
 $EndComp
 $Comp
-L +1.8V #PWR07
+L +1.8V #PWR5
 U 1 1 54F46275
-P 6150 3450
-F 0 "#PWR07" H 6150 3590 20  0001 C CNN
-F 1 "+1.8V" H 6150 3560 30  0000 C CNN
-F 2 "" H 6150 3450 60  0000 C CNN
-F 3 "" H 6150 3450 60  0000 C CNN
-	1    6150 3450
+P 5900 3050
+F 0 "#PWR5" H 5900 3190 20  0001 C CNN
+F 1 "+1.8V" H 5900 3160 30  0000 C CNN
+F 2 "" H 5900 3050 60  0000 C CNN
+F 3 "" H 5900 3050 60  0000 C CNN
+	1    5900 3050
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
@@ -288,9 +288,7 @@ Wire Wire Line
 Wire Wire Line
 	8850 4050 8200 4050
 Wire Wire Line
-	6150 3950 6600 3950
-Wire Wire Line
-	6150 3450 6150 3950
+	5900 3950 6600 3950
 Wire Wire Line
 	6600 4150 5100 4150
 Connection ~ 5100 4150
@@ -302,57 +300,72 @@ Wire Wire Line
 Wire Wire Line
 	1000 4400 1000 2450
 Wire Wire Line
-	1000 2450 6000 2450
+	1000 2450 5200 2450
 Wire Wire Line
-	6000 2450 6000 4050
+	5200 2450 5200 4050
 Wire Wire Line
-	6000 4050 6600 4050
+	5200 4050 6600 4050
 Wire Wire Line
 	7650 3150 8350 3150
 Wire Wire Line
 	8350 3150 8350 3650
 Connection ~ 8350 3650
 Wire Wire Line
-	5600 3150 7250 3150
+	6350 3150 7250 3150
 Wire Wire Line
 	6550 3150 6550 3650
 Wire Wire Line
 	6550 3650 6600 3650
 Wire Wire Line
-	5600 3100 5600 3200
+	6350 3050 6350 3200
 Connection ~ 6550 3150
 Wire Wire Line
-	5600 3700 5600 3750
+	6350 3700 6350 3750
 Wire Wire Line
-	5350 3750 6600 3750
-Connection ~ 5600 3150
-Text Label 6150 3950 0    60   ~ 0
+	6200 3750 6600 3750
+Connection ~ 6350 3150
+Text Label 5900 3950 0    60   ~ 0
 1_8V_SENSE
 $Comp
-L VDD #PWR08
+L VDD #PWR6
 U 1 1 54F463DD
-P 5350 3100
-F 0 "#PWR08" H 5350 3200 30  0001 C CNN
-F 1 "VDD" H 5350 3210 30  0000 C CNN
-F 2 "" H 5350 3100 60  0000 C CNN
-F 3 "" H 5350 3100 60  0000 C CNN
-	1    5350 3100
+P 6200 3050
+F 0 "#PWR6" H 6200 3150 30  0001 C CNN
+F 1 "VDD" H 6200 3160 30  0000 C CNN
+F 2 "" H 6200 3050 60  0000 C CNN
+F 3 "" H 6200 3050 60  0000 C CNN
+	1    6200 3050
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
-	5350 3100 5350 3750
-Connection ~ 5600 3750
+	6200 3050 6200 3750
+Connection ~ 6350 3750
 Wire Wire Line
 	1400 2850 8550 2850
 $Comp
-L VIO #PWR09
+L VIO #PWR7
 U 1 1 54F464F9
-P 5600 3100
-F 0 "#PWR09" H 5600 3200 30  0001 C CNN
-F 1 "VIO" H 5600 3210 30  0000 C CNN
-F 2 "" H 5600 3100 60  0000 C CNN
-F 3 "" H 5600 3100 60  0000 C CNN
-	1    5600 3100
+P 6350 3050
+F 0 "#PWR7" H 6350 3150 30  0001 C CNN
+F 1 "VIO" H 6350 3160 30  0000 C CNN
+F 2 "" H 6350 3050 60  0000 C CNN
+F 3 "" H 6350 3050 60  0000 C CNN
+	1    6350 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 54FDBF43
+P 5900 3450
+F 0 "R2" V 5980 3450 40  0000 C CNN
+F 1 "10K" V 5907 3451 40  0000 C CNN
+F 2 "~" V 5830 3450 30  0000 C CNN
+F 3 "~" H 5900 3450 30  0000 C CNN
+	1    5900 3450
 	1    0    0    -1  
 $EndComp
+Wire Wire Line
+	5900 3700 5900 3950
+Wire Wire Line
+	5900 3200 5900 3050
 $EndSCHEMATC