Merge "net: stmmac: Add support for qcom serdes" into wip-er12

6 files changed, 733 insertions, 20 deletions

diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index b8741ed28ee82..15b93a51ecdc7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -21,8 +21,8 @@ obj-$(CONFIG_DWMAC_MEDIATEK)	+= dwmac-mediatek.o
 obj-$(CONFIG_DWMAC_MESON)	+= dwmac-meson.o dwmac-meson8b.o
 obj-$(CONFIG_DWMAC_OXNAS)	+= dwmac-oxnas.o
 obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-eth.o
-dwmac-qcom-eth-objs := dwmac-qcom-ethqos.o dwmac-qcom-gpio.o dwmac-qcom-pps.o
-
+dwmac-qcom-eth-objs := dwmac-qcom-ethqos.o dwmac-qcom-gpio.o dwmac-qcom-pps.o \
+		       dwmac-qcom-serdes.o
 obj-$(CONFIG_DWMAC_ROCKCHIP)	+= dwmac-rk.o
 obj-$(CONFIG_DWMAC_SOCFPGA)	+= dwmac-altr-socfpga.o
 obj-$(CONFIG_DWMAC_STI)		+= dwmac-sti.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index f1285e63af80f..9b8f885b4adc7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -27,6 +27,7 @@
 #include "stmmac_platform.h"
 #include "dwmac-qcom-ethqos.h"
 #include "stmmac_ptp.h"
+#include "dwmac-qcom-serdes.h"
 
 #define RGMII_IO_MACRO_DEBUG1		0x20
 #define EMAC_SYSTEM_LOW_POWER_DEBUG	0x28
@@ -1016,18 +1017,51 @@ static int ethqos_configure_mac_v3(struct qcom_ethqos *ethqos)
 	return ret;
 }
 
+int ethqos_configureSGMII(struct qcom_ethqos *ethqos)
+{
+	u32 value = 0;
+
+	value = readl(ethqos->ioaddr + MAC_CTRL_REG);
+	switch (ethqos->speed) {
+	case SPEED_1000:
+		value &= ~BIT(15);
+		writel(value, ethqos->ioaddr + MAC_CTRL_REG);
+		rgmii_updatel(ethqos, BIT(16), BIT(16), RGMII_IO_MACRO_CONFIG2);
+	break;
+
+	case SPEED_100:
+		value |= BIT(15) | BIT(14);
+		writel(value, ethqos->ioaddr + MAC_CTRL_REG);
+	break;
+	case SPEED_10:
+		value |= BIT(15);
+		value &= ~BIT(14);
+		writel(value, ethqos->ioaddr + MAC_CTRL_REG);
+	break;
+	}
+
+	return value;
+}
+
 static void ethqos_fix_mac_speed(void *priv, unsigned int speed)
 {
 	struct qcom_ethqos *ethqos = priv;
-	int ret = 0;
+	struct stmmac_priv *stmpriv = qcom_ethqos_get_priv(ethqos);
+	int ret = -1;
 
 	ethqos->speed = speed;
-	ethqos_update_rgmii_clk(ethqos, speed);
-	if (ethqos->emac_ver == EMAC_HW_v3_0_0_RG)
-		ret = ethqos_configure_mac_v3(ethqos);
-	else
-		ethqos_configure(ethqos);
-	if (ret != 0)
+
+	if (stmpriv->plat->interface == PHY_INTERFACE_MODE_SGMII) {
+		ret = ethqos_configureSGMII(ethqos);
+	} else {
+		ethqos_update_rgmii_clk(ethqos, speed);
+		if (ethqos->emac_ver == EMAC_HW_v3_0_0_RG)
+			ret = ethqos_configure_mac_v3(ethqos);
+		else
+			ethqos_configure(ethqos);
+	}
+
+	if (ret < 0)
 		ETHQOSERR("HSR configuration has failed\n");
 }
 
@@ -1170,6 +1204,7 @@ static int ethqos_phy_intr_enable(void *priv_n)
 }
 
 static const struct of_device_id qcom_ethqos_match[] = {
+	{ .compatible = "qcom,stmmac-ethqos", },
 	{ .compatible = "qcom,stmmac-ethqos-emac0", },
 	{ .compatible = "qcom,stmmac-ethqos-emac1", },
 	{ .compatible = "qcom,emac-smmu-embedded", },
@@ -1630,24 +1665,32 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
 		return PTR_ERR(plat_dat);
 	}
 
+	ethqos->ioaddr = (&stmmac_res)->addr;
+
 	ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
 	if (IS_ERR(ethqos->rgmii_base)) {
 		ret = PTR_ERR(ethqos->rgmii_base);
 		goto err_mem;
 	}
 
-	ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii");
-	if (IS_ERR(ethqos->rgmii_clk)) {
-		ret = PTR_ERR(ethqos->rgmii_clk);
-		goto err_mem;
+	ethqos->speed = SPEED_10;
+	if (plat_dat->interface == PHY_INTERFACE_MODE_SGMII) {
+		ret = configure_serdes_dt(ethqos);
+		if (ret)
+			goto err_mem;
+		qcom_ethqos_serdes_init(ethqos, ethqos->speed);
+	} else {
+		ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii");
+		if (IS_ERR(ethqos->rgmii_clk)) {
+			ret = PTR_ERR(ethqos->rgmii_clk);
+			goto err_mem;
+		}
+		ret = clk_prepare_enable(ethqos->rgmii_clk);
+		if (ret)
+			goto err_mem;
+		ethqos_update_rgmii_clk(ethqos, SPEED_10);
 	}
 
-	ret = clk_prepare_enable(ethqos->rgmii_clk);
-	if (ret)
-		goto err_mem;
-
-	ethqos->speed = SPEED_1000;
-	ethqos_update_rgmii_clk(ethqos, SPEED_1000);
 	ethqos_set_func_clk_en(ethqos);
 
 	plat_dat->bsp_priv = ethqos;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.h
index 82517275897fc..76f06335a2327 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.h
@@ -119,9 +119,15 @@ struct ethqos_io_macro {
 struct qcom_ethqos {
 	struct platform_device *pdev;
 	void __iomem *rgmii_base;
+	void __iomem *sgmii_base;
+	void __iomem *ioaddr;
+
 
 	unsigned int rgmii_clk_rate;
 	struct clk *rgmii_clk;
+	struct clk *phyaux_clk;
+	struct clk *sgmiref_clk;
+
 	unsigned int speed;
 
 	int gpio_phy_intr_redirect;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-serdes.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-serdes.c
new file mode 100644
index 0000000000000..056013d91f400
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-serdes.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+
+// Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/of_gpio.h>
+
+#include <linux/phy.h>
+#include <linux/io.h>
+
+#include <linux/iopoll.h>
+#include <linux/mii.h>
+#include <linux/of_mdio.h>
+#include <linux/slab.h>
+#include <linux/poll.h>
+#include <linux/debugfs.h>
+#include <linux/dma-iommu.h>
+#include <linux/iommu.h>
+#include <linux/micrel_phy.h>
+#include <linux/tcp.h>
+#include <linux/ip.h>
+
+#include <linux/rtnetlink.h>
+#include <asm-generic/io.h>
+#include <linux/kthread.h>
+#include <linux/io-64-nonatomic-hi-lo.h>
+
+#include "dwmac-qcom-serdes.h"
+
+int configure_serdes_dt(struct qcom_ethqos *ethqos)
+{
+	struct resource *res = NULL;
+	struct platform_device *pdev = ethqos->pdev;
+	int ret;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "serdes");
+	ethqos->sgmii_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(ethqos->sgmii_base)) {
+		dev_err(&pdev->dev, "Can't get sgmii base\n");
+		ret = PTR_ERR(ethqos->sgmii_base);
+		goto err_mem;
+	}
+
+	ethqos->sgmiref_clk = devm_clk_get(&pdev->dev, "sgmi_ref");
+	if (IS_ERR(ethqos->sgmiref_clk)) {
+		ret = PTR_ERR(ethqos->sgmiref_clk);
+		ethqos->sgmiref_clk = NULL;
+		goto err_mem;
+	}
+	ethqos->phyaux_clk = devm_clk_get(&pdev->dev, "phyaux");
+	if (IS_ERR(ethqos->phyaux_clk)) {
+		ret = PTR_ERR(ethqos->phyaux_clk);
+		goto err_get_phyaux_clk;
+	}
+
+	ret = clk_prepare_enable(ethqos->sgmiref_clk);
+	if (ret)
+		goto err_enable_sgmiref_clk;
+
+	ret = clk_prepare_enable(ethqos->phyaux_clk);
+	if (ret)
+		goto err_enable_phyaux_clk;
+
+	return 0;
+
+err_enable_phyaux_clk:
+	clk_disable_unprepare(ethqos->sgmiref_clk);
+err_enable_sgmiref_clk:
+	ethqos->phyaux_clk = NULL;
+err_get_phyaux_clk:
+	ethqos->sgmiref_clk = NULL;
+err_mem:
+	return ret;
+}
+
+void qcom_ethqos_serdes_init(struct qcom_ethqos *ethqos, int speed)
+{
+	int retry = 500;
+	unsigned int val;
+
+	/****************MODULE: SGMII_PHY_SGMII_PCS**********************************/
+	writel_relaxed(0x01, ethqos->sgmii_base + QSERDES_PCS_SW_RESET);
+	writel_relaxed(0x01, ethqos->sgmii_base + QSERDES_PCS_POWER_DOWN_CONTROL);
+
+	/***************** MODULE: QSERDES_COM_SGMII_QMP_PLL*********/
+	writel_relaxed(0x0F, ethqos->sgmii_base + QSERDES_COM_PLL_IVCO);
+	writel_relaxed(0x06, ethqos->sgmii_base + QSERDES_COM_CP_CTRL_MODE0);
+	writel_relaxed(0x16, ethqos->sgmii_base + QSERDES_COM_PLL_RCTRL_MODE0);
+	writel_relaxed(0x36, ethqos->sgmii_base + QSERDES_COM_PLL_CCTRL_MODE0);
+	writel_relaxed(0x1A, ethqos->sgmii_base + QSERDES_COM_SYSCLK_EN_SEL);
+	writel_relaxed(0x0A, ethqos->sgmii_base + QSERDES_COM_LOCK_CMP1_MODE0);
+	writel_relaxed(0x1A, ethqos->sgmii_base + QSERDES_COM_LOCK_CMP2_MODE0);
+	writel_relaxed(0x82, ethqos->sgmii_base + QSERDES_COM_DEC_START_MODE0);
+	writel_relaxed(0x55, ethqos->sgmii_base + QSERDES_COM_DIV_FRAC_START1_MODE0);
+	writel_relaxed(0x55, ethqos->sgmii_base + QSERDES_COM_DIV_FRAC_START2_MODE0);
+	writel_relaxed(0x03, ethqos->sgmii_base + QSERDES_COM_DIV_FRAC_START3_MODE0);
+	writel_relaxed(0x24, ethqos->sgmii_base + QSERDES_COM_VCO_TUNE1_MODE0);
+
+	writel_relaxed(0x02, ethqos->sgmii_base + QSERDES_COM_VCO_TUNE2_MODE0);
+	writel_relaxed(0x00, ethqos->sgmii_base + QSERDES_COM_VCO_TUNE_INITVAL2);
+	writel_relaxed(0x04, ethqos->sgmii_base + QSERDES_COM_HSCLK_SEL);
+	writel_relaxed(0x00, ethqos->sgmii_base + QSERDES_COM_HSCLK_HS_SWITCH_SEL);
+	writel_relaxed(0x0A, ethqos->sgmii_base + QSERDES_COM_CORECLK_DIV_MODE0);
+	writel_relaxed(0x00, ethqos->sgmii_base + QSERDES_COM_CORE_CLK_EN);
+	writel_relaxed(0xB9, ethqos->sgmii_base + QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0);
+	writel_relaxed(0x1E, ethqos->sgmii_base + QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0);
+	writel_relaxed(0x11, ethqos->sgmii_base + QSERDES_COM_BIN_VCOCAL_HSCLK_SEL);
+
+	/******************MODULE: QSERDES_TX0_SGMII_QMP_TX***********************/
+	writel_relaxed(0x05, ethqos->sgmii_base + QSERDES_TX_TX_BAND);
+	writel_relaxed(0x0A, ethqos->sgmii_base + QSERDES_TX_SLEW_CNTL);
+	writel_relaxed(0x09, ethqos->sgmii_base + QSERDES_TX_RES_CODE_LANE_OFFSET_TX);
+	writel_relaxed(0x09, ethqos->sgmii_base + QSERDES_TX_RES_CODE_LANE_OFFSET_RX);
+	writel_relaxed(0x05, ethqos->sgmii_base + QSERDES_TX_LANE_MODE_1);
+	writel_relaxed(0x00, ethqos->sgmii_base + QSERDES_TX_LANE_MODE_3);
+	writel_relaxed(0x12, ethqos->sgmii_base + QSERDES_TX_RCV_DETECT_LVL_2);
+	writel_relaxed(0x0C, ethqos->sgmii_base + QSERDES_TX_TRAN_DRVR_EMP_EN);
+
+	/*****************MODULE: QSERDES_RX0_SGMII_QMP_RX*******************/
+	writel_relaxed(0x0A, ethqos->sgmii_base + QSERDES_RX_UCDR_FO_GAIN);
+	writel_relaxed(0x06, ethqos->sgmii_base + QSERDES_RX_UCDR_SO_GAIN);
+	writel_relaxed(0x0A, ethqos->sgmii_base + QSERDES_RX_UCDR_FASTLOCK_FO_GAIN);
+	writel_relaxed(0x7F, ethqos->sgmii_base + QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE);
+	writel_relaxed(0x00, ethqos->sgmii_base + QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW);
+	writel_relaxed(0x01, ethqos->sgmii_base + QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH);
+	writel_relaxed(0x81, ethqos->sgmii_base + QSERDES_RX_UCDR_PI_CONTROLS);
+	writel_relaxed(0x80, ethqos->sgmii_base + QSERDES_RX_UCDR_PI_CTRL2);
+	writel_relaxed(0x04, ethqos->sgmii_base + QSERDES_RX_RX_TERM_BW);
+	writel_relaxed(0x08, ethqos->sgmii_base + QSERDES_RX_VGA_CAL_CNTRL2);
+	writel_relaxed(0x0F, ethqos->sgmii_base + QSERDES_RX_GM_CAL);
+	writel_relaxed(0x04, ethqos->sgmii_base + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1);
+	writel_relaxed(0x00, ethqos->sgmii_base + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2);
+	writel_relaxed(0x4A, ethqos->sgmii_base + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3);
+	writel_relaxed(0x0A, ethqos->sgmii_base + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4);
+	writel_relaxed(0x80, ethqos->sgmii_base + QSERDES_RX_RX_IDAC_TSETTLE_LOW);
+	writel_relaxed(0x01, ethqos->sgmii_base + QSERDES_RX_RX_IDAC_TSETTLE_HIGH);
+	writel_relaxed(0x20, ethqos->sgmii_base + QSERDES_RX_RX_IDAC_MEASURE_TIME);
+	writel_relaxed(0x17, ethqos->sgmii_base + QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1);
+	writel_relaxed(0x00, ethqos->sgmii_base + QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2);
+	writel_relaxed(0x0F, ethqos->sgmii_base + QSERDES_RX_SIGDET_CNTRL);
+	writel_relaxed(0x1E, ethqos->sgmii_base + QSERDES_RX_SIGDET_DEGLITCH_CNTRL);
+	writel_relaxed(0x05, ethqos->sgmii_base + QSERDES_RX_RX_BAND);
+	writel_relaxed(0xE0, ethqos->sgmii_base + QSERDES_RX_RX_MODE_00_LOW);
+	writel_relaxed(0xC8, ethqos->sgmii_base + QSERDES_RX_RX_MODE_00_HIGH);
+	writel_relaxed(0xC8, ethqos->sgmii_base + QSERDES_RX_RX_MODE_00_HIGH2);
+	writel_relaxed(0x09, ethqos->sgmii_base + QSERDES_RX_RX_MODE_00_HIGH3);
+	writel_relaxed(0xB1, ethqos->sgmii_base + QSERDES_RX_RX_MODE_00_HIGH4);
+	writel_relaxed(0xE0, ethqos->sgmii_base + QSERDES_RX_RX_MODE_01_LOW);
+	writel_relaxed(0xC8, ethqos->sgmii_base + QSERDES_RX_RX_MODE_01_HIGH);
+	writel_relaxed(0xC8, ethqos->sgmii_base + QSERDES_RX_RX_MODE_01_HIGH2);
+	writel_relaxed(0x09, ethqos->sgmii_base + QSERDES_RX_RX_MODE_01_HIGH3);
+	writel_relaxed(0xB1, ethqos->sgmii_base + QSERDES_RX_RX_MODE_01_HIGH4);
+	writel_relaxed(0xE0, ethqos->sgmii_base + QSERDES_RX_RX_MODE_10_LOW);
+	writel_relaxed(0xC8, ethqos->sgmii_base + QSERDES_RX_RX_MODE_10_HIGH);
+	writel_relaxed(0xC8, ethqos->sgmii_base + QSERDES_RX_RX_MODE_10_HIGH2);
+	writel_relaxed(0x3B, ethqos->sgmii_base + QSERDES_RX_RX_MODE_10_HIGH3);
+	writel_relaxed(0xB7, ethqos->sgmii_base + QSERDES_RX_RX_MODE_10_HIGH4);
+	writel_relaxed(0x0C, ethqos->sgmii_base + QSERDES_RX_DCC_CTRL1);
+
+	/****************MODULE: SGMII_PHY_SGMII_PCS**********************************/
+	writel_relaxed(0x0C, ethqos->sgmii_base + QSERDES_PCS_LINE_RESET_TIME);
+	writel_relaxed(0x1F, ethqos->sgmii_base + QSERDES_PCS_TX_LARGE_AMP_DRV_LVL);
+	writel_relaxed(0x03, ethqos->sgmii_base + QSERDES_PCS_TX_SMALL_AMP_DRV_LVL);
+	writel_relaxed(0x83, ethqos->sgmii_base + QSERDES_PCS_TX_MID_TERM_CTRL1);
+	writel_relaxed(0x08, ethqos->sgmii_base + QSERDES_PCS_TX_MID_TERM_CTRL2);
+	writel_relaxed(0x0C, ethqos->sgmii_base + QSERDES_PCS_SGMII_MISC_CTRL8);
+	writel_relaxed(0x00, ethqos->sgmii_base + QSERDES_PCS_SW_RESET);
+
+	writel_relaxed(0x01, ethqos->sgmii_base + QSERDES_PCS_PHY_START);
+
+	do {
+		val = readl_relaxed(ethqos->sgmii_base + QSERDES_COM_C_READY_STATUS);
+		val &= BIT(0);
+		if (val)
+			break;
+		usleep_range(1000, 1500);
+		retry--;
+	} while (retry > 0);
+	if (!retry)
+		ETHQOSERR("QSERDES_COM_C_READY_STATUS timedout with retry = %d\n", retry);
+
+	retry = 500;
+	do {
+		val = readl_relaxed(ethqos->sgmii_base + QSERDES_PCS_PCS_READY_STATUS);
+		val &= BIT(0);
+		if (val)
+			break;
+		usleep_range(1000, 1500);
+		retry--;
+	} while (retry > 0);
+	if (!retry)
+		ETHQOSERR("PCS_READY timedout with retry = %d\n", retry);
+
+	retry = 500;
+	do {
+		val = readl_relaxed(ethqos->sgmii_base + QSERDES_PCS_PCS_READY_STATUS);
+		val &= BIT(7);
+		if (val)
+			break;
+		usleep_range(1000, 1500);
+		retry--;
+	} while (retry > 0);
+	if (!retry)
+		ETHQOSERR("SGMIIPHY_READY timedout with retry = %d\n", retry);
+
+	retry = 5000;
+	do {
+		val = readl_relaxed(ethqos->sgmii_base + QSERDES_COM_CMN_STATUS);
+		val &= BIT(1);
+		if (val)
+			break;
+		usleep_range(1000, 1500);
+		retry--;
+	} while (retry > 0);
+	if (!retry)
+		ETHQOSERR("PLL Lock Status timedout with retry = %d\n", retry);
+}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-serdes.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-serdes.h
new file mode 100644
index 0000000000000..f7acda6c7dbda
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-serdes.h
@@ -0,0 +1,443 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+/*Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.*/
+#ifndef	_DWMAC_QCOM_SERDES_H
+#define	_DWMAC_QCOM_SERDES_H
+
+#include <linux/inetdevice.h>
+#include <linux/inet.h>
+#include <net/addrconf.h>
+#include <net/ipv6.h>
+#include <net/inet_common.h>
+#include <linux/uaccess.h>
+
+#include "stmmac.h"
+#include "dwmac-qcom-ethqos.h"
+
+#define QSERDES_QMP_PLL	0x0
+#define QSERDES_COM_ATB_SEL1	(QSERDES_QMP_PLL + 0x0)
+#define QSERDES_COM_ATB_SEL2	(QSERDES_QMP_PLL + 0x4)
+#define QSERDES_COM_BG_TIMER	(QSERDES_QMP_PLL + 0xC)
+#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN	(QSERDES_QMP_PLL + 0x44)
+#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM	(QSERDES_QMP_PLL + 0x90)
+#define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	(QSERDES_QMP_PLL + 0x1AC)
+#define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	(QSERDES_QMP_PLL + 0x1B4)
+#define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	(QSERDES_QMP_PLL + 0x1B0)
+#define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	(QSERDES_QMP_PLL + 0x1B8)
+#define QSERDES_COM_BIN_VCOCAL_HSCLK_SEL	(QSERDES_QMP_PLL + 0x1BC)
+#define QSERDES_COM_C_READY_STATUS	(QSERDES_QMP_PLL + 0x178)
+#define QSERDES_COM_CLK_ENABLE1	(QSERDES_QMP_PLL + 0x48)
+#define QSERDES_COM_CLK_EP_DIV_MODE0	(QSERDES_QMP_PLL + 0x6C)
+#define QSERDES_COM_CLK_EP_DIV_MODE1	(QSERDES_QMP_PLL + 0x70)
+#define QSERDES_COM_CLK_SELECT	(QSERDES_QMP_PLL + 0x154)
+#define QSERDES_COM_CML_SYSCLK_SEL	(QSERDES_QMP_PLL + 0x98)
+#define QSERDES_COM_CMN_CONFIG	(QSERDES_QMP_PLL + 0x17C)
+#define QSERDES_COM_CMN_IETRIM	(QSERDES_QMP_PLL + 0x5C)
+#define QSERDES_COM_CMN_IPTRIM	(QSERDES_QMP_PLL + 0x60)
+#define QSERDES_COM_CMN_MISC1	(QSERDES_QMP_PLL + 0x19C)
+#define QSERDES_COM_CMN_MODE	(QSERDES_QMP_PLL + 0x1A0)
+#define QSERDES_COM_CMN_MODE_CONTD	(QSERDES_QMP_PLL + 0x1A4)
+#define QSERDES_COM_CMN_RATE_OVERRIDE	(QSERDES_QMP_PLL + 0x180)
+#define QSERDES_COM_CMN_STATUS	(QSERDES_QMP_PLL + 0x140)
+#define QSERDES_COM_CORE_CLK_EN	(QSERDES_QMP_PLL + 0x174)
+#define QSERDES_COM_CORECLK_DIV_MODE0	(QSERDES_QMP_PLL + 0x168)
+#define QSERDES_COM_CORECLK_DIV_MODE1	(QSERDES_QMP_PLL + 0x16C)
+#define QSERDES_COM_CP_CTRL_MODE0	(QSERDES_QMP_PLL + 0x74)
+#define QSERDES_COM_CP_CTRL_MODE1	(QSERDES_QMP_PLL + 0x78)
+#define QSERDES_COM_DEBUG_BUS0	(QSERDES_QMP_PLL + 0x188)
+#define QSERDES_COM_DEBUG_BUS1	(QSERDES_QMP_PLL + 0x18C)
+#define QSERDES_COM_DEBUG_BUS2	(QSERDES_QMP_PLL + 0x190)
+#define QSERDES_COM_DEBUG_BUS3	(QSERDES_QMP_PLL + 0x194)
+#define QSERDES_COM_DEBUG_BUS_SEL	(QSERDES_QMP_PLL + 0x198)
+#define QSERDES_COM_DEC_START_MODE0	(QSERDES_QMP_PLL + 0xBC)
+#define QSERDES_COM_DEC_START_MODE1	(QSERDES_QMP_PLL + 0xC4)
+#define QSERDES_COM_DEC_START_MSB_MODE0	(QSERDES_QMP_PLL + 0xC0)
+#define QSERDES_COM_DEC_START_MSB_MODE1	(QSERDES_QMP_PLL + 0xC8)
+#define QSERDES_COM_DIV_FRAC_START1_MODE0	(QSERDES_QMP_PLL + 0xCC)
+#define QSERDES_COM_DIV_FRAC_START1_MODE1	(QSERDES_QMP_PLL + 0xD8)
+#define QSERDES_COM_DIV_FRAC_START2_MODE0	(QSERDES_QMP_PLL + 0xD0)
+#define QSERDES_COM_DIV_FRAC_START2_MODE1	(QSERDES_QMP_PLL + 0xDC)
+#define QSERDES_COM_DIV_FRAC_START3_MODE0	(QSERDES_QMP_PLL + 0xD4)
+#define QSERDES_COM_DIV_FRAC_START3_MODE1	(QSERDES_QMP_PLL + 0xE0)
+#define QSERDES_COM_EP_CLOCK_DETECT_CTRL	(QSERDES_QMP_PLL + 0x64)
+#define QSERDES_COM_FREQ_UPDATE	(QSERDES_QMP_PLL + 0x8)
+#define QSERDES_COM_HSCLK_HS_SWITCH_SEL	(QSERDES_QMP_PLL + 0x15C)
+#define QSERDES_COM_HSCLK_SEL	(QSERDES_QMP_PLL + 0x158)
+#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS	(QSERDES_QMP_PLL + 0x160)
+#define QSERDES_COM_INTEGLOOP_EN	(QSERDES_QMP_PLL + 0xE8)
+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0	(QSERDES_QMP_PLL + 0xEC)
+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1	(QSERDES_QMP_PLL + 0xF4)
+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0	(QSERDES_QMP_PLL + 0xF0)
+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1	(QSERDES_QMP_PLL + 0xF8)
+#define QSERDES_COM_INTEGLOOP_INITVAL	(QSERDES_QMP_PLL + 0xE4)
+#define QSERDES_COM_INTEGLOOP_P_PATH_GAIN0	(QSERDES_QMP_PLL + 0xFC)
+#define QSERDES_COM_INTEGLOOP_P_PATH_GAIN1	(QSERDES_QMP_PLL + 0x100)
+#define QSERDES_COM_LOCK_CMP1_MODE0	(QSERDES_QMP_PLL + 0xAC)
+#define QSERDES_COM_LOCK_CMP1_MODE1	(QSERDES_QMP_PLL + 0xB4)
+#define QSERDES_COM_LOCK_CMP2_MODE0	(QSERDES_QMP_PLL + 0xB0)
+#define QSERDES_COM_LOCK_CMP2_MODE1	(QSERDES_QMP_PLL + 0xB8)
+#define QSERDES_COM_LOCK_CMP_CFG	(QSERDES_QMP_PLL + 0xA8)
+#define QSERDES_COM_LOCK_CMP_EN	(QSERDES_QMP_PLL + 0xA4)
+#define QSERDES_COM_MODE_OPERATION_STATUS	(QSERDES_QMP_PLL + 0x1C4)
+#define QSERDES_COM_PLL_ANALOG	(QSERDES_QMP_PLL + 0x164)
+#define QSERDES_COM_PLL_CCTRL_MODE0	(QSERDES_QMP_PLL + 0x84)
+#define QSERDES_COM_PLL_CCTRL_MODE1	(QSERDES_QMP_PLL + 0x88)
+#define QSERDES_COM_PLL_CNTRL	(QSERDES_QMP_PLL + 0x8C)
+#define QSERDES_COM_PLL_EN	(QSERDES_QMP_PLL + 0x54)
+#define QSERDES_COM_PLL_IVCO	(QSERDES_QMP_PLL + 0x58)
+#define QSERDES_COM_PLL_RCTRL_MODE0	(QSERDES_QMP_PLL + 0x7C)
+#define QSERDES_COM_PLL_RCTRL_MODE1	(QSERDES_QMP_PLL + 0x80)
+#define QSERDES_COM_PLLCAL_CODE1_STATUS	(QSERDES_QMP_PLL + 0x14C)
+#define QSERDES_COM_PLLCAL_CODE2_STATUS	(QSERDES_QMP_PLL + 0x150)
+#define QSERDES_COM_POST_DIV	(QSERDES_QMP_PLL + 0x3C)
+#define QSERDES_COM_POST_DIV_MUX	(QSERDES_QMP_PLL + 0x40)
+#define QSERDES_COM_RESERVED_1	(QSERDES_QMP_PLL + 0x1C0)
+#define QSERDES_COM_RESET_SM_STATUS	(QSERDES_QMP_PLL + 0x144)
+#define QSERDES_COM_RESETSM_CNTRL	(QSERDES_QMP_PLL + 0x9C)
+#define QSERDES_COM_RESETSM_CNTRL2	(QSERDES_QMP_PLL + 0xA0)
+#define QSERDES_COM_RESTRIM_CODE_STATUS	(QSERDES_QMP_PLL + 0x148)
+#define QSERDES_COM_SSC_ADJ_PER1	(QSERDES_QMP_PLL + 0x14)
+#define QSERDES_COM_SSC_ADJ_PER2	(QSERDES_QMP_PLL + 0x18)
+#define QSERDES_COM_SSC_EN_CENTER	(QSERDES_QMP_PLL + 0x10)
+#define QSERDES_COM_SSC_PER1	(QSERDES_QMP_PLL + 0x1C)
+#define QSERDES_COM_SSC_PER2	(QSERDES_QMP_PLL + 0x20)
+#define QSERDES_COM_SSC_STEP_SIZE1_MODE0	(QSERDES_QMP_PLL + 0x24)
+#define QSERDES_COM_SSC_STEP_SIZE1_MODE1	(QSERDES_QMP_PLL + 0x30)
+#define QSERDES_COM_SSC_STEP_SIZE2_MODE0	(QSERDES_QMP_PLL + 0x28)
+#define QSERDES_COM_SSC_STEP_SIZE2_MODE1	(QSERDES_QMP_PLL + 0x34)
+#define QSERDES_COM_SSC_STEP_SIZE3_MODE0	(QSERDES_QMP_PLL + 0x2C)
+#define QSERDES_COM_SSC_STEP_SIZE3_MODE1	(QSERDES_QMP_PLL + 0x38)
+#define QSERDES_COM_SVS_MODE_CLK_SEL	(QSERDES_QMP_PLL + 0x184)
+#define QSERDES_COM_SW_RESET	(QSERDES_QMP_PLL + 0x170)
+#define QSERDES_COM_SYS_CLK_CTRL	(QSERDES_QMP_PLL + 0x4C)
+#define QSERDES_COM_SYSCLK_BUF_ENABLE	(QSERDES_QMP_PLL + 0x50)
+#define QSERDES_COM_SYSCLK_DET_COMP_STATUS	(QSERDES_QMP_PLL + 0x68)
+#define QSERDES_COM_SYSCLK_EN_SEL	(QSERDES_QMP_PLL + 0x94)
+#define QSERDES_COM_VCO_DC_LEVEL_CTRL	(QSERDES_QMP_PLL + 0x1A8)
+#define QSERDES_COM_VCO_TUNE1_MODE0	(QSERDES_QMP_PLL + 0x110)
+#define QSERDES_COM_VCO_TUNE1_MODE1	(QSERDES_QMP_PLL + 0x118)
+#define QSERDES_COM_VCO_TUNE2_MODE0	(QSERDES_QMP_PLL + 0x114)
+#define QSERDES_COM_VCO_TUNE2_MODE1	(QSERDES_QMP_PLL + 0x11C)
+#define QSERDES_COM_VCO_TUNE_CTRL	(QSERDES_QMP_PLL + 0x108)
+#define QSERDES_COM_VCO_TUNE_INITVAL1	(QSERDES_QMP_PLL + 0x120)
+#define QSERDES_COM_VCO_TUNE_INITVAL2	(QSERDES_QMP_PLL + 0x124)
+#define QSERDES_COM_VCO_TUNE_MAP	(QSERDES_QMP_PLL + 0x10C)
+#define QSERDES_COM_VCO_TUNE_MAXVAL1	(QSERDES_QMP_PLL + 0x130)
+#define QSERDES_COM_VCO_TUNE_MAXVAL2	(QSERDES_QMP_PLL + 0x134)
+#define QSERDES_COM_VCO_TUNE_MINVAL1	(QSERDES_QMP_PLL + 0x128)
+#define QSERDES_COM_VCO_TUNE_MINVAL2	(QSERDES_QMP_PLL + 0x12C)
+#define QSERDES_COM_VCO_TUNE_TIMER1	(QSERDES_QMP_PLL + 0x138)
+#define QSERDES_COM_VCO_TUNE_TIMER2	(QSERDES_QMP_PLL + 0x13C)
+#define QSERDES_COM_VCOCAL_DEADMAN_CTRL	(QSERDES_QMP_PLL + 0x104)
+
+#define QSERDES_RX	0x600
+#define QSERDES_RX_UCDR_FO_GAIN_HALF	(QSERDES_RX + 0x0)
+#define QSERDES_RX_UCDR_FO_GAIN_QUARTER	(QSERDES_RX + 0x4)
+#define QSERDES_RX_UCDR_FO_GAIN	(QSERDES_RX + 0x8)
+#define QSERDES_RX_UCDR_SO_GAIN_HALF	(QSERDES_RX + 0xC)
+#define QSERDES_RX_UCDR_SO_GAIN_QUARTER	(QSERDES_RX + 0x10)
+#define QSERDES_RX_UCDR_SO_GAIN	(QSERDES_RX + 0x14)
+#define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF	(QSERDES_RX + 0x18)
+#define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER	(QSERDES_RX + 0x1C)
+#define QSERDES_RX_UCDR_SVS_FO_GAIN	(QSERDES_RX + 0x20)
+#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF	(QSERDES_RX + 0x24)
+#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER	(QSERDES_RX + 0x28)
+#define QSERDES_RX_UCDR_SVS_SO_GAIN	(QSERDES_RX + 0x2C)
+#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN	(QSERDES_RX + 0x30)
+#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE	(QSERDES_RX + 0x34)
+#define QSERDES_RX_UCDR_FO_TO_SO_DELAY	(QSERDES_RX + 0x38)
+#define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW	(QSERDES_RX + 0x3C)
+#define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH	(QSERDES_RX + 0x40)
+#define QSERDES_RX_UCDR_PI_CONTROLS	(QSERDES_RX + 0x44)
+#define QSERDES_RX_UCDR_PI_CTRL2	(QSERDES_RX + 0x48)
+#define QSERDES_RX_UCDR_SB2_THRESH1	(QSERDES_RX + 0x4C)
+#define QSERDES_RX_UCDR_SB2_THRESH2	(QSERDES_RX + 0x50)
+#define QSERDES_RX_UCDR_SB2_GAIN1	(QSERDES_RX + 0x54)
+#define QSERDES_RX_UCDR_SB2_GAIN2	(QSERDES_RX + 0x58)
+#define QSERDES_RX_AUX_CONTROL	(QSERDES_RX + 0x5C)
+#define QSERDES_RX_AUX_DATA_TCOARSE_TFINE	(QSERDES_RX + 0x60)
+#define QSERDES_RX_RCLK_AUXDATA_SEL	(QSERDES_RX + 0x64)
+#define QSERDES_RX_AC_JTAG_ENABLE	(QSERDES_RX + 0x68)
+#define QSERDES_RX_AC_JTAG_INITP	(QSERDES_RX + 0x6C)
+#define QSERDES_RX_AC_JTAG_INITN	(QSERDES_RX + 0x70)
+#define QSERDES_RX_AC_JTAG_LVL	(QSERDES_RX + 0x74)
+#define QSERDES_RX_AC_JTAG_MODE	(QSERDES_RX + 0x78)
+#define QSERDES_RX_AC_JTAG_RESET	(QSERDES_RX + 0x7C)
+#define QSERDES_RX_RX_TERM_BW	(QSERDES_RX + 0x80)
+#define QSERDES_RX_RX_RCVR_IQ_EN	(QSERDES_RX + 0x84)
+#define QSERDES_RX_RX_IDAC_I_DC_OFFSETS	(QSERDES_RX + 0x88)
+#define QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS	(QSERDES_RX + 0x8C)
+#define QSERDES_RX_RX_IDAC_Q_DC_OFFSETS	(QSERDES_RX + 0x90)
+#define QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS	(QSERDES_RX + 0x94)
+#define QSERDES_RX_RX_IDAC_A_DC_OFFSETS	(QSERDES_RX + 0x98)
+#define QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS	(QSERDES_RX + 0x9C)
+#define QSERDES_RX_RX_IDAC_EN	(QSERDES_RX + 0xA0)
+#define QSERDES_RX_RX_IDAC_ENABLES	(QSERDES_RX + 0xA4)
+#define QSERDES_RX_RX_IDAC_SIGN	(QSERDES_RX + 0xA8)
+#define QSERDES_RX_RX_HIGHZ_HIGHRATE	(QSERDES_RX + 0xAC)
+#define QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET	(QSERDES_RX + 0xB0)
+#define QSERDES_RX_DFE_1	(QSERDES_RX + 0xB4)
+#define QSERDES_RX_DFE_2	(QSERDES_RX + 0xB8)
+#define QSERDES_RX_DFE_3	(QSERDES_RX + 0xBC)
+#define QSERDES_RX_DFE_4	(QSERDES_RX + 0xC0)
+#define QSERDES_RX_TX_ADAPT_PRE_THRESH1	(QSERDES_RX + 0xC4)
+#define QSERDES_RX_TX_ADAPT_PRE_THRESH2	(QSERDES_RX + 0xC8)
+#define QSERDES_RX_TX_ADAPT_POST_THRESH	(QSERDES_RX + 0xCC)
+#define QSERDES_RX_TX_ADAPT_MAIN_THRESH	(QSERDES_RX + 0xD0)
+#define QSERDES_RX_VGA_CAL_CNTRL1	(QSERDES_RX + 0xD4)
+#define QSERDES_RX_VGA_CAL_CNTRL2	(QSERDES_RX + 0xD8)
+#define QSERDES_RX_GM_CAL	(QSERDES_RX + 0xDC)
+#define QSERDES_RX_RX_VGA_GAIN2_LSB	(QSERDES_RX + 0xE0)
+#define QSERDES_RX_RX_VGA_GAIN2_MSB	(QSERDES_RX + 0xE4)
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1	(QSERDES_RX + 0xE8)
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2	(QSERDES_RX + 0xEC)
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3	(QSERDES_RX + 0xF0)
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4	(QSERDES_RX + 0xF4)
+#define QSERDES_RX_RX_IDAC_TSETTLE_LOW	(QSERDES_RX + 0xF8)
+#define QSERDES_RX_RX_IDAC_TSETTLE_HIGH	(QSERDES_RX + 0xFC)
+#define QSERDES_RX_RX_IDAC_MEASURE_TIME	(QSERDES_RX + 0x100)
+#define QSERDES_RX_RX_IDAC_ACCUMULATOR	(QSERDES_RX + 0x104)
+#define QSERDES_RX_RX_EQ_OFFSET_LSB	(QSERDES_RX + 0x108)
+#define QSERDES_RX_RX_EQ_OFFSET_MSB	(QSERDES_RX + 0x10C)
+#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	(QSERDES_RX + 0x110)
+#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2	(QSERDES_RX + 0x114)
+#define QSERDES_RX_SIGDET_ENABLES	(QSERDES_RX + 0x118)
+#define QSERDES_RX_SIGDET_CNTRL	(QSERDES_RX + 0x11C)
+#define QSERDES_RX_SIGDET_LVL	(QSERDES_RX + 0x120)
+#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL	(QSERDES_RX + 0x124)
+#define QSERDES_RX_RX_BAND	(QSERDES_RX + 0x128)
+#define QSERDES_RX_CDR_FREEZE_UP_DN	(QSERDES_RX + 0x12C)
+#define QSERDES_RX_CDR_RESET_OVERRIDE	(QSERDES_RX + 0x130)
+#define QSERDES_RX_RX_INTERFACE_MODE	(QSERDES_RX + 0x134)
+#define QSERDES_RX_JITTER_GEN_MODE	(QSERDES_RX + 0x138)
+#define QSERDES_RX_SJ_AMP1	(QSERDES_RX + 0x13C)
+#define QSERDES_RX_SJ_AMP2	(QSERDES_RX + 0x140)
+#define QSERDES_RX_SJ_PER1	(QSERDES_RX + 0x144)
+#define QSERDES_RX_SJ_PER2	(QSERDES_RX + 0x148)
+#define QSERDES_RX_PPM_OFFSET1	(QSERDES_RX + 0x14C)
+#define QSERDES_RX_PPM_OFFSET2	(QSERDES_RX + 0x150)
+#define QSERDES_RX_SIGN_PPM_PERIOD1	(QSERDES_RX + 0x154)
+#define QSERDES_RX_SIGN_PPM_PERIOD2	(QSERDES_RX + 0x158)
+#define QSERDES_RX_RX_MODE_00_LOW	(QSERDES_RX + 0x15C)
+#define QSERDES_RX_RX_MODE_00_HIGH	(QSERDES_RX + 0x160)
+#define QSERDES_RX_RX_MODE_00_HIGH2	(QSERDES_RX + 0x164)
+#define QSERDES_RX_RX_MODE_00_HIGH3	(QSERDES_RX + 0x168)
+#define QSERDES_RX_RX_MODE_00_HIGH4	(QSERDES_RX + 0x16C)
+#define QSERDES_RX_RX_MODE_01_LOW	(QSERDES_RX + 0x170)
+#define QSERDES_RX_RX_MODE_01_HIGH	(QSERDES_RX + 0x174)
+#define QSERDES_RX_RX_MODE_01_HIGH2	(QSERDES_RX + 0x178)
+#define QSERDES_RX_RX_MODE_01_HIGH3	(QSERDES_RX + 0x17C)
+#define QSERDES_RX_RX_MODE_01_HIGH4	(QSERDES_RX + 0x180)
+#define QSERDES_RX_RX_MODE_10_LOW	(QSERDES_RX + 0x184)
+#define QSERDES_RX_RX_MODE_10_HIGH	(QSERDES_RX + 0x188)
+#define QSERDES_RX_RX_MODE_10_HIGH2	(QSERDES_RX + 0x18C)
+#define QSERDES_RX_RX_MODE_10_HIGH3	(QSERDES_RX + 0x190)
+#define QSERDES_RX_RX_MODE_10_HIGH4	(QSERDES_RX + 0x194)
+#define QSERDES_RX_PHPRE_CTRL	(QSERDES_RX + 0x198)
+#define QSERDES_RX_PHPRE_INITVAL	(QSERDES_RX + 0x19C)
+#define QSERDES_RX_DFE_EN_TIMER	(QSERDES_RX + 0x1A0)
+#define QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	(QSERDES_RX + 0x1A4)
+#define QSERDES_RX_DCC_CTRL1	(QSERDES_RX + 0x1A8)
+#define QSERDES_RX_DCC_CTRL2	(QSERDES_RX + 0x1AC)
+#define QSERDES_RX_VTH_CODE	(QSERDES_RX + 0x1B0)
+#define QSERDES_RX_VTH_MIN_THRESH	(QSERDES_RX + 0x1B4)
+#define QSERDES_RX_VTH_MAX_THRESH	(QSERDES_RX + 0x1B8)
+#define QSERDES_RX_ALOG_OBSV_BUS_CTRL_1	(QSERDES_RX + 0x1BC)
+#define QSERDES_RX_PI_CTRL1	(QSERDES_RX + 0x1C0)
+#define QSERDES_RX_PI_CTRL2	(QSERDES_RX + 0x1C4)
+#define QSERDES_RX_PI_QUAD	(QSERDES_RX + 0x1C8)
+#define QSERDES_RX_IDATA1	(QSERDES_RX + 0x1CC)
+#define QSERDES_RX_IDATA2	(QSERDES_RX + 0x1D0)
+#define QSERDES_RX_AUX_DATA1	(QSERDES_RX + 0x1D4)
+#define QSERDES_RX_AUX_DATA2	(QSERDES_RX + 0x1D8)
+#define QSERDES_RX_AC_JTAG_OUTP	(QSERDES_RX + 0x1DC)
+#define QSERDES_RX_AC_JTAG_OUTN	(QSERDES_RX + 0x1E0)
+#define QSERDES_RX_RX_SIGDET	(QSERDES_RX + 0x1E4)
+#define QSERDES_RX_ALOG_OBSV_BUS_STATUS_1	(QSERDES_RX + 0x1E8)
+
+#define QSERDES_TX	0x400
+#define QSERDES_TX_BIST_MODE_LANENO	(QSERDES_TX + 0x0)
+#define QSERDES_TX_BIST_INVERT	(QSERDES_TX + 0x4)
+#define QSERDES_TX_CLKBUF_ENABLE	(QSERDES_TX + 0x8)
+#define QSERDES_TX_TX_EMP_POST1_LVL	(QSERDES_TX + 0xC)
+#define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP	(QSERDES_TX + 0x10)
+#define QSERDES_TX_TX_DRV_LVL	(QSERDES_TX + 0x14)
+#define QSERDES_TX_TX_DRV_LVL_OFFSET	(QSERDES_TX + 0x18)
+#define QSERDES_TX_RESET_TSYNC_EN	(QSERDES_TX + 0x1C)
+#define QSERDES_TX_PRE_STALL_LDO_BOOST_EN	(QSERDES_TX + 0x20)
+#define QSERDES_TX_TX_BAND	(QSERDES_TX + 0x24)
+#define QSERDES_TX_SLEW_CNTL	(QSERDES_TX + 0x28)
+#define QSERDES_TX_INTERFACE_SELECT	(QSERDES_TX + 0x2C)
+#define QSERDES_TX_LPB_EN	(QSERDES_TX + 0x30)
+#define QSERDES_TX_RES_CODE_LANE_TX	(QSERDES_TX + 0x34)
+#define QSERDES_TX_RES_CODE_LANE_RX	(QSERDES_TX + 0x38)
+#define QSERDES_TX_RES_CODE_LANE_OFFSET_TX	(QSERDES_TX + 0x3C)
+#define QSERDES_TX_RES_CODE_LANE_OFFSET_RX	(QSERDES_TX + 0x40)
+#define QSERDES_TX_PERL_LENGTH1	(QSERDES_TX + 0x44)
+#define QSERDES_TX_PERL_LENGTH2	(QSERDES_TX + 0x48)
+#define QSERDES_TX_SERDES_BYP_EN_OUT	(QSERDES_TX + 0x4C)
+#define QSERDES_TX_DEBUG_BUS_SEL	(QSERDES_TX + 0x50)
+#define QSERDES_TX_TRANSCEIVER_BIAS_EN	(QSERDES_TX + 0x54)
+#define QSERDES_TX_HIGHZ_DRVR_EN	(QSERDES_TX + 0x58)
+#define QSERDES_TX_TX_POL_INV	(QSERDES_TX + 0x5C)
+#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN	(QSERDES_TX + 0x60)
+#define QSERDES_TX_BIST_PATTERN1	(QSERDES_TX + 0x64)
+#define QSERDES_TX_BIST_PATTERN2	(QSERDES_TX + 0x68)
+#define QSERDES_TX_BIST_PATTERN3	(QSERDES_TX + 0x6C)
+#define QSERDES_TX_BIST_PATTERN4	(QSERDES_TX + 0x70)
+#define QSERDES_TX_BIST_PATTERN5	(QSERDES_TX + 0x74)
+#define QSERDES_TX_BIST_PATTERN6	(QSERDES_TX + 0x78)
+#define QSERDES_TX_BIST_PATTERN7	(QSERDES_TX + 0x7C)
+#define QSERDES_TX_BIST_PATTERN8	(QSERDES_TX + 0x80)
+#define QSERDES_TX_LANE_MODE_1	(QSERDES_TX + 0x84)
+#define QSERDES_TX_LANE_MODE_2	(QSERDES_TX + 0x88)
+#define QSERDES_TX_LANE_MODE_3	(QSERDES_TX + 0x8C)
+#define QSERDES_TX_LANE_MODE_4	(QSERDES_TX + 0x90)
+#define QSERDES_TX_LANE_MODE_5	(QSERDES_TX + 0x94)
+#define QSERDES_TX_ATB_SEL1	(QSERDES_TX + 0x98)
+#define QSERDES_TX_ATB_SEL2	(QSERDES_TX + 0x9C)
+#define QSERDES_TX_RCV_DETECT_LVL	(QSERDES_TX + 0xA0)
+#define QSERDES_TX_RCV_DETECT_LVL_2	(QSERDES_TX + 0xA4)
+#define QSERDES_TX_PRBS_SEED1	(QSERDES_TX + 0xA8)
+#define QSERDES_TX_PRBS_SEED2	(QSERDES_TX + 0xAC)
+#define QSERDES_TX_PRBS_SEED3	(QSERDES_TX + 0xB0)
+#define QSERDES_TX_PRBS_SEED4	(QSERDES_TX + 0xB4)
+#define QSERDES_TX_RESET_GEN	(QSERDES_TX + 0xB8)
+#define QSERDES_TX_RESET_GEN_MUXES	(QSERDES_TX + 0xBC)
+#define QSERDES_TX_TRAN_DRVR_EMP_EN	(QSERDES_TX + 0xC0)
+#define QSERDES_TX_TX_INTERFACE_MODE	(QSERDES_TX + 0xC4)
+#define QSERDES_TX_VMODE_CTRL1	(QSERDES_TX + 0xC8)
+#define QSERDES_TX_ALOG_OBSV_BUS_CTRL_1	(QSERDES_TX + 0xCC)
+#define QSERDES_TX_BIST_STATUS	(QSERDES_TX + 0xD0)
+#define QSERDES_TX_BIST_ERROR_COUNT1	(QSERDES_TX + 0xD4)
+#define QSERDES_TX_BIST_ERROR_COUNT2	(QSERDES_TX + 0xD8)
+#define QSERDES_TX_ALOG_OBSV_BUS_STATUS_1	(QSERDES_TX + 0xDC)
+#define QSERDES_TX_LANE_DIG_CONFIG	(QSERDES_TX + 0xE0)
+#define QSERDES_TX_PI_QEC_CTRL	(QSERDES_TX + 0xE4)
+#define QSERDES_TX_PRE_EMPH	(QSERDES_TX + 0xE8)
+#define QSERDES_TX_SW_RESET	(QSERDES_TX + 0xEC)
+#define QSERDES_TX_DCC_OFFSET	(QSERDES_TX + 0xF0)
+#define QSERDES_TX_DCC_CMUX_POSTCAL_OFFSET	(QSERDES_TX + 0xF4)
+#define QSERDES_TX_DCC_CMUX_CAL_CTRL1	(QSERDES_TX + 0xF8)
+#define QSERDES_TX_DCC_CMUX_CAL_CTRL2	(QSERDES_TX + 0xFC)
+#define QSERDES_TX_DIG_BKUP_CTRL	(QSERDES_TX + 0x100)
+#define QSERDES_TX_DEBUG_BUS0	(QSERDES_TX + 0x104)
+#define QSERDES_TX_DEBUG_BUS1	(QSERDES_TX + 0x108)
+#define QSERDES_TX_DEBUG_BUS2	(QSERDES_TX + 0x10C)
+#define QSERDES_TX_DEBUG_BUS3	(QSERDES_TX + 0x110)
+#define QSERDES_TX_READ_EQCODE	(QSERDES_TX + 0x114)
+#define QSERDES_TX_READ_OFFSETCODE	(QSERDES_TX + 0x118)
+#define QSERDES_TX_IA_ERROR_COUNTER_LOW	(QSERDES_TX + 0x11C)
+#define QSERDES_TX_IA_ERROR_COUNTER_HIGH	(QSERDES_TX + 0x120)
+#define QSERDES_TX_VGA_READ_CODE	(QSERDES_TX + 0x124)
+#define QSERDES_TX_VTH_READ_CODE	(QSERDES_TX + 0x128)
+#define QSERDES_TX_DFE_TAP1_READ_CODE	(QSERDES_TX + 0x12C)
+#define QSERDES_TX_DFE_TAP2_READ_CODE	(QSERDES_TX + 0x130)
+#define QSERDES_TX_IDAC_STATUS_I	(QSERDES_TX + 0x134)
+#define QSERDES_TX_IDAC_STATUS_IBAR	(QSERDES_TX + 0x138)
+#define QSERDES_TX_IDAC_STATUS_Q	(QSERDES_TX + 0x13C)
+#define QSERDES_TX_IDAC_STATUS_QBAR	(QSERDES_TX + 0x140)
+#define QSERDES_TX_IDAC_STATUS_A	(QSERDES_TX + 0x144)
+#define QSERDES_TX_IDAC_STATUS_ABAR	(QSERDES_TX + 0x148)
+#define QSERDES_TX_IDAC_STATUS_SM_ON	(QSERDES_TX + 0x14C)
+#define QSERDES_TX_IDAC_STATUS_CAL_DONE	(QSERDES_TX + 0x150)
+#define QSERDES_TX_IDAC_STATUS_SIGNERROR	(QSERDES_TX + 0x154)
+#define QSERDES_TX_DCC_CAL_STATUS	(QSERDES_TX + 0x158)
+#define QSERDES_TX_DCC_READ_CODE_STATUS	(QSERDES_TX + 0x15C)
+
+#define QSERDES_PCS	0xC00
+#define QSERDES_PCS_PHY_START (QSERDES_PCS + 0x0)
+#define QSERDES_PCS_POWER_DOWN_CONTROL (QSERDES_PCS + 0x4)
+#define QSERDES_PCS_SW_RESET (QSERDES_PCS + 0x8)
+#define QSERDES_PCS_LINE_RESET_TIME (QSERDES_PCS + 0xC)
+#define QSERDES_PCS_PCS_CTRL1 (QSERDES_PCS + 0x10)
+#define QSERDES_PCS_TSYNC_RSYNC_CNTL (QSERDES_PCS + 0x14)
+#define QSERDES_PCS_RETIME_BUFFER_EN (QSERDES_PCS + 0x18)
+#define QSERDES_PCS_PLL_CNTL (QSERDES_PCS + 0x1C)
+#define QSERDES_PCS_TX_LARGE_AMP_DRV_LVL (QSERDES_PCS + 0x20)
+#define QSERDES_PCS_TX_LARGE_AMP_POST_EMP_LVL (QSERDES_PCS + 0x24)
+#define QSERDES_PCS_TX_SMALL_AMP_DRV_LVL (QSERDES_PCS + 0x28)
+#define QSERDES_PCS_TX_SMALL_AMP_POST_EMP_LVL (QSERDES_PCS + 0x2C)
+#define QSERDES_PCS_RX_SYNC_WAIT_TIME (QSERDES_PCS + 0x30)
+#define QSERDES_PCS_L0_BIST_CTRL (QSERDES_PCS + 0x34)
+#define QSERDES_PCS_MISC_BIST_CTRL (QSERDES_PCS + 0x38)
+#define QSERDES_PCS_BIST_PRBS_POLY0 (QSERDES_PCS + 0x3C)
+#define QSERDES_PCS_BIST_PRBS_POLY1 (QSERDES_PCS + 0x40)
+#define QSERDES_PCS_BIST_PRBS_SEED0 (QSERDES_PCS + 0x44)
+#define QSERDES_PCS_BIST_PRBS_SEED1 (QSERDES_PCS + 0x48)
+#define QSERDES_PCS_BIST_PRBS_SEED2 (QSERDES_PCS + 0x4C)
+#define QSERDES_PCS_BIST_NUM_IPG (QSERDES_PCS + 0x50)
+#define QSERDES_PCS_RX_HS_EQUALIZER_SETTING_CAPABILITY (QSERDES_PCS + 0x54)
+#define QSERDES_PCS_RX_HS_ADAPT_LENGTH_REFRESH_CAPABILITY (QSERDES_PCS + 0x58)
+#define QSERDES_PCS_RX_HS_ADAPT_LENGTH_INITIAL_CAPABILITY (QSERDES_PCS + 0x5C)
+#define QSERDES_PCS_DEBUG_BUS_CLKSEL (QSERDES_PCS + 0x60)
+#define QSERDES_PCS_DEBUG_BUS_0_CTRL (QSERDES_PCS + 0x64)
+#define QSERDES_PCS_DEBUG_BUS_1_CTRL (QSERDES_PCS + 0x68)
+#define QSERDES_PCS_DEBUG_BUS_2_CTRL (QSERDES_PCS + 0x6C)
+#define QSERDES_PCS_DEBUG_BUS_3_CTRL (QSERDES_PCS + 0x70)
+#define QSERDES_PCS_DEBUG_BUS_0_STATUS_CHK (QSERDES_PCS + 0x74)
+#define QSERDES_PCS_DEBUG_BUS_1_STATUS_CHK (QSERDES_PCS + 0x78)
+#define QSERDES_PCS_DEBUG_BUS_2_STATUS_CHK (QSERDES_PCS + 0x7C)
+#define QSERDES_PCS_DEBUG_BUS_3_STATUS_CHK (QSERDES_PCS + 0x80)
+#define QSERDES_PCS_RX_MIN_HIBERN8_TIME (QSERDES_PCS + 0x84)
+#define QSERDES_PCS_RX_SIGDET_CTRL1 (QSERDES_PCS + 0x88)
+#define QSERDES_PCS_RX_SIGDET_CTRL2 (QSERDES_PCS + 0x8C)
+#define QSERDES_PCS_TCLK_SYM_CNTR_INITVAL (QSERDES_PCS + 0x90)
+#define QSERDES_PCS_PCS_READY_STATUS (QSERDES_PCS + 0x94)
+#define QSERDES_PCS_PCS_MISC_STATUS (QSERDES_PCS + 0x98)
+#define QSERDES_PCS_L0_BIST_CHK_ERR_CNT_L_STATUS (QSERDES_PCS + 0x9C)
+#define QSERDES_PCS_L0_BIST_CHK_ERR_CNT_H_STATUS (QSERDES_PCS + 0xA0)
+#define QSERDES_PCS_L0_BIST_CHK_STATUS (QSERDES_PCS + 0xA4)
+#define QSERDES_PCS_DEBUG_BUS_0_STATUS (QSERDES_PCS + 0xA8)
+#define QSERDES_PCS_DEBUG_BUS_1_STATUS (QSERDES_PCS + 0xAC)
+#define QSERDES_PCS_DEBUG_BUS_2_STATUS (QSERDES_PCS + 0xB0)
+#define QSERDES_PCS_DEBUG_BUS_3_STATUS (QSERDES_PCS + 0xB4)
+#define QSERDES_PCS_REVISION_ID0 (QSERDES_PCS + 0xB8)
+#define QSERDES_PCS_REVISION_ID1 (QSERDES_PCS + 0xBC)
+#define QSERDES_PCS_REVISION_ID2 (QSERDES_PCS + 0xC0)
+#define QSERDES_PCS_REVISION_ID3 (QSERDES_PCS + 0xC4)
+#define QSERDES_PCS_SYSCLK_EN_COUNT_CTRL (QSERDES_PCS + 0xC8)
+#define QSERDES_PCS_PLL_SHUTDOWN_CTRL (QSERDES_PCS + 0xCC)
+#define QSERDES_PCS_TIMER_20US_CORECLK_STEPS_MSB (QSERDES_PCS + 0xD0)
+#define QSERDES_PCS_TIMER_20US_CORECLK_STEPS_LSB (QSERDES_PCS + 0xD4)
+#define QSERDES_PCS_TX_MID_TERM_CTRL1 (QSERDES_PCS + 0xD8)
+#define QSERDES_PCS_TX_MID_TERM_CTRL2 (QSERDES_PCS + 0xDC)
+#define QSERDES_PCS_MULTI_LANE_CTRL1 (QSERDES_PCS + 0xE0)
+#define QSERDES_PCS_L1_BIST_CTRL (QSERDES_PCS + 0xE4)
+#define QSERDES_PCS_L1_BIST_CHK_ERR_CNT_L_STATUS (QSERDES_PCS + 0xE8)
+#define QSERDES_PCS_L1_BIST_CHK_ERR_CNT_H_STATUS (QSERDES_PCS + 0xEC)
+#define QSERDES_PCS_L1_BIST_CHK_STATUS (QSERDES_PCS + 0xF0)
+#define QSERDES_PCS_STATUS_CLEAR (QSERDES_PCS + 0xF4)
+#define QSERDES_PCS_RX_HSG4_SYNC_WAIT_TIME (QSERDES_PCS + 0xF8)
+#define QSERDES_PCS_SGMII_MISC_CTRL1 (QSERDES_PCS + 0xFC)
+#define QSERDES_PCS_SGMII_MISC_CTRL2 (QSERDES_PCS + 0x100)
+#define QSERDES_PCS_SGMII_MISC_CTRL3 (QSERDES_PCS + 0x104)
+#define QSERDES_PCS_SGMII_MISC_CTRL4 (QSERDES_PCS + 0x108)
+#define QSERDES_PCS_SGMII_MISC_CTRL5 (QSERDES_PCS + 0x10C)
+#define QSERDES_PCS_SGMII_MISC_CTRL6 (QSERDES_PCS + 0x110)
+#define QSERDES_PCS_SGMII_MISC_CTRL7 (QSERDES_PCS + 0x114)
+#define QSERDES_PCS_SGMII_MISC_CTRL8 (QSERDES_PCS + 0x118)
+#define QSERDES_PCS_SGMII_INTERRUPT_STATUS (QSERDES_PCS + 0x11C)
+#define QSERDES_PCS_SGMII_IRQ_CLEAR (QSERDES_PCS + 0x120)
+#define QSERDES_PCS_SGMII_IRQ_MASK (QSERDES_PCS + 0x124)
+
+#define QSERDES_PCS_2	0x200
+#define QSERDES_PCS2_PCS_CMN_STATUS (QSERDES_PCS_2 + 0x0)
+#define QSERDES_PCS2_TCLK_CTRL_STATUS (QSERDES_PCS_2 + 0x4)
+#define QSERDES_PCS2_TX_LANE0_0_STATUS (QSERDES_PCS_2 + 0x8)
+#define QSERDES_PCS2_TX_LANE0_1_STATUS (QSERDES_PCS_2 + 0xC)
+#define QSERDES_PCS2_TX_LANE0_2_STATUS (QSERDES_PCS_2 + 0x10)
+#define QSERDES_PCS2_RX_LANE0_0_STATUS (QSERDES_PCS_2 + 0x14)
+#define QSERDES_PCS2_RX_LANE0_1_STATUS (QSERDES_PCS_2 + 0x18)
+#define QSERDES_PCS2_RX_LANE0_3_STATUS (QSERDES_PCS_2 + 0x1C)
+#define QSERDES_PCS2_TX_LANE1_0_STATUS (QSERDES_PCS_2 + 0x20)
+#define QSERDES_PCS2_TX_LANE1_1_STATUS (QSERDES_PCS_2 + 0x24)
+#define QSERDES_PCS2_TX_LANE1_2_STATUS (QSERDES_PCS_2 + 0x28)
+#define QSERDES_PCS2_RX_LANE1_0_STATUS (QSERDES_PCS_2 + 0x2C)
+#define QSERDES_PCS2_RX_LANE1_1_STATUS (QSERDES_PCS_2 + 0x30)
+#define QSERDES_PCS2_RX_LANE1_3_STATUS (QSERDES_PCS_2 + 0x34)
+
+int configure_serdes_dt(struct qcom_ethqos *ethqos);
+void qcom_ethqos_serdes_init(struct qcom_ethqos *ethqos, int speed);
+#endif
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 2dbc4a41d1e87..fcdcf633a39aa 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -5736,7 +5736,7 @@ static void stmmac_common_interrupt(struct stmmac_priv *priv)
 		}
 
 		/* PCS link status */
-		if (priv->hw->pcs) {
+		if (priv->hw->pcs && priv->hw->pcs != STMMAC_PCS_SGMII) {
 			if (priv->xstats.pcs_link)
 				netif_carrier_on(priv->dev);
 			else