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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DWMAC_QCOM_ETHQOS_H
#define _DWMAC_QCOM_ETHQOS_H
#define DRV_NAME "qcom-ethqos"
#define ETHQOSDBG(fmt, args...) \
pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args)
#define ETHQOSERR(fmt, args...) \
pr_err(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args)
#define ETHQOSINFO(fmt, args...) \
pr_info(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args)
#define RGMII_IO_MACRO_CONFIG 0x0
#define SDCC_HC_REG_DLL_CONFIG 0x4
#define SDCC_TEST_CTL 0x8
#define SDCC_HC_REG_DDR_CONFIG 0xC
#define SDCC_HC_REG_DLL_CONFIG2 0x10
#define SDC4_STATUS 0x14
#define SDCC_USR_CTL 0x18
#define RGMII_IO_MACRO_CONFIG2 0x1C
#define EMAC_HW_NONE 0
#define ETHQOS_CONFIG_PPSOUT_CMD 44
#define ETHQOS_AVB_ALGORITHM 27
#define MAC_PPS_CONTROL 0x00000b70
#define PPS_MAXIDX(x) ((((x) + 1) * 8) - 1)
#define PPS_MINIDX(x) ((x) * 8)
#define MCGRENX(x) BIT(PPS_MAXIDX(x))
#define PPSEN0 BIT(4)
#define MAC_PPSX_TARGET_TIME_SEC(x) (0x00000b80 + ((x) * 0x10))
#define MAC_PPSX_TARGET_TIME_NSEC(x) (0x00000b84 + ((x) * 0x10))
#define TRGTBUSY0 BIT(31)
#define TTSL0 GENMASK(30, 0)
#define MAC_PPSX_INTERVAL(x) (0x00000b88 + ((x) * 0x10))
#define MAC_PPSX_WIDTH(x) (0x00000b8c + ((x) * 0x10))
#define DWC_ETH_QOS_PPS_CH_2 2
#define DWC_ETH_QOS_PPS_CH_3 3
#define AVB_CLASS_A_POLL_DEV_NODE "avb_class_a_intr"
#define AVB_CLASS_B_POLL_DEV_NODE "avb_class_b_intr"
#define AVB_CLASS_A_CHANNEL_NUM 2
#define AVB_CLASS_B_CHANNEL_NUM 3
#define PPS_19_2_FREQ 19200000
static inline u32 PPSCMDX(u32 x, u32 val)
{
return (GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) &
((val) << PPS_MINIDX(x)));
}
static inline u32 TRGTMODSELX(u32 x, u32 val)
{
return (GENMASK(PPS_MAXIDX(x) - 1, PPS_MAXIDX(x) - 2) &
((val) << (PPS_MAXIDX(x) - 2)));
}
static inline u32 PPSX_MASK(u32 x)
{
return GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x));
}
struct ethqos_emac_por {
unsigned int offset;
unsigned int value;
};
struct ethqos_emac_driver_data {
struct ethqos_emac_por *por;
unsigned int num_por;
};
struct qcom_ethqos {
struct platform_device *pdev;
void __iomem *rgmii_base;
unsigned int rgmii_clk_rate;
struct clk *rgmii_clk;
unsigned int speed;
int gpio_phy_intr_redirect;
u32 phy_intr;
/* Work struct for handling phy interrupt */
struct work_struct emac_phy_work;
struct ethqos_emac_por *por;
unsigned int num_por;
unsigned int emac_ver;
struct regulator *reg_rgmii;
struct regulator *reg_emac_phy;
struct regulator *reg_rgmii_io_pads;
struct dentry *debugfs_dir;
int pps_class_a_irq;
int pps_class_b_irq;
struct pinctrl_state *emac_pps_0;
/* avb_class_a dev node variables*/
dev_t avb_class_a_dev_t;
struct cdev *avb_class_a_cdev;
struct class *avb_class_a_class;
/* avb_class_b dev node variables*/
dev_t avb_class_b_dev_t;
struct cdev *avb_class_b_cdev;
struct class *avb_class_b_class;
unsigned long avb_class_a_intr_cnt;
unsigned long avb_class_b_intr_cnt;
};
struct pps_cfg {
unsigned int ptpclk_freq;
unsigned int ppsout_freq;
unsigned int ppsout_ch;
unsigned int ppsout_duty;
unsigned int ppsout_start;
};
struct ifr_data_struct {
unsigned int flags;
unsigned int qinx; /* dma channel no to be configured */
unsigned int cmd;
unsigned int context_setup;
unsigned int connected_speed;
unsigned int rwk_filter_values[8];
unsigned int rwk_filter_length;
int command_error;
int test_done;
void *ptr;
};
struct pps_info {
int channel_no;
};
int ethqos_init_reqgulators(struct qcom_ethqos *ethqos);
void ethqos_disable_regulators(struct qcom_ethqos *ethqos);
int ethqos_init_gpio(struct qcom_ethqos *ethqos);
void ethqos_free_gpios(struct qcom_ethqos *ethqos);
void *qcom_ethqos_get_priv(struct qcom_ethqos *ethqos);
int create_pps_interrupt_device_node(dev_t *pps_dev_t,
struct cdev **pps_cdev,
struct class **pps_class,
char *pps_dev_node_name);
void ethqos_remove_pps_dev(struct qcom_ethqos *ethqos);
int ppsout_config(struct stmmac_priv *priv, struct pps_cfg *eth_pps_cfg);
int ethqos_init_pps(void *priv_n);
struct qcom_ethqos *get_pethqos(void);
#define QTAG_VLAN_ETH_TYPE_OFFSET 16
#define QTAG_UCP_FIELD_OFFSET 14
#define QTAG_ETH_TYPE_OFFSET 12
#define PTP_UDP_EV_PORT 0x013F
#define PTP_UDP_GEN_PORT 0x0140
#define IPA_DMA_TX_CH 0
#define IPA_DMA_RX_CH 0
#define VLAN_TAG_UCP_SHIFT 13
#define CLASS_A_TRAFFIC_UCP 3
#define CLASS_A_TRAFFIC_TX_CHANNEL 3
#define CLASS_B_TRAFFIC_UCP 2
#define CLASS_B_TRAFFIC_TX_CHANNEL 2
#define NON_TAGGED_IP_TRAFFIC_TX_CHANNEL 1
#define ALL_OTHER_TRAFFIC_TX_CHANNEL 1
#define ALL_OTHER_TX_TRAFFIC_IPA_DISABLED 0
#define DEFAULT_INT_MOD 1
#define AVB_INT_MOD 8
#define IP_PKT_INT_MOD 32
#define PTP_INT_MOD 1
enum dwmac_qcom_queue_operating_mode {
DWMAC_QCOM_QDISABLED = 0X0,
DWMAC_QCOM_QAVB,
DWMAC_QCOM_QDCB,
DWMAC_QCOM_QGENERIC
};
struct dwmac_qcom_avb_algorithm_params {
unsigned int idle_slope;
unsigned int send_slope;
unsigned int hi_credit;
unsigned int low_credit;
};
struct dwmac_qcom_avb_algorithm {
unsigned int qinx;
unsigned int algorithm;
unsigned int cc;
struct dwmac_qcom_avb_algorithm_params speed100params;
struct dwmac_qcom_avb_algorithm_params speed1000params;
enum dwmac_qcom_queue_operating_mode op_mode;
};
unsigned int dwmac_qcom_get_plat_tx_coal_frames(struct sk_buff *skb);
#endif
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