diff options
| author | Bjorn Andersson <bjorn.andersson@linaro.org> | 2018-10-21 12:15:00 +0530 |
|---|---|---|
| committer | Nicolas Dechesne <nicolas.dechesne@linaro.org> | 2018-11-23 23:00:15 +0100 |
| commit | 253e8c98a95c29d99a1f7f2c2531cc598caf6e56 (patch) | |
| tree | 4ed917bb8b94603d2cac358c508091ec381c5c9c | |
| parent | 695f01b82f475ffb1dfeb135bce0ae54592fad57 (diff) | |
FROMGIT: pcie: dwc: qcom: Add cfg clock to 2.4.0
Change-Id: I6e227b05c5e69d66f293bee7d08c21220bd7b93e
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
(cherry picked from commit d973772060fecaed460e37772084ed9015a3d24d
https://git.linaro.org/people/niklas.cassel/kernel.git/commit/?h=niklas-qcs404-pcie-4.14)
Signed-off-by: Prashanth Vadde <pvadde@codeaurora.org>
Reviewed-on: https://chromium-review.googlesource.com/c/1343763
Reviewed-by: Zhihong Yu <zhihongyu@chromium.org>
Tested-by: Zhihong Yu <zhihongyu@chromium.org>
| -rw-r--r-- | drivers/pci/dwc/pcie-qcom.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c index ce7ba5b7552a..3c3a5d75edb2 100644 --- a/drivers/pci/dwc/pcie-qcom.c +++ b/drivers/pci/dwc/pcie-qcom.c @@ -122,6 +122,7 @@ struct qcom_pcie_resources_2_4_0 { struct clk *aux_clk; struct clk *master_clk; struct clk *slave_clk; + struct clk *cfg_clk; struct reset_control *axi_m_reset; struct reset_control *axi_s_reset; struct reset_control *pipe_reset; @@ -654,6 +655,10 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + res->cfg_clk = devm_clk_get(dev, "cfg"); + if (IS_ERR(res->cfg_clk)) + return PTR_ERR(res->cfg_clk); + res->aux_clk = devm_clk_get(dev, "aux"); if (IS_ERR(res->aux_clk)) return PTR_ERR(res->aux_clk); @@ -737,6 +742,7 @@ static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) clk_disable_unprepare(res->aux_clk); clk_disable_unprepare(res->master_clk); clk_disable_unprepare(res->slave_clk); + clk_disable_unprepare(res->cfg_clk); } static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) @@ -747,6 +753,12 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) u32 val; int ret; + ret = clk_prepare_enable(res->cfg_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable cfg clock\n"); + return ret; + } + ret = reset_control_assert(res->axi_m_reset); if (ret) { dev_err(dev, "cannot assert axi master reset\n"); |