onsuccess: #209: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/209/

Results :
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap_O1:
  | 1

check_regression status : 0

4 files changed, 12 insertions, 12 deletions

diff --git a/notify/jira/comment-template.txt b/notify/jira/comment-template.txt
index fbf3d6b..4da0356 100644
--- a/notify/jira/comment-template.txt
+++ b/notify/jira/comment-template.txt
@@ -1,3 +1,3 @@
 [GNU-692]
 Success
-Details: https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/208/artifact/artifacts/notify/mail-body.txt/*view*/
+Details: https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/209/artifact/artifacts/notify/mail-body.txt/*view*/
diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index 6317cb2..7429fc0 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -2,13 +2,13 @@ Dear contributor, our automatic CI has detected problems related to your patch(e
 
 In bootstrap_build master-arm-bootstrap_O1 after:
 
-  | 40 commits in gcc
-  | c0a70df6403 RISC-V: Support cond vmulh.vv and vmulu.vv autovec patterns
-  | 842e4d51c11 RISC-V: Support cond vnsrl/vnsra autovec patterns
-  | 6737a517288 RISC-V: Support cond vfsgnj.vv autovec patterns
-  | 92ea12ea99f tree-optimization/111397 - missed copy propagation involving abnormal dest
-  | feb23a37e61 RISC-V: Bugfix PR111362 for incorrect frm emit
-  | ... and 35 more commits in gcc
+  | 62 commits in gcc
+  | 0f1f6cf872a aarch64: Coerce addresses to be suitable for LD1RQ
+  | 62b29347c38 libstdc++: Add dg-require-thread-fence in several tests
+  | 53ad1bd5207 RISC-V: Fix ICE in get_avl_or_vl_reg
+  | 7c4f6ebe54f RISC-V: Format VSETVL PASS code
+  | 3acf7e9da39 LoongArch: Change the value of branch_cost from 2 to 6.
+  | ... and 57 more commits in gcc
 
 Results changed to
 # reset_artifacts:
@@ -32,6 +32,6 @@ CI config tcwg_bootstrap_build/master-arm-bootstrap_O1
 -----------------8<--------------------------8<--------------------------8<--------------------------
 The information below can be used to reproduce a debug environment:
 
-Current build   : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/208/artifact/artifacts
-Reference build : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/207/artifact/artifacts
+Current build   : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/209/artifact/artifacts
+Reference build : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/208/artifact/artifacts
 
diff --git a/notify/mail-recipients.txt b/notify/mail-recipients.txt
index 40fa8ba..d2dd651 100644
--- a/notify/mail-recipients.txt
+++ b/notify/mail-recipients.txt
@@ -1 +1 @@
-bcc:tcwg-validation@linaro.org,guojiufu@linux.ibm.com,cc:gcc-regression@gcc.gnu.org,iant@golang.org,jason@redhat.com,cc:juzhe.zhong@rivai.ai,rdapp@ventanamicro.com,mjambor@suse.cz,lehua.ding@rivai.ai,rguenther@suse.de,apinski@marvell.com,gccadmin@gcc.gnu.org,pan2.li@intel.com,ewlu@rivosinc.com,ppalka@redhat.com,richard.sandiford@arm.com
+bcc:tcwg-validation@linaro.org,gaiusmod2@gmail.com,fdumont@gcc.gnu.org,cc:gcc-regression@gcc.gnu.org,cc:jjsuwa_sys3175@yahoo.co.jp,christophe.lyon@linaro.org,cc:juzhe.zhong@rivai.ai,rguenther@suse.de,chenglulu@loongson.cn,apinski@marvell.com,jcmvbkbc@gmail.com,gccadmin@gcc.gnu.org,pan2.li@intel.com,cc:chenxiaolong@loongson.cn,richard.sandiford@arm.com
diff --git a/notify/mail-subject.txt b/notify/mail-subject.txt
index 6455962..a5d6275 100644
--- a/notify/mail-subject.txt
+++ b/notify/mail-subject.txt
@@ -1 +1 @@
-[Linaro-TCWG-CI] 40 commits in gcc: Success on arm
+[Linaro-TCWG-CI] 62 commits in gcc: Success on arm