onsuccess: #240: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/240/

Results :
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap_O1:
  | 1

check_regression status : 0

5 files changed, 12 insertions, 12 deletions

diff --git a/notify/jira/comment-template.txt b/notify/jira/comment-template.txt
index 696d434..d76d08c 100644
--- a/notify/jira/comment-template.txt
+++ b/notify/jira/comment-template.txt
@@ -1,3 +1,3 @@
 [GNU-692]
 Success
-Details: https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/239/artifact/artifacts/notify/mail-body.txt/*view*/
+Details: https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/240/artifact/artifacts/notify/mail-body.txt/*view*/
diff --git a/notify/lnt_report.json b/notify/lnt_report.json
deleted file mode 100644
index e69de29..0000000
--- a/notify/lnt_report.json
+++ /dev/null
diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index c2bf10f..8b68955 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -2,13 +2,13 @@ Dear contributor, our automatic CI has detected problems related to your patch(e
 
 In bootstrap_build master-arm-bootstrap_O1 after:
 
-  | 28 commits in gcc
-  | f6c5e247b29 RISC-V: Fix incorrect index(offset) of gather/scatter
-  | d1e5566685a RISC-V: Support FP lrint/lrintf auto vectorization
-  | d4de593d366 RISC-V: Remove XFAIL of ssa-dom-cse-2.c
-  | e75bf1985fd tree-ssa-strlen: optimization skips clobbering store [PR111519]
-  | c4149242314 Optimize (ne:SI (subreg:QI (ashift:SI x 7) 0) 0) as (and:SI x 1).
-  | ... and 23 more commits in gcc
+  | 35 commits in gcc
+  | 2cc4f58a7c1 RISC-V: Support FP lround/lroundf auto vectorization
+  | dfb40855a08 dwarf2out: Stop using wide_int in GC structures
+  | 05f98310b54 tree-optimization/111764 - wrong reduction vectorization
+  | 5fbd91b12cd Support Intel USER_MSR
+  | 3948844679a LoongArch: Modify check_effective_target_vect_int_mod according to SX/ASX capabilities.
+  | ... and 30 more commits in gcc
 
 Results changed to
 # reset_artifacts:
@@ -32,6 +32,6 @@ CI config tcwg_bootstrap_build/master-arm-bootstrap_O1
 -----------------8<--------------------------8<--------------------------8<--------------------------
 The information below can be used to reproduce a debug environment:
 
-Current build   : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/239/artifact/artifacts
-Reference build : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/238/artifact/artifacts
+Current build   : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/240/artifact/artifacts
+Reference build : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/239/artifact/artifacts
 
diff --git a/notify/mail-recipients.txt b/notify/mail-recipients.txt
index eca2e68..af264e9 100644
--- a/notify/mail-recipients.txt
+++ b/notify/mail-recipients.txt
@@ -1 +1 @@
-cc:andrew@sifive.com,roger@nextmovesoftware.com,cc:ebotcazou@adacore.com,bcc:tcwg-validation@linaro.org,poulhies@adacore.com,jakub@redhat.com,cc:gcc-regression@gcc.gnu.org,jason@redhat.com,cc:juzhe.zhong@rivai.ai,jlaw@ventanamicro.com,lehua.ding@rivai.ai,rguenther@suse.de,gccadmin@gcc.gnu.org,pinskia@gmail.com,pan2.li@intel.com,cc:desplanques@adacore.com,hongtao.liu@intel.com,christoph.muellner@vrull.eu,cc:miranda@adacore.com
+cc:jun.zhang@intel.com,fkastl@suse.cz,bcc:tcwg-validation@linaro.org,cc:yangyujie@loongson.cn,jakub@redhat.com,gaiusmod2@gmail.com,cc:mary.bennett@embecosm.com,cc:gcc-regression@gcc.gnu.org,kito.cheng@sifive.com,cc:zewei.mo@intel.com,pault@gcc.gnu.org,jlaw@ventanamicro.com,hongyu.wang@intel.com,rguenther@suse.de,chenglulu@loongson.cn,gccadmin@gcc.gnu.org,pinskia@gmail.com,pan2.li@intel.com,hongtao.liu@intel.com,lin1.hu@intel.com,linkw@linux.ibm.com,cc:panchenghui@loongson.cn
diff --git a/notify/mail-subject.txt b/notify/mail-subject.txt
index f23f552..07841d3 100644
--- a/notify/mail-subject.txt
+++ b/notify/mail-subject.txt
@@ -1 +1 @@
-[Linaro-TCWG-CI] 28 commits in gcc: Success on arm
+[Linaro-TCWG-CI] 35 commits in gcc: Success on arm