onsuccess: #258: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/258/

Results :
  | # reset_artifacts:
  | -10
  | # true:
  | 0
  | # build_abe bootstrap_O1:
  | 1

check_regression status : 0

4 files changed, 12 insertions, 12 deletions

diff --git a/notify/jira/comment-template.txt b/notify/jira/comment-template.txt
index 8f931f9..47514da 100644
--- a/notify/jira/comment-template.txt
+++ b/notify/jira/comment-template.txt
@@ -1,3 +1,3 @@
 [GNU-692]
 Success
-Details: https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/257/artifact/artifacts/notify/mail-body.txt/*view*/
+Details: https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/258/artifact/artifacts/notify/mail-body.txt/*view*/
diff --git a/notify/mail-body.txt b/notify/mail-body.txt
index c043a19..07d07c2 100644
--- a/notify/mail-body.txt
+++ b/notify/mail-body.txt
@@ -2,13 +2,13 @@ Dear contributor, our automatic CI has detected problems related to your patch(e
 
 In bootstrap_build master-arm-bootstrap_O1 after:
 
-  | 11 commits in gcc
-  | 36a52cdc233 rs6000: Change bitwise xor to an equality operator [PR106907]
-  | ff4cea05a6e PR testsuite/111462 - add powerpc64le to list of ssa-sink-18.c XFAIL
-  | eb1cdb3e43f RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32
-  | f3e44d07974 Fortran: Fix a problem with SELECT TYPE selectors [PR104555].
-  | 8c40b72036c Improve memcmpeq for 512-bit vector with vpcmpeq + kortest.
-  | ... and 6 more commits in gcc
+  | 24 commits in gcc
+  | 6bf2cebe2bf LoongArch: Define HAVE_AS_TLS to 0 if it's undefined [PR112299]
+  | 5ee961b6f26 RISC-V: Add assert of the number of vmerge in autovec cond testcases
+  | 711d703d07c match.pd: Support combine cond_len_op + vec_cond similar to cond_op
+  | 9cc2b97458b Fix incorrect option mask and avx512cd target push
+  | 5ee894130fd RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond
+  | ... and 19 more commits in gcc
 
 Results changed to
 # reset_artifacts:
@@ -32,6 +32,6 @@ CI config tcwg_bootstrap_build/master-arm-bootstrap_O1
 -----------------8<--------------------------8<--------------------------8<--------------------------
 The information below can be used to reproduce a debug environment:
 
-Current build   : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/257/artifact/artifacts
-Reference build : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/256/artifact/artifacts
+Current build   : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/258/artifact/artifacts
+Reference build : https://ci.linaro.org/job/tcwg_bootstrap_build--master-arm-bootstrap_O1-build/257/artifact/artifacts
 
diff --git a/notify/mail-recipients.txt b/notify/mail-recipients.txt
index fabee03..1aa5723 100644
--- a/notify/mail-recipients.txt
+++ b/notify/mail-recipients.txt
@@ -1 +1 @@
-bcc:tcwg-validation@linaro.org,fdumont@gcc.gnu.org,cc:gcc-regression@gcc.gnu.org,pault@gcc.gnu.org,cc:juzhe.zhong@rivai.ai,rguenther@suse.de,guihaoc@gcc.gnu.org,gccadmin@gcc.gnu.org,pan2.li@intel.com,jeevitha@linux.ibm.com,hongtao.liu@intel.com,ibuclaw@gdcproject.org
+richard.ball@arm.com,roger@nextmovesoftware.com,xry111@xry111.site,bcc:tcwg-validation@linaro.org,ubizjak@gmail.com,haochen.jiang@intel.com,fdumont@gcc.gnu.org,cc:gcc-regression@gcc.gnu.org,cc:mayshao-oc@zhaoxin.com,patrick@rivosinc.com,mjambor@suse.cz,lehua.ding@rivai.ai,gccadmin@gcc.gnu.org,pinskia@gmail.com,iain@sandoe.co.uk,hongtao.liu@intel.com,fxcoudert@gcc.gnu.org
diff --git a/notify/mail-subject.txt b/notify/mail-subject.txt
index 4b2a0ae..679e467 100644
--- a/notify/mail-subject.txt
+++ b/notify/mail-subject.txt
@@ -1 +1 @@
-[Linaro-TCWG-CI] 11 commits in gcc: Success on arm
+[Linaro-TCWG-CI] 24 commits in gcc: Success on arm