diff options
author | Sagar Thakur <sagar.thakur@imgtec.com> | 2015-07-13 09:52:06 +0000 |
---|---|---|
committer | Sagar Thakur <sagar.thakur@imgtec.com> | 2015-07-13 09:52:06 +0000 |
commit | 4586362bad78f6533818bb4f691f682fbf4fa427 (patch) | |
tree | 9be7395abeb7b7b83cf140528fbdf686c2bfdcb1 | |
parent | 48a0b2755668823fa705ea37b533803dcbec7633 (diff) |
[LLDB][MIPS] Add mips cores in cores_match () in ArchSpec
This patch:
- Allows mips32 cores to match with any mips32/mips64 cores.
- Allows mips32r2 cores to match with core only up-to mips32r2/mips64r2.
- Allows mips32r3 cores to match with core only up-to mips32r3/mips64r3.
- Allows mips32r5 cores to match with core only up-to mips32r3/mips64r5.
- Allows mips32r6 core to match with only mips32r6/mips64r6 or mips32/mips64.
Reviewers: emaste, jaydeep, clayborg
Subscribers: mohit.bhakkad, nitesh.jain, bhushan, lldb-commits
Differential Revision: http://reviews.llvm.org/D10921
git-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@242016 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | source/Core/ArchSpec.cpp | 96 |
1 files changed, 93 insertions, 3 deletions
diff --git a/source/Core/ArchSpec.cpp b/source/Core/ArchSpec.cpp index 543808d4e..363443077 100644 --- a/source/Core/ArchSpec.cpp +++ b/source/Core/ArchSpec.cpp @@ -1181,11 +1181,46 @@ cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_in } break; + case ArchSpec::eCore_mips32: + if (!enforce_exact_match) + { + if (core2 >= ArchSpec::kCore_mips32_first && core2 <= ArchSpec::kCore_mips32_last) + return true; + try_inverse = false; + } + break; + + case ArchSpec::eCore_mips32el: + if (!enforce_exact_match) + { + if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= ArchSpec::kCore_mips32el_last) + return true; + try_inverse = false; + } + case ArchSpec::eCore_mips64: + if (!enforce_exact_match) + { + if (core2 >= ArchSpec::kCore_mips32_first && core2 <= ArchSpec::kCore_mips32_last) + return true; + if (core2 >= ArchSpec::kCore_mips64_first && core2 <= ArchSpec::kCore_mips64_last) + return true; + try_inverse = false; + } + + case ArchSpec::eCore_mips64el: + if (!enforce_exact_match) + { + if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= ArchSpec::kCore_mips32el_last) + return true; + if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= ArchSpec::kCore_mips64el_last) + return true; + try_inverse = false; + } + case ArchSpec::eCore_mips64r2: case ArchSpec::eCore_mips64r3: case ArchSpec::eCore_mips64r5: - case ArchSpec::eCore_mips64r6: if (!enforce_exact_match) { if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) @@ -1196,11 +1231,9 @@ cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_in } break; - case ArchSpec::eCore_mips64el: case ArchSpec::eCore_mips64r2el: case ArchSpec::eCore_mips64r3el: case ArchSpec::eCore_mips64r5el: - case ArchSpec::eCore_mips64r6el: if (!enforce_exact_match) { if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) @@ -1211,6 +1244,63 @@ cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_in } break; + case ArchSpec::eCore_mips32r2: + case ArchSpec::eCore_mips32r3: + case ArchSpec::eCore_mips32r5: + if (!enforce_exact_match) + { + if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) + return true; + } + break; + + case ArchSpec::eCore_mips32r2el: + case ArchSpec::eCore_mips32r3el: + case ArchSpec::eCore_mips32r5el: + if (!enforce_exact_match) + { + if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) + return true; + } + break; + + case ArchSpec::eCore_mips32r6: + if (!enforce_exact_match) + { + if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) + return true; + } + break; + + case ArchSpec::eCore_mips32r6el: + if (!enforce_exact_match) + { + if (core2 == ArchSpec::eCore_mips32el || core2 == ArchSpec::eCore_mips32r6el) + return true; + return true; + } + break; + + case ArchSpec::eCore_mips64r6: + if (!enforce_exact_match) + { + if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) + return true; + if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) + return true; + } + break; + + case ArchSpec::eCore_mips64r6el: + if (!enforce_exact_match) + { + if (core2 == ArchSpec::eCore_mips32el || core2 == ArchSpec::eCore_mips32r6el) + return true; + if (core2 == ArchSpec::eCore_mips64el || core2 == ArchSpec::eCore_mips64r6el) + return true; + } + break; + default: break; } |