diff options
Diffstat (limited to 'acsr')
| -rw-r--r-- | acsr/c_helpers.c | 14 | ||||
| -rw-r--r-- | acsr/helpers.h | 14 | ||||
| -rw-r--r-- | acsr/helpers.s | 446 | ||||
| -rw-r--r-- | acsr/v7.s | 148 |
4 files changed, 311 insertions, 311 deletions
diff --git a/acsr/c_helpers.c b/acsr/c_helpers.c index a7df858..7ca6df7 100644 --- a/acsr/c_helpers.c +++ b/acsr/c_helpers.c @@ -1,23 +1,23 @@ /* * Copyright (c) 2012, ARM Limited. All rights reserved. - * + * * Redistribution and use in source and binary forms, with * or without modification, are permitted provided that the * following conditions are met: - * + * * Redistributions of source code must retain the above - * copyright notice, this list of conditions and the + * copyright notice, this list of conditions and the * following disclaimer. * * Redistributions in binary form must reproduce the - * above copyright notice, this list of conditions and - * the following disclaimer in the documentation + * above copyright notice, this list of conditions and + * the following disclaimer in the documentation * and/or other materials provided with the distribution. - * + * * Neither the name of ARM nor the names of its * contributors may be used to endorse or promote products * derived from this software without specific prior written - * permission. + * permission. */ /** diff --git a/acsr/helpers.h b/acsr/helpers.h index 14c8472..ea1e0ca 100644 --- a/acsr/helpers.h +++ b/acsr/helpers.h @@ -1,23 +1,23 @@ /* * Copyright (c) 2012, ARM Limited. All rights reserved. - * + * * Redistribution and use in source and binary forms, with * or without modification, are permitted provided that the * following conditions are met: - * + * * Redistributions of source code must retain the above - * copyright notice, this list of conditions and the + * copyright notice, this list of conditions and the * following disclaimer. * * Redistributions in binary form must reproduce the - * above copyright notice, this list of conditions and - * the following disclaimer in the documentation + * above copyright notice, this list of conditions and + * the following disclaimer in the documentation * and/or other materials provided with the distribution. - * + * * Neither the name of ARM nor the names of its * contributors may be used to endorse or promote products * derived from this software without specific prior written - * permission. + * permission. */ /* diff --git a/acsr/helpers.s b/acsr/helpers.s index 0c92511..1a7fba4 100644 --- a/acsr/helpers.s +++ b/acsr/helpers.s @@ -1,26 +1,26 @@ ; ; Copyright (c) 2012, ARM Limited. All rights reserved. - ; + ; ; Redistribution and use in source and binary forms, with ; or without modification, are permitted provided that the ; following conditions are met: - ; + ; ; Redistributions of source code must retain the above - ; copyright notice, this list of conditions and the + ; copyright notice, this list of conditions and the ; following disclaimer. ; ; Redistributions in binary form must reproduce the - ; above copyright notice, this list of conditions and - ; the following disclaimer in the documentation + ; above copyright notice, this list of conditions and + ; the following disclaimer in the documentation ; and/or other materials provided with the distribution. - ; + ; ; Neither the name of ARM nor the names of its ; contributors may be used to endorse or promote products ; derived from this software without specific prior written - ; permission. - ; + ; permission. + ; - EXPORT isb + EXPORT isb EXPORT dsb EXPORT dmb EXPORT wfi @@ -33,25 +33,25 @@ EXPORT get_cpu_type EXPORT va_to_pa - EXPORT read_cbar + EXPORT read_cbar EXPORT read_sctlr EXPORT read_actlr EXPORT read_prrr EXPORT read_nmrr EXPORT read_l2ctlr EXPORT read_dacr - EXPORT read_ttbr0 - EXPORT read_cpacr + EXPORT read_ttbr0 + EXPORT read_cpacr EXPORT read_scr EXPORT read_cpsr EXPORT read_midr - EXPORT read_mpidr - EXPORT read_cntpct - EXPORT read_cntfrq + EXPORT read_mpidr + EXPORT read_cntpct + EXPORT read_cntfrq EXPORT read_vmpidr - EXPORT read_vmidr + EXPORT read_vmidr EXPORT read_vttbr - EXPORT read_httbr + EXPORT read_httbr EXPORT read_id_pfr0 EXPORT read_id_pfr1 EXPORT read_id_dfr0 @@ -59,20 +59,20 @@ EXPORT read_id_mmfr0 EXPORT read_id_mmfr1 EXPORT read_id_mmfr2 - EXPORT read_id_mmfr3 + EXPORT read_id_mmfr3 EXPORT read_id_isar0 EXPORT read_id_isar1 EXPORT read_id_isar2 EXPORT read_id_isar3 EXPORT read_id_isar4 - EXPORT read_id_isar5 + EXPORT read_id_isar5 EXPORT read_cpuid - EXPORT read_aidr + EXPORT read_aidr EXPORT read_ctr EXPORT read_tcmtr EXPORT read_tlbtr EXPORT read_clusterid - EXPORT read_l2ctlr + EXPORT read_l2ctlr EXPORT read_hsctlr EXPORT read_hdfar EXPORT read_hpfar @@ -80,22 +80,22 @@ EXPORT read_hcr EXPORT read_hdcr EXPORT read_hcptr - EXPORT read_hstr + EXPORT read_hstr EXPORT read_cnthctl - EXPORT read_cntkctl + EXPORT read_cntkctl EXPORT read_cntp_ctl - EXPORT read_cntp_tval + EXPORT read_cntp_tval EXPORT read_cnthp_ctl EXPORT read_cnthp_tval - EXPORT read_cnthp_cval + EXPORT read_cnthp_cval EXPORT read_ttbcr EXPORT read_nsacr - EXPORT read_clidr + EXPORT read_clidr EXPORT read_csselr EXPORT read_ccsidr EXPORT read_nmrr EXPORT read_prrr - EXPORT read_mvbar + EXPORT read_mvbar EXPORT read_vbar EXPORT read_hsr EXPORT read_dfar @@ -103,53 +103,53 @@ EXPORT read_dfsr EXPORT read_ifsr EXPORT read_adfsr - EXPORT read_aifsr - EXPORT read_l2ectlr - EXPORT read_pmuserenr - EXPORT read_pmintenset - EXPORT read_pmintenclr - EXPORT read_pmovsset - EXPORT read_pmccntr - EXPORT read_pmxevtyper - EXPORT read_pmxevcntr - EXPORT read_pmcr - EXPORT read_pmcntenset - EXPORT read_pmcntenclr - EXPORT read_pmovsr - EXPORT read_pmswinc - EXPORT read_pmselr - EXPORT read_pmceid0 - EXPORT read_pmceid1 - - EXPORT write_l2ectlr - EXPORT write_pmuserenr - EXPORT write_pmintenset - EXPORT write_pmintenclr - EXPORT write_pmovsset - EXPORT write_pmccntr - EXPORT write_pmxevtyper - EXPORT write_pmxevcntr - EXPORT write_pmcr - EXPORT write_pmcntenset - EXPORT write_pmcntenclr - EXPORT write_pmovsr - EXPORT write_pmswinc - EXPORT write_pmselr - EXPORT write_pmceid0 - EXPORT write_pmceid1 + EXPORT read_aifsr + EXPORT read_l2ectlr + EXPORT read_pmuserenr + EXPORT read_pmintenset + EXPORT read_pmintenclr + EXPORT read_pmovsset + EXPORT read_pmccntr + EXPORT read_pmxevtyper + EXPORT read_pmxevcntr + EXPORT read_pmcr + EXPORT read_pmcntenset + EXPORT read_pmcntenclr + EXPORT read_pmovsr + EXPORT read_pmswinc + EXPORT read_pmselr + EXPORT read_pmceid0 + EXPORT read_pmceid1 + + EXPORT write_l2ectlr + EXPORT write_pmuserenr + EXPORT write_pmintenset + EXPORT write_pmintenclr + EXPORT write_pmovsset + EXPORT write_pmccntr + EXPORT write_pmxevtyper + EXPORT write_pmxevcntr + EXPORT write_pmcr + EXPORT write_pmcntenset + EXPORT write_pmcntenclr + EXPORT write_pmovsr + EXPORT write_pmswinc + EXPORT write_pmselr + EXPORT write_pmceid0 + EXPORT write_pmceid1 EXPORT write_dacr EXPORT write_prrr - EXPORT write_nmrr + EXPORT write_nmrr EXPORT write_ttbr0 EXPORT write_cpacr EXPORT write_nsacr EXPORT write_scr EXPORT write_mvbar EXPORT write_vbar - EXPORT write_hvbar + EXPORT write_hvbar EXPORT write_vmpidr - EXPORT write_vmidr - EXPORT write_csselr + EXPORT write_vmidr + EXPORT write_csselr EXPORT write_hcr EXPORT write_hdcr EXPORT write_hcptr @@ -157,29 +157,29 @@ EXPORT write_sctlr EXPORT write_actlr EXPORT write_ttbcr - EXPORT write_cntfrq + EXPORT write_cntfrq EXPORT write_cnthctl - EXPORT write_cntkctl + EXPORT write_cntkctl EXPORT write_cntp_ctl - EXPORT write_cntp_tval + EXPORT write_cntp_tval EXPORT write_cnthp_ctl EXPORT write_cnthp_tval - EXPORT write_cnthp_cval + EXPORT write_cnthp_cval EXPORT write_hsctlr EXPORT write_httbr - EXPORT write_vttbr + EXPORT write_vttbr EXPORT write_htcr - EXPORT write_vtcr - EXPORT write_hmair0 + EXPORT write_vtcr + EXPORT write_hmair0 EXPORT write_hmair1 EXPORT write_dfar EXPORT write_ifar EXPORT write_dfsr EXPORT write_ifsr EXPORT write_adfsr - EXPORT write_aifsr - - + EXPORT write_aifsr + + MIDR_CPU_MASK EQU 0xff00fff0 AREA ACSR, CODE, ALIGN=5 @@ -194,7 +194,7 @@ wfi FUNCTION wfi bx lr ENDFUNC - + ; WFI forever, and attempt to prevent speculative accesses starting ; FIQ and IRQ are assumed to be disabled endless_wfi FUNCTION @@ -234,8 +234,8 @@ copy_words FUNCTION bne %b0 1 bx lr ENDFUNC - - + + appf_memcpy FUNCTION cmp r2, #0 bxeq lr @@ -264,26 +264,26 @@ write_cntfrq FUNCTION mcr p15, 0, r0, c14, c0, 0 bx lr ENDFUNC - + read_cntpct FUNCTION mrrc p15, 0, r0, r1, c14 bx lr ENDFUNC - + isb FUNCTION isb bx lr - ENDFUNC + ENDFUNC read_vmpidr FUNCTION mrc p15, 4, r0, c0, c0, 5 bx lr ENDFUNC - + read_vmidr FUNCTION mrc p15, 4, r0, c0, c0, 0 bx lr - ENDFUNC + ENDFUNC read_id_pfr0 FUNCTION mrc p15, 0, r0, c0, c1, 0 @@ -299,12 +299,12 @@ read_id_dfr0 FUNCTION mrc p15, 0, r0, c0, c1, 2 bx lr ENDFUNC - + read_id_afr0 FUNCTION mrc p15, 0, r0, c0, c1, 3 bx lr ENDFUNC - + read_id_mmfr0 FUNCTION mrc p15, 0, r0, c0, c1, 4 bx lr @@ -314,17 +314,17 @@ read_id_mmfr1 FUNCTION mrc p15, 0, r0, c0, c1, 5 bx lr ENDFUNC - + read_id_mmfr2 FUNCTION mrc p15, 0, r0, c0, c1, 6 bx lr - ENDFUNC + ENDFUNC read_id_mmfr3 FUNCTION mrc p15, 0, r0, c0, c1, 7 bx lr ENDFUNC - + read_id_isar0 FUNCTION mrc p15, 0, r0, c0, c2, 0 bx lr @@ -334,17 +334,17 @@ read_id_isar1 FUNCTION mrc p15, 0, r0, c0, c2, 1 bx lr ENDFUNC - + read_id_isar2 FUNCTION mrc p15, 0, r0, c0, c2, 2 bx lr ENDFUNC - + read_id_isar3 FUNCTION mrc p15, 0, r0, c0, c2, 3 bx lr ENDFUNC - + read_id_isar4 FUNCTION mrc p15, 0, r0, c0, c2, 4 bx lr @@ -353,8 +353,8 @@ read_id_isar4 FUNCTION read_id_isar5 FUNCTION mrc p15, 0, r0, c0, c2, 5 bx lr - ENDFUNC - + ENDFUNC + read_ctr FUNCTION mrc p15, 0, r0, c0, c0, 1 bx lr @@ -368,12 +368,12 @@ read_tcmtr FUNCTION read_tlbtr FUNCTION mrc p15, 0, r0, c0, c0, 3 bx lr - ENDFUNC - + ENDFUNC + read_aidr FUNCTION mrc p15, 1, r0, c0, c0, 7 bx lr - ENDFUNC + ENDFUNC read_dacr FUNCTION mrc p15, 0, r0, c3, c0, 0 @@ -395,7 +395,7 @@ read_cpacr FUNCTION mrc p15, 0, r0, c1, c0, 2 bx lr ENDFUNC - + write_cpacr FUNCTION mcr p15, 0, r0, c1, c0, 2 bx lr @@ -419,7 +419,7 @@ read_scr FUNCTION write_scr FUNCTION mcr p15, 0, r0, c1, c1, 0 dsb - isb + isb bx lr ENDFUNC @@ -441,32 +441,32 @@ write_mvbar FUNCTION ENDFUNC write_vbar FUNCTION - mcr p15, 0, r0, c12, c0, 0 + mcr p15, 0, r0, c12, c0, 0 bx lr ENDFUNC write_hvbar FUNCTION - mcr p15, 4, r0, c12, c0, 0 + mcr p15, 4, r0, c12, c0, 0 bx lr - ENDFUNC + ENDFUNC read_mvbar FUNCTION mrc p15, 0, r0, c12, c0, 1 bx lr ENDFUNC - + read_vbar FUNCTION - mrc p15, 0, r0, c12, c0, 0 + mrc p15, 0, r0, c12, c0, 0 bx lr ENDFUNC - + read_cpuid FUNCTION mrc p15, 0, r0, c0, c0, 5 ands r0, r0, #0xf bx lr ENDFUNC -read_clusterid FUNCTION +read_clusterid FUNCTION mrc p15, 0, r0, c0, c0, 5 lsr r0, r0, #0x8 ands r0, r0, #0xf @@ -478,32 +478,32 @@ write_ttbr0 FUNCTION mcr p15, 0, r0, c7, c5, 6 mcr p15, 0, r0, c8, c7, 0 dsb - isb + isb bx lr ENDFUNC read_ttbcr FUNCTION mrc p15, 0, r0, c2, c0, 2 bx lr - ENDFUNC - + ENDFUNC + write_ttbcr FUNCTION mcr p15, 0, r0, c2, c0, 2 bx lr - ENDFUNC + ENDFUNC write_vmpidr FUNCTION mcr p15, 4, r0, c0, c0, 5 isb bx lr ENDFUNC - + write_vmidr FUNCTION mcr p15, 4, r0, c0, c0, 0 isb bx lr - ENDFUNC - + ENDFUNC + read_vtcr FUNCTION mrc p15, 4, r0, c2, c1, 2 bx lr @@ -518,16 +518,16 @@ read_hdcr FUNCTION mrc p15, 4, r0, c1, c1, 1 bx lr ENDFUNC - + read_hcptr FUNCTION mrc p15, 4, r0, c1, c1, 2 bx lr ENDFUNC - + read_hstr FUNCTION mrc p15, 4, r0, c1, c1, 3 bx lr - ENDFUNC + ENDFUNC read_httbr FUNCTION mrrc p15, 4, r0, r1, c2 @@ -537,25 +537,25 @@ read_httbr FUNCTION read_vttbr FUNCTION mrrc p15, 6, r0, r1, c2 bx lr - ENDFUNC - + ENDFUNC + write_hcr FUNCTION mcr p15, 4, r0, c1, c1, 0 dsb - isb + isb bx lr ENDFUNC write_hdcr FUNCTION mcr p15, 4, r0, c1, c1, 1 bx lr - ENDFUNC - + ENDFUNC + write_hcptr FUNCTION mcr p15, 4, r0, c1, c1, 2 bx lr - ENDFUNC - + ENDFUNC + write_hstr FUNCTION mcr p15, 4, r0, c1, c1, 3 bx lr @@ -566,7 +566,7 @@ write_httbr FUNCTION mcr p15, 0, r0, c7, c5, 6 mcr p15, 0, r0, c8, c7, 0 dsb - isb + isb bx lr ENDFUNC @@ -575,10 +575,10 @@ write_vttbr FUNCTION mcr p15, 0, r0, c7, c5, 6 mcr p15, 0, r0, c8, c7, 0 dsb - isb + isb bx lr - ENDFUNC - + ENDFUNC + write_htcr FUNCTION mcr p15, 4, r0, c2, c0, 2 bx lr @@ -587,7 +587,7 @@ write_htcr FUNCTION write_vtcr FUNCTION mcr p15, 4, r0, c2, c1, 2 bx lr - ENDFUNC + ENDFUNC write_hmair0 FUNCTION mcr p15, 4, r0, c10, c2, 0 @@ -597,20 +597,20 @@ write_hmair0 FUNCTION write_hmair1 FUNCTION mcr p15, 4, r0, c10, c2, 1 bx lr - ENDFUNC - + ENDFUNC + read_nsacr FUNCTION mrc p15, 0, r0, c1, c1, 2 bx lr ENDFUNC read_l2ctlr FUNCTION - mrc p15, 1, r0, c9, c0, 2 + mrc p15, 1, r0, c9, c0, 2 bx lr ENDFUNC read_l2ectlr FUNCTION - mrc p15, 1, r0, c9, c0, 3 + mrc p15, 1, r0, c9, c0, 3 bx lr ENDFUNC @@ -618,71 +618,71 @@ read_pmuserenr FUNCTION mrc p15, 0, r0, c9, c14, 0 bx lr ENDFUNC - + read_pmintenset FUNCTION mrc p15, 0, r0, c9, c14, 1 bx lr - ENDFUNC + ENDFUNC read_pmintenclr FUNCTION mrc p15, 0, r0, c9, c14, 2 bx lr ENDFUNC - + read_pmovsset FUNCTION mrc p15, 0, r0, c9, c14, 3 bx lr ENDFUNC - + read_pmccntr FUNCTION mrc p15, 0, r0, c9, c13, 0 bx lr ENDFUNC - + read_pmxevtyper FUNCTION mrc p15, 0, r0, c9, c13, 1 bx lr ENDFUNC - + read_pmxevcntr FUNCTION mrc p15, 0, r0, c9, c13, 2 bx lr ENDFUNC - + read_pmcr FUNCTION mrc p15, 0, r0, c9, c12, 0 bx lr ENDFUNC - + read_pmcntenset FUNCTION mrc p15, 0, r0, c9, c12, 1 bx lr ENDFUNC - + read_pmcntenclr FUNCTION mrc p15, 0, r0, c9, c12, 2 bx lr ENDFUNC - + read_pmovsr FUNCTION mrc p15, 0, r0, c9, c12, 3 bx lr ENDFUNC - + read_pmswinc FUNCTION mrc p15, 0, r0, c9, c12, 4 bx lr ENDFUNC - + read_pmselr FUNCTION mrc p15, 0, r0, c9, c12, 5 bx lr ENDFUNC - + read_pmceid0 FUNCTION mrc p15, 0, r0, c9, c12, 6 bx lr - ENDFUNC + ENDFUNC read_pmceid1 FUNCTION mrc p15, 0, r0, c9, c12, 7 @@ -690,7 +690,7 @@ read_pmceid1 FUNCTION ENDFUNC write_l2ectlr FUNCTION - mcr p15, 1, r0, c9, c0, 3 + mcr p15, 1, r0, c9, c0, 3 bx lr ENDFUNC @@ -698,78 +698,78 @@ write_pmuserenr FUNCTION mcr p15, 0, r0, c9, c14, 0 bx lr ENDFUNC - + write_pmintenset FUNCTION mcr p15, 0, r0, c9, c14, 1 bx lr - ENDFUNC + ENDFUNC write_pmintenclr FUNCTION mcr p15, 0, r0, c9, c14, 2 bx lr ENDFUNC - + write_pmovsset FUNCTION mcr p15, 0, r0, c9, c14, 3 bx lr ENDFUNC - + write_pmccntr FUNCTION mcr p15, 0, r0, c9, c13, 0 bx lr ENDFUNC - + write_pmxevtyper FUNCTION mcr p15, 0, r0, c9, c13, 1 bx lr ENDFUNC - + write_pmxevcntr FUNCTION mcr p15, 0, r0, c9, c13, 2 bx lr ENDFUNC - + write_pmcr FUNCTION mcr p15, 0, r0, c9, c12, 0 bx lr ENDFUNC - + write_pmcntenset FUNCTION mcr p15, 0, r0, c9, c12, 1 bx lr ENDFUNC - + write_pmcntenclr FUNCTION mcr p15, 0, r0, c9, c12, 2 bx lr ENDFUNC - + write_pmovsr FUNCTION mcr p15, 0, r0, c9, c12, 3 bx lr ENDFUNC - + write_pmswinc FUNCTION mcr p15, 0, r0, c9, c12, 4 bx lr ENDFUNC - + write_pmselr FUNCTION mcr p15, 0, r0, c9, c12, 5 bx lr ENDFUNC - + write_pmceid0 FUNCTION mcr p15, 0, r0, c9, c12, 6 bx lr - ENDFUNC + ENDFUNC write_pmceid1 FUNCTION mcr p15, 0, r0, c9, c12, 7 bx lr - ENDFUNC - -read_sctlr FUNCTION + ENDFUNC + +read_sctlr FUNCTION mrc p15, 0, r0, c1, c0, 0 bx lr ENDFUNC @@ -781,18 +781,18 @@ write_sctlr FUNCTION bx lr ENDFUNC -read_hsctlr FUNCTION +read_hsctlr FUNCTION mrc p15, 4, r0, c1, c0, 0 bx lr ENDFUNC read_hdfar FUNCTION - mrc p15, 4, r0, c6, c0, 0 + mrc p15, 4, r0, c6, c0, 0 bx lr ENDFUNC - + read_hpfar FUNCTION - mrc p15, 4, r0, c6, c0, 4 + mrc p15, 4, r0, c6, c0, 4 bx lr ENDFUNC @@ -804,10 +804,10 @@ read_hsr FUNCTION write_hsctlr FUNCTION mcr p15, 4, r0, c1, c0, 0 dsb - isb + isb bx lr ENDFUNC - + read_cnthctl FUNCTION mrc p15, 4, r0, c14, c1, 0 bx lr @@ -816,7 +816,7 @@ read_cnthctl FUNCTION read_cntkctl FUNCTION mrc p15, 0, r0, c14, c1, 0 bx lr - ENDFUNC + ENDFUNC read_cnthp_cval FUNCTION mrrc p15, 6, r0, r1, c14 @@ -832,16 +832,16 @@ read_cntp_tval FUNCTION mrc p15, 0, r0, c14, c2, 0 bx lr ENDFUNC - + read_cntp_ctl FUNCTION mrc p15, 0, r0, c14, c2, 1 bx lr - ENDFUNC - + ENDFUNC + read_cnthp_ctl FUNCTION mrc p15, 4, r0, c14, c2, 1 bx lr - ENDFUNC + ENDFUNC write_cnthctl FUNCTION mcr p15, 4, r0, c14, c1, 0 @@ -851,65 +851,65 @@ write_cnthctl FUNCTION write_cntkctl FUNCTION mcr p15, 0, r0, c14, c1, 0 bx lr - ENDFUNC + ENDFUNC write_cntp_tval FUNCTION mcr p15, 0, r0, c14, c2, 0 isb bx lr - ENDFUNC - + ENDFUNC + write_cntp_ctl FUNCTION mcr p15, 0, r0, c14, c2, 1 dsb - isb + isb bx lr - ENDFUNC - + ENDFUNC + write_cnthp_cval FUNCTION mcrr p15, 6, r0, r1, c14 dsb - isb + isb bx lr ENDFUNC write_cnthp_tval FUNCTION mcr p15, 4, r0, c14, c2, 0 dsb - isb + isb bx lr ENDFUNC - + write_cnthp_ctl FUNCTION mcr p15, 4, r0, c14, c2, 1 dsb - isb + isb bx lr - ENDFUNC - -read_clidr FUNCTION + ENDFUNC + +read_clidr FUNCTION mrc p15, 1, r0, c0, c0, 1 ; read clidr bx lr ENDFUNC -read_ccsidr FUNCTION +read_ccsidr FUNCTION mrc p15, 1, r0, c0, c0, 0 ; read ccsidr bx lr ENDFUNC -read_csselr FUNCTION +read_csselr FUNCTION mrc p15, 2, r0, c0, c0, 0 ; read csselr bx lr - ENDFUNC - -write_csselr FUNCTION + ENDFUNC + +write_csselr FUNCTION mcr p15, 2, r0, c0, c0, 0 ; read csselr dsb - isb + isb bx lr - ENDFUNC - -read_actlr FUNCTION + ENDFUNC + +read_actlr FUNCTION mrc p15, 0, r0, c1, c0, 1 bx lr ENDFUNC @@ -917,64 +917,64 @@ read_actlr FUNCTION write_actlr FUNCTION mcr p15, 0, r0, c1, c0, 1 dsb - isb + isb bx lr ENDFUNC -read_prrr FUNCTION +read_prrr FUNCTION mrc p15, 0, r0, c10, c2, 0 bx lr ENDFUNC -read_nmrr FUNCTION +read_nmrr FUNCTION mrc p15, 0, r0, c10, c2, 1 bx lr ENDFUNC -write_prrr FUNCTION +write_prrr FUNCTION mcr p15, 0, r0, c10, c2, 0 dsb - isb + isb bx lr ENDFUNC -write_nmrr FUNCTION +write_nmrr FUNCTION mcr p15, 0, r0, c10, c2, 1 dsb - isb + isb bx lr - ENDFUNC + ENDFUNC read_dfar FUNCTION mrc p15, 0, r0, c6, c0, 0 bx lr ENDFUNC - + read_ifar FUNCTION - mrc p15, 0, r0, c6, c0, 2 + mrc p15, 0, r0, c6, c0, 2 bx lr ENDFUNC - + read_dfsr FUNCTION - mrc p15, 0, r0, c5, c0, 0 + mrc p15, 0, r0, c5, c0, 0 bx lr ENDFUNC - + read_ifsr FUNCTION - mrc p15, 0, r0, c5, c0, 1 + mrc p15, 0, r0, c5, c0, 1 bx lr ENDFUNC - + read_adfsr FUNCTION mrc p15, 0, r0, c5, c1, 0 bx lr ENDFUNC - + read_aifsr FUNCTION - mrc p15, 0, r0, c5, c1, 1 + mrc p15, 0, r0, c5, c1, 1 bx lr ENDFUNC - + write_dfar FUNCTION mcr p15, 0, r0, c6, c0, 0 dsb @@ -985,38 +985,38 @@ write_dfar FUNCTION write_ifar FUNCTION mcr p15, 0, r0, c6, c0, 2 dsb - isb + isb bx lr ENDFUNC write_dfsr FUNCTION mcr p15, 0, r0, c5, c0, 0 dsb - isb + isb bx lr ENDFUNC write_ifsr FUNCTION mcr p15, 0, r0, c5, c0, 1 dsb - isb + isb bx lr ENDFUNC - + write_adfsr FUNCTION mcr p15, 0, r0, c5, c1, 0 dsb - isb + isb bx lr ENDFUNC - + write_aifsr FUNCTION mcr p15, 0, r0, c5, c1, 1 dsb - isb + isb bx lr ENDFUNC - + read_cbar FUNCTION mrc p15, 4, r0, c15, c0, 0 ; Read Configuration Base Address Register bx lr @@ -1033,7 +1033,7 @@ dsb FUNCTION dsb bx lr ENDFUNC - + va_to_pa FUNCTION ; Note: assumes conversion will be successful! mov r1, r0 mcr p15, 0, r0, c7, c8, 1 ; Priv Write Current World VA-PA @@ -1,24 +1,24 @@ ; ; Copyright (c) 2012, ARM Limited. All rights reserved. - ; - ; Redistribution and use in source and binary forms, with - ; or without modification, are permitted provided that the - ; following conditions are met: - ; - ; Redistributions of source code must retain the above - ; copyright notice, this list of conditions and the - ; following disclaimer. - ; - ; Redistributions in binary form must reproduce the - ; above copyright notice, this list of conditions and - ; the following disclaimer in the documentation - ; and/or other materials provided with the distribution. - ; - ; Neither the name of ARM nor the names of its - ; contributors may be used to endorse or promote products - ; derived from this software without specific prior written - ; permission. - ; + ; + ; Redistribution and use in source and binary forms, with + ; or without modification, are permitted provided that the + ; following conditions are met: + ; + ; Redistributions of source code must retain the above + ; copyright notice, this list of conditions and the + ; following disclaimer. + ; + ; Redistributions in binary form must reproduce the + ; above copyright notice, this list of conditions and + ; the following disclaimer in the documentation + ; and/or other materials provided with the distribution. + ; + ; Neither the name of ARM nor the names of its + ; contributors may be used to endorse or promote products + ; derived from this software without specific prior written + ; permission. + ; EXPORT save_performance_monitors EXPORT restore_performance_monitors @@ -45,7 +45,7 @@ EXPORT restore_generic_timer EXPORT save_fault_status - EXPORT restore_fault_status + EXPORT restore_fault_status AREA APPF, CODE @@ -62,7 +62,7 @@ MODE_HYP EQU 0x1A TTBCR_EAE EQU (1<<31) ; Are we using LPAE? -PFR0_THUMB_EE_SUPPORT EQU (1<<12) +PFR0_THUMB_EE_SUPPORT EQU (1<<12) save_performance_monitors FUNCTION @@ -73,14 +73,14 @@ save_performance_monitors FUNCTION bic r1,r8,#1 mcr p15,0,r1,c9,c12,0 ; disable counter updates from here isb ; 0b0 => PMCR<0> - mrc p15,0,r9,c9,c12,5 ; PMon: Event Counter Selection Register + mrc p15,0,r9,c9,c12,5 ; PMon: Event Counter Selection Register mrc p15,0,r10,c9,c12,1 ; PMon: Count Enable Set Reg stm r0!, {r8-r10} - mrc p15,0,r8,c9,c12,2 ; PMon: Count Enable Clear Register + mrc p15,0,r8,c9,c12,2 ; PMon: Count Enable Clear Register mrc p15,0,r9,c9,c13,0 ; PMon: Cycle Counter Register mrc p15,0,r10,c9,c12,3 ; PMon: Overflow flag Status Register stm r0!, {r8-r10} - mrc p15,0,r8,c9,c14,1 ; PMon: Interrupt Enable Set Registern + mrc p15,0,r8,c9,c14,1 ; PMon: Interrupt Enable Set Registern mrc p15,0,r9,c9,c14,2 ; PMon: Interrupt Enable Clear Register stm r0!, {r8-r9} mrc p15,0,r8,c9,c12,0 ; Read PMon Control Register @@ -120,15 +120,15 @@ restore_performance_monitors FUNCTION tst r12, r12 beq %f20 - add r1,r0,#32 ; r1 now points to the 1st saved event counter + add r1,r0,#32 ; r1 now points to the 1st saved event counter ;; Restore counters mov r6,#0 10 mcr p15,0,r6,c9,c12,5 ; PMon: select CounterN isb - ldm r1!, {r3,r4} ; Read saved data + ldm r1!, {r3,r4} ; Read saved data mcr p15,0,r3,c9,c13,1 ; PMon: restore Event Type Register mcr p15,0,r4,c9,c13,2 ; PMon: restore Event Counter Register - add r6,r6,#1 ; increment index + add r6,r6,#1 ; increment index cmps r6,r12 bne %b10 @@ -154,13 +154,13 @@ restore_performance_monitors FUNCTION ;; Restore left regs but PMCR add r1,r0,#4 ; r1 now points to the PMSELR ldm r1!,{r3,r4} - mcr p15,0,r3,c9,c12,5 ; PMon: Event Counter Selection Reg + mcr p15,0,r3,c9,c12,5 ; PMon: Event Counter Selection Reg mcr p15,0,r4,c9,c12,1 ; PMon: Count Enable Set Reg ldm r1!, {r3,r4} mcr p15,0,r4,c9,c13,0 ; PMon: Cycle Counter Register ldm r1!,{r3,r4} mcr p15,0,r3,c9,c14,2 ; PMon: Interrupt Enable Clear Reg - mcr p15,0,r4,c9,c14,1 ; PMon: Interrupt Enable Set Reg + mcr p15,0,r4,c9,c14,1 ; PMon: Interrupt Enable Set Reg ldr r3,[r1] isb ldr r0,[r0] @@ -180,20 +180,20 @@ save_banked_registers FUNCTION str sp,[r0], #4 ; save the User SP str lr,[r0], #4 ; save the User LR cps #MODE_ABT ; switch to Abort mode - str sp,[r0], #4 ; save the current SP - mrs r3,SPSR + str sp,[r0], #4 ; save the current SP + mrs r3,SPSR stm r0!,{r3,lr} ; save the current SPSR, LR cps #MODE_UND ; switch to Undefined mode str sp,[r0], #4 ; save the current SP - mrs r3,SPSR + mrs r3,SPSR stm r0!,{r3,lr} ; save the current SPSR, LR cps #MODE_IRQ ; switch to IRQ mode str sp,[r0], #4 ; save the current SP - mrs r3,SPSR + mrs r3,SPSR stm r0!,{r3,lr} ; save the current SPSR, LR cps #MODE_FIQ ; switch to FIQ mode str SP,[r0], #4 ; save the current SP - mrs r3,SPSR + mrs r3,SPSR stm r0!,{r8-r12,lr} ; save the current SPSR,r8-r12,LR msr CPSR_cxsf, r2 ; switch back to original mode bx lr @@ -243,23 +243,23 @@ restore_banked_registers FUNCTION cmp r3, #MODE_HYP ; instructions to restore the banked registers beq rest_in_hyp ; without changing the mode - cps #MODE_SYS ; switch to System mode - ldr sp,[r0],#4 ; restore the User SP + cps #MODE_SYS ; switch to System mode + ldr sp,[r0],#4 ; restore the User SP ldr lr,[r0],#4 ; restore the User LR - cps #MODE_ABT ; switch to Abort mode - ldr sp,[r0],#4 ; restore the current SP - ldm r0!,{r3,lr} ; restore the current LR + cps #MODE_ABT ; switch to Abort mode + ldr sp,[r0],#4 ; restore the current SP + ldm r0!,{r3,lr} ; restore the current LR msr SPSR_fsxc,r3 ; restore the current SPSR - cps #MODE_UND ; switch to Undefined mode - ldr sp,[r0],#4 ; restore the current SP - ldm r0!,{r3,lr} ; restore the current LR + cps #MODE_UND ; switch to Undefined mode + ldr sp,[r0],#4 ; restore the current SP + ldm r0!,{r3,lr} ; restore the current LR msr SPSR_fsxc,r3 ; restore the current SPSR - cps #MODE_IRQ ; switch to IRQ mode - ldr sp,[r0],#4 ; restore the current SP - ldm r0!,{r3,lr} ; restore the current LR + cps #MODE_IRQ ; switch to IRQ mode + ldr sp,[r0],#4 ; restore the current SP + ldm r0!,{r3,lr} ; restore the current LR msr SPSR_fsxc,r3 ; restore the current SPSR - cps #MODE_FIQ ; switch to FIQ mode - ldr sp,[r0],#4 ; restore the current SP + cps #MODE_FIQ ; switch to FIQ mode + ldr sp,[r0],#4 ; restore the current SP ldm r0!,{r8-r12,lr} ; restore the current r8-r12,LR msr SPSR_fsxc,r4 ; restore the current SPSR msr CPSR_cxsf, r2 ; switch back to original mode @@ -274,53 +274,53 @@ rest_in_hyp msr SPSR_und, r2 msr LR_und, r3 - ldm r0!, {r1-r3} + ldm r0!, {r1-r3} msr SP_abt, r1 msr SPSR_abt, r2 msr LR_abt, r3 - ldm r0!, {r1-r3} + ldm r0!, {r1-r3} msr SP_svc, r1 msr SPSR_svc, r2 msr LR_svc, r3 - ldm r0!, {r1-r3} + ldm r0!, {r1-r3} msr SP_irq, r1 msr SPSR_irq, r2 msr LR_irq, r3 - + ldm r0!, {r1-r3} msr SP_fiq, r1 msr SPSR_fiq, r2 - msr LR_fiq, r3 + msr LR_fiq, r3 ldm r0!, {r1-r3} msr r8_fiq, r1 msr r9_fiq, r2 - msr r10_fiq, r3 + msr r10_fiq, r3 ldm r0!, {r1-r2} msr r11_fiq, r1 msr r12_fiq, r2 - - bx lr + + bx lr ENDFUNC - + save_cp15 FUNCTION ; CSSELR Cache Size Selection Register mrc p15,2,r3,c0,c0,0 str r3,[r0], #4 - ; IMPLEMENTATION DEFINED - proprietary features: + ; IMPLEMENTATION DEFINED - proprietary features: ; (CP15 register 15, TCM support, lockdown support, etc.) ; NOTE: IMP DEF registers might have save and restore order that relate - ; to other CP15 registers or logical grouping requirements and can + ; to other CP15 registers or logical grouping requirements and can ; therefore occur at any point in this sequence. bx lr ENDFUNC - + restore_cp15 FUNCTION ; CSSELR – Cache Size Selection Register ldr r3,[r0], #4 @@ -328,7 +328,7 @@ restore_cp15 FUNCTION bx lr ENDFUNC - + ; Function called with two arguments: ; r0 contains address to store control registers ; r1 is non-zero if we are Secure @@ -354,16 +354,16 @@ save_control_registers FUNCTION ; The next two registers are only present if ThumbEE is implemented mrc p15, 0, r1, c0, c1, 0 ; Read ID_PFR0 tst r1, #PFR0_THUMB_EE_SUPPORT - mrcne p14,6,r1,c0,c0,0 ; TEECR + mrcne p14,6,r1,c0,c0,0 ; TEECR mrcne p14,6,r2,c1,c0,0 ; TEEHBR stmne r0!, {r1, r2} - + mrc p14,7,r1,c1,c0,0 ; JOSCR mrc p14,7,r2,c2,c0,0 ; JMCR stm r0!, {r1, r2} bx lr ENDFUNC - + ; Function called with two arguments: ; r0 contains address to read control registers @@ -455,7 +455,7 @@ restore_mmu FUNCTION bx lr ENDFUNC - + save_mpu FUNCTION mrc p15, 0, r1, c0, c0, 4 ; Read MPUIR and r1, r1, #0xff00 @@ -475,7 +475,7 @@ save_mpu FUNCTION 20 bx lr ENDFUNC - + restore_mpu FUNCTION mrc p15, 0, r1, c0, c0, 4 ; Read MPUIR and r1, r1, #0xff00 @@ -500,7 +500,7 @@ save_vfp FUNCTION ; FPU state save/restore. ; FPSID,MVFR0 and MVFR1 don't get serialized/saved (Read Only). mrc p15,0,r3,c1,c0,2 ; CPACR allows CP10 and CP11 access - ORR r2,r3,#0xF00000 + ORR r2,r3,#0xF00000 mcr p15,0,r2,c1,c0,2 isb mrc p15,0,r2,c1,c0,2 @@ -509,7 +509,7 @@ save_vfp FUNCTION beq %f0 movs r2, #0 b %f2 - + 0 ; Save configuration registers and enable. vmrs r12,FPEXC str r12,[r0],#4 ; Save the FPEXC @@ -518,7 +518,7 @@ save_vfp FUNCTION vmsr FPEXC,r2 vmrs r2,FPSCR str r2,[r0],#4 ; Save the FPSCR - ; Store the VFP-D16 registers. + ; Store the VFP-D16 registers. vstm r0!, {D0-D15} ; Check for Advanced SIMD/VFP-D32 support vmrs r2,MVFR0 @@ -528,7 +528,7 @@ save_vfp FUNCTION ; Store the Advanced SIMD/VFP-D32 additional registers. vstm r0!, {D16-D31} - ; IMPLEMENTATION DEFINED: save any subarchitecture defined state + ; IMPLEMENTATION DEFINED: save any subarchitecture defined state ; NOTE: Don't change the order of the FPEXC and CPACR restores 1 vmsr FPEXC,r12 ; Restore the original En bit of FPU. @@ -543,12 +543,12 @@ restore_vfp FUNCTION ; serialized (RO). ; Modify CPACR to allow CP10 and CP11 access mrc p15,0,r1,c1,c0,2 - ORR r2,r1,#0x00F00000 + ORR r2,r1,#0x00F00000 mcr p15,0,r2,c1,c0,2 ; Enable FPU access to save/restore the rest of registers. ldr r2,=0x40000000 vmsr FPEXC, r2 - ; Recover FPEXC and FPSCR. These will be restored later. + ; Recover FPEXC and FPSCR. These will be restored later. ldm r0!,{r3,r12} ; Restore the VFP-D16 registers. vldm r0!, {D0-D15} @@ -561,12 +561,12 @@ restore_vfp FUNCTION ; Store the Advanced SIMD/VFP-D32 additional registers. vldm r0!, {D16-D31} - ; IMPLEMENTATION DEFINED: restore any subarchitecture defined state + ; IMPLEMENTATION DEFINED: restore any subarchitecture defined state 0 ; Restore configuration registers and enable. ; Restore FPSCR _before_ FPEXC since FPEXC could disable FPU ; and make setting FPSCR unpredictable. - vmsr FPSCR,r12 + vmsr FPSCR,r12 vmsr FPEXC,r3 ; Restore FPEXC after FPSCR ; Restore CPACR mcr p15,0,r1,c1,c0,2 @@ -577,7 +577,7 @@ restore_vfp FUNCTION ; If r1 is 0, we assume that the OS is not using the Virtualization extensions, ; and that the warm boot code will set up CNTHCTL correctly. If r1 is non-zero ; then CNTHCTL is saved and restored - ; CNTP_CVAL will be preserved as it is in the always-on domain. + ; CNTP_CVAL will be preserved as it is in the always-on domain. save_generic_timer FUNCTION mrc p15,0,r2,c14,c2,1 ; read CNTP_CTL |