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/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
* above copyright notice, this list of conditions and
* the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
*/
/*
* Master interrupt controller driver - talks to real IC and dispatches
* * interrupts to slave ICs or monitor drivers as appropriate
*/
#ifndef _INT_MASTER_H_
#define _INT_MASTER_H_
#include "bl.h"
#define INT_ENABLED 0x1 /* Interrupt is enabled, something to pass it on to */
#define INT_ACTIVE 0x2 /* Interrupt is currently actually disabled at the real controller because it is active */
#define INT_TRIGGER 0
#define INT_ENABLE 1
#define INT_DISABLE 2
#define INT_GETRAW 3
#define INT_UNTRIGGER 4
extern unsigned async_switchover;
vm_context *handle_interrupt(vm_context * context);
int gic_masterhandler(void *ptr, unsigned int num, unsigned int op);
void gic_masterinit(void);
void gic_deactivate_int(unsigned int num);
void gic_setup_secure(unsigned, unsigned);
void enable_2ndstage(void);
void setup_hcr(void);
void test_vgic(void);
#endif
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