diff options
| author | Steve Capper <steve.capper@linaro.org> | 2014-07-02 11:46:23 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-07-25 12:59:06 +0100 |
| commit | a95eca36ffbf8891d1e1a20d5c4a237f6d8f6a1f (patch) | |
| tree | dc8eaa34513ceafa6977c4a1148867d90801f324 /arch/x86/include/uapi/asm/msr-index.h | |
| parent | 6dca4f12e885d399d7a6fb9ab396981153886f9e (diff) | |
arm64: mm: Make icache synchronisation logic huge page aware
The __sync_icache_dcache routine will only flush the dcache for the
first page of a compound page, potentially leading to stale icache
data residing further on in a hugetlb page.
This patch addresses this issue by taking into consideration the
order of the page when flushing the dcache.
Reported-by: Mark Brown <broonie@linaro.org>
Tested-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: <stable@vger.kernel.org> # v3.11+
(cherry picked from commit 923b8f5044da753e4985ab15c1374ced2cdf616c)
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'arch/x86/include/uapi/asm/msr-index.h')
0 files changed, 0 insertions, 0 deletions