diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2012-07-14 19:09:17 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-03 13:12:52 +1000 |
| commit | 3863c9bc887e9638a9d905d55f6038641ece78d6 (patch) | |
| tree | 923decce50fc9f0ed28e04d5ad83d6518162bad0 /drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | |
| parent | 8a9b889e668a5bc2f4031015fe4893005c43403d (diff) | |
drm/nouveau/instmem: completely new implementation, as a subdev module
v2 (Ben Skeggs):
- some fixes for 64KiB PAGE_SIZE
- fix porting issues in (currently unused) nv41/nv44 pciegart code
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c index df53b9f27208..65a670f92a07 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c @@ -31,8 +31,6 @@ #include "nouveau_util.h" #include <core/ramht.h> -#include <core/subdev/instmem/nv04.h> - static struct ramfc_desc { unsigned bits:6; unsigned ctxs:5; @@ -104,7 +102,7 @@ nv40_fifo_context_new(struct nouveau_channel *chan, int engine) /* initialise default fifo context */ nv_wo32(priv->ramfc, fctx->ramfc + 0x00, chan->pushbuf_base); nv_wo32(priv->ramfc, fctx->ramfc + 0x04, chan->pushbuf_base); - nv_wo32(priv->ramfc, fctx->ramfc + 0x0c, chan->pushbuf->pinst >> 4); + nv_wo32(priv->ramfc, fctx->ramfc + 0x0c, chan->pushbuf->addr >> 4); nv_wo32(priv->ramfc, fctx->ramfc + 0x18, 0x30000000 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | @@ -144,8 +142,8 @@ nv40_fifo_init(struct drm_device *dev, int engine) nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | ((dev_priv->ramht->bits - 9) << 16) | - (dev_priv->ramht->gpuobj->pinst >> 8)); - nv_wr32(dev, NV03_PFIFO_RAMRO, priv->ramro->pinst >> 8); + (dev_priv->ramht->gpuobj->addr >> 8)); + nv_wr32(dev, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); switch (dev_priv->chipset) { case 0x47: @@ -163,7 +161,7 @@ nv40_fifo_init(struct drm_device *dev, int engine) default: nv_wr32(dev, 0x002230, 0x00000000); nv_wr32(dev, 0x002220, ((nvfb_vram_size(dev) - 512 * 1024 + - priv->ramfc->pinst) >> 16) | + priv->ramfc->addr) >> 16) | 0x00030000); break; } @@ -189,15 +187,14 @@ int nv40_fifo_create(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nv04_instmem_priv *imem = dev_priv->engine.instmem.priv; struct nv40_fifo_priv *priv; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; - nouveau_gpuobj_ref(imem->ramro, &priv->ramro); - nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); + nouveau_gpuobj_ref(nvimem_ramro(dev), &priv->ramro); + nouveau_gpuobj_ref(nvimem_ramfc(dev), &priv->ramfc); priv->base.base.destroy = nv04_fifo_destroy; priv->base.base.init = nv40_fifo_init; |