juno: Improve TZC-400 initialisation code

 - Distinguish Juno specific from platform agnostic constants
 - Define constants for Juno TZC-400 NSAID

3 files changed, 31 insertions, 20 deletions

diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c
index e671615..7fe96f2 100644
--- a/plat/juno/bl1_plat_setup.c
+++ b/plat/juno/bl1_plat_setup.c
@@ -34,6 +34,7 @@
 #include <bl1.h>
 #include <console.h>
 #include <cci400.h>
+#include <tzc400.h>
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
@@ -150,14 +151,6 @@ static void init_nic400(void)
 }
 
 
-#define TZC400_GATE_KEEPER_REG            0x008
-#define TZC400_REGION_ATTRIBUTES_0_REG    0x110
-#define TZC400_REGION_ID_ACCESS_0_REG     0x114
-
-#define TZC400_NSAID_WR_EN	(1 << 16)
-#define TZC400_NSAID_RD_EN	(1 << 0)
-#define TZC400_NSAID_RD_RW	(TZC400_NSAID_WR_EN | TZC400_NSAID_RD_EN)
-
 static void init_tzc400(void)
 {
 	/* Enable all filter units available */
@@ -174,17 +167,17 @@ static void init_tzc400(void)
 	 * Non-Secure World
 	 */
 	mmio_write_32(TZC400_BASE + TZC400_REGION_ID_ACCESS_0_REG,
-		(TZC400_NSAID_RD_RW << 0) |	/* CCI400 */
-		(TZC400_NSAID_RD_RW << 1) |	/* PCIE */
-		(TZC400_NSAID_RD_RW << 2) |	/* HDLCD0 */
-		(TZC400_NSAID_RD_RW << 3) |	/* HDLCD1 */
-		(TZC400_NSAID_RD_RW << 4) |	/* USB */
-		(TZC400_NSAID_RD_RW << 5) |	/* DMA330 */
-		(TZC400_NSAID_RD_RW << 6) |	/* THINLINKS */
-		(TZC400_NSAID_RD_RW << 9) |	/* AP */
-		(TZC400_NSAID_RD_RW << 10) |	/* GPU */
-		(TZC400_NSAID_RD_RW << 11) |	/* SCP */
-		(TZC400_NSAID_RD_RW << 12)	/* CORESIGHT */
+		(TZC400_NSAID_RD_RW << TZC400_NSAID_CCI400)	|
+		(TZC400_NSAID_RD_RW << TZC400_NSAID_PCIE)	|
+		(TZC400_NSAID_RD_RW << TZC400_NSAID_HDLCD0)	|
+		(TZC400_NSAID_RD_RW << TZC400_NSAID_HDLCD1)	|
+		(TZC400_NSAID_RD_RW << TZC400_NSAID_USB)	|
+		(TZC400_NSAID_RD_RW << TZC400_NSAID_DMA330)	|
+		(TZC400_NSAID_RD_RW << TZC400_NSAID_THINLINKS)	|
+		(TZC400_NSAID_RD_RW << TZC400_NSAID_AP)		|
+		(TZC400_NSAID_RD_RW << TZC400_NSAID_GPU)	|
+		(TZC400_NSAID_RD_RW << TZC400_NSAID_SCP)	|
+		(TZC400_NSAID_RD_RW << TZC400_NSAID_CORESIGHT)
 		);
 }
 
diff --git a/plat/juno/platform.h b/plat/juno/platform.h
index 14a966a..0118aac 100644
--- a/plat/juno/platform.h
+++ b/plat/juno/platform.h
@@ -117,7 +117,6 @@
 /* Following covers Columbus Peripherals excluding NSROM and NSRAM  */
 #define DEVICE0_BASE		0x20000000
 #define DEVICE0_SIZE		0x0e000000
-#define TZC400_BASE		0x2a4a0000
 #define MHU_BASE		0x2b1f0000
 
 #define NSRAM_BASE		0x2e000000
@@ -268,6 +267,24 @@
 
 
 /*******************************************************************************
+ * TZC-400 related constants
+ ******************************************************************************/
+#define TZC400_BASE		0x2a4a0000
+
+#define TZC400_NSAID_CCI400	0  /* Note: Same as default NSAID!! HW fix in next revision */
+#define TZC400_NSAID_PCIE	1
+#define TZC400_NSAID_HDLCD0	2
+#define TZC400_NSAID_HDLCD1	3
+#define TZC400_NSAID_USB	4
+#define TZC400_NSAID_DMA330	5
+#define TZC400_NSAID_THINLINKS	6
+#define TZC400_NSAID_AP		9
+#define TZC400_NSAID_GPU	10
+#define TZC400_NSAID_SCP	11
+#define TZC400_NSAID_CORESIGHT	12
+
+
+/*******************************************************************************
  * Declarations and constants to access the mailboxes safely. Each mailbox is
  * aligned on the biggest cache line size in the platform. This is known only
  * to the platform as it might have a combination of integrated and external
diff --git a/plat/juno/platform.mk b/plat/juno/platform.mk
index 48616c5..039c771 100644
--- a/plat/juno/platform.mk
+++ b/plat/juno/platform.mk
@@ -29,6 +29,7 @@
 #
 
 PLAT_INCLUDES		:=	-Idrivers/arm/interconnect/cci-400	\
+				-Idrivers/arm/trustzone/tzc-400		\
 				-Idrivers/arm/peripherals/pl011		\
 				-Idrivers/power