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authorTushar Behera <tushar.behera@linaro.org>2013-04-15 15:43:45 +0530
committerAndrey Konovalov <andrey.konovalov@linaro.org>2013-06-18 01:24:44 +0400
commit86c08fa921a5839399bd13d23c535fde2e086c5a (patch)
treea1e30c0f6304881beccbcfd6049ccfc2c58b58e2
parent32a0a54987cb4ada1715eba62a4c8f15a08db224 (diff)
The Exynos 5250 includes an architected timer which is on core and very cheap to read. Enabling the architected timer can lead to a significant performance improvement for timer sensitive workloads such as TCP/IP. It turns out that both arch_sys_counter and mct-frc have a rating of 400. On bootup, arch_sys_counter is initialized first then the clocksource changes to mct-frc when that initialises later on. If the rating of mct-frc is reduced below 400, then arch_sys_counter becomes the default. Suggested-by: Steve Capper <steve.capper@linaro.org> Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
-rw-r--r--arch/arm/mach-exynos/mct.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 6cb48f5d67c2..c957b4fd01b0 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -161,6 +161,10 @@ static void __init exynos4_clocksource_init(void)
{
exynos4_mct_frc_start(0, 0);
+ if (soc_is_exynos5250()) {
+ mct_frc.rating = 399;
+ }
+
if (clocksource_register_hz(&mct_frc, clk_rate))
panic("%s: can't register clocksource\n", mct_frc.name);
}