aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-exynos
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/Kconfig1
-rw-r--r--arch/arm/mach-exynos/common.c20
-rw-r--r--arch/arm/mach-exynos/cpuidle.c20
-rw-r--r--arch/arm/mach-exynos/firmware.c8
-rw-r--r--arch/arm/mach-exynos/headsmp.S8
-rw-r--r--arch/arm/mach-exynos/hotplug.c2
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h1
-rw-r--r--arch/arm/mach-exynos/include/mach/pm-core.h4
-rw-r--r--arch/arm/mach-exynos/include/mach/uncompress.h6
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c1
-rw-r--r--arch/arm/mach-exynos/platsmp.c10
-rw-r--r--arch/arm/mach-exynos/pm.c48
-rw-r--r--arch/arm/mach-exynos/pm_domains.c6
-rw-r--r--arch/arm/mach-exynos/pmu.c24
14 files changed, 95 insertions, 64 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4c414af75ef0..6f1cac856669 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -31,6 +31,7 @@ config ARCH_EXYNOS4
config ARCH_EXYNOS5
bool "SAMSUNG EXYNOS5"
+ select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_AMBA
select CLKSRC_OF
select HAVE_ARM_SCU if SMP
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 1bf303f8dfe3..fd71a6fc8974 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -224,6 +224,15 @@ static struct map_desc exynos5250_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5420_iodesc[] __initdata = {
+ {
+ .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn = __phys_to_pfn(EXYNOS5420_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
@@ -265,7 +274,7 @@ static struct map_desc exynos5_iodesc[] __initdata = {
void exynos4_restart(enum reboot_mode mode, const char *cmd)
{
- __raw_writel(0x1, S5P_SWRESET);
+ writel_relaxed(0x1, S5P_SWRESET);
}
void exynos5_restart(enum reboot_mode mode, const char *cmd)
@@ -282,15 +291,15 @@ void exynos5_restart(enum reboot_mode mode, const char *cmd)
np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
addr = of_iomap(np, 0) + 0xbc;
- status = __raw_readl(addr);
+ status = readl_relaxed(addr);
addr = of_iomap(np, 0) + 0xcc;
- val = __raw_readl(addr);
+ val = readl_relaxed(addr);
val = (val & 0xffff0000) | (status & 0xffff);
}
- __raw_writel(val, addr);
+ writel_relaxed(val, addr);
}
static struct platform_device exynos_cpuidle = {
@@ -379,6 +388,9 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+
+ if (soc_is_exynos5420())
+ iotable_init(exynos5420_iodesc, ARRAY_SIZE(exynos5420_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index f57cb91f02aa..45aef491c16d 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -87,7 +87,7 @@ static struct cpuidle_driver exynos4_idle_driver = {
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos4_set_wakeupmask(void)
{
- __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
+ writel_relaxed(0x0000ff3e, S5P_WAKEUP_MASK);
}
static unsigned int g_pwr_ctrl, g_diag_reg;
@@ -127,15 +127,15 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
- __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
- __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
+ writel_relaxed(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
+ writel_relaxed(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
save_cpu_arch_register();
/* Setting Central Sequence Register for power down mode */
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = readl_relaxed(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ writel_relaxed(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
cpu_pm_enter();
cpu_suspend(0, idle_finisher);
@@ -154,14 +154,14 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = readl_relaxed(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ writel_relaxed(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
}
/* Clear wakeup state register */
- __raw_writel(0x0, S5P_WAKEUP_STAT);
+ writel_relaxed(0x0, S5P_WAKEUP_STAT);
return index;
}
@@ -198,7 +198,7 @@ static void __init exynos5_core_down_clk(void)
PWR_CTRL1_USE_CORE0_WFE | \
PWR_CTRL1_USE_CORE1_WFI | \
PWR_CTRL1_USE_CORE0_WFI;
- __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
+ writel_relaxed(tmp, EXYNOS5_PWR_CTRL1);
/*
* Enable arm clock up (on exiting idle). Set arm divider
@@ -211,7 +211,7 @@ static void __init exynos5_core_down_clk(void)
PWR_CTRL2_DUR_STANDBY1_VAL | \
PWR_CTRL2_CORE2_UP_RATIO | \
PWR_CTRL2_CORE1_UP_RATIO;
- __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
+ writel_relaxed(tmp, EXYNOS5_PWR_CTRL2);
}
static int exynos_cpuidle_probe(struct platform_device *pdev)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 932129ef26c6..e61df85d650e 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -17,6 +17,7 @@
#include <asm/firmware.h>
#include <mach/map.h>
+#include <plat/cpu.h>
#include "smc.h"
@@ -34,9 +35,12 @@ static int exynos_cpu_boot(int cpu)
static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
{
- void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
+ void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
- __raw_writel(boot_addr, boot_reg);
+ if (!soc_is_exynos5420())
+ boot_reg += 4 * cpu;
+
+ writel_relaxed(boot_addr, boot_reg);
return 0;
}
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index cdd9d91e9933..bec41317c4ac 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -12,6 +12,7 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/assembler.h>
/*
* exynos4 specific entry point for secondary CPUs. This provides
@@ -19,8 +20,13 @@
* ready for them to initialise.
*/
ENTRY(exynos4_secondary_startup)
+ /*
+ * ROM code operates in little endian mode, when we get control we
+ * need to switch it to big endian mode.
+ */
+ARM_BE8(setend be)
mrc p15, 0, r0, c0, c0, 5
- and r0, r0, #15
+ and r0, r0, #0xffffff
adr r4, 1f
ldmia r4, {r5, r6}
sub r4, r4, r5
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead530c6f8..dfba277a2fcb 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -96,7 +96,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
/* make cpu1 to be turned off at next WFI command */
if (cpu == 1)
- __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+ writel_relaxed(0, S5P_ARM_CORE1_CONFIGURATION);
/*
* here's the WFI
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b59d9ec..8c5be197bf75 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
+#define EXYNOS5420_PA_SYSRAM_NS 0x02073000
#define EXYNOS_PA_CHIPID 0x10000000
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index dc0697c2fa92..a12caa6fed49 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -37,8 +37,8 @@ static inline void s3c_pm_debug_init_uart(void)
static inline void s3c_pm_arch_prepare_irqs(void)
{
- __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
- __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+ writel_relaxed(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
+ writel_relaxed(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
}
static inline void s3c_pm_arch_stop_clocks(void)
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 5d7ce36be46f..7106a436883a 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -17,9 +17,15 @@
#include <mach/map.h>
#include <plat/uncompress.h>
+#include <linux/swab.h>
+
static unsigned int __raw_readl(unsigned int ptr)
{
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ return __swab32(*((volatile unsigned int *)ptr));
+#else
return *((volatile unsigned int *)ptr);
+#endif /* CONFIG_CPU_BIG_ENDIAN */
}
static void arch_detect_cpu(void)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 37ea261f0f6c..609a811e1a2c 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -73,6 +73,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.smp = smp_ops(exynos_smp_ops),
.map_io = exynos_init_io,
+ .init_early = exynos_firmware_init,
.init_machine = exynos5_dt_machine_init,
.init_late = exynos_init_late,
.dt_compat = exynos5_dt_compat,
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 2cf56b977018..4c7fafb4e514 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -109,14 +109,14 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
write_pen_release(phys_cpu);
- if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
- __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ if (!(readl_relaxed(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+ writel_relaxed(S5P_CORE_LOCAL_PWR_EN,
S5P_ARM_CORE1_CONFIGURATION);
timeout = 10;
/* wait max 10 ms until cpu1 is on */
- while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+ while ((readl_relaxed(S5P_ARM_CORE1_STATUS)
& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
@@ -149,7 +149,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
* and fall back to boot register if it fails.
*/
if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
- __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+ writel_relaxed(boot_addr, cpu_boot_reg(phys_cpu));
call_firmware_op(cpu_boot, phys_cpu);
@@ -224,7 +224,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
boot_addr = virt_to_phys(exynos4_secondary_startup);
if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
- __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+ writel_relaxed(boot_addr, cpu_boot_reg(phys_cpu));
}
}
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e00025bbbe89..f429e34e7280 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -130,19 +130,19 @@ static void exynos_pm_prepare(void)
} else {
s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
- tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
+ tmp = readl_relaxed(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
- __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
+ writel_relaxed(tmp, EXYNOS5_JPEG_MEM_OPTION);
}
/* Set value of power down register for sleep mode */
exynos_sys_powerdown_conf(SYS_SLEEP);
- __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
+ writel_relaxed(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
- __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
+ writel_relaxed(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
/* Before enter central sequence mode, clock src register have to set */
@@ -187,7 +187,7 @@ static void exynos4_restore_pll(void)
locktime = (3000 / pll_in_rate) * p_div;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
- __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
+ writel_relaxed(lockcnt, EXYNOS4_EPLL_LOCK);
s3c_pm_do_restore_core(exynos4_epll_save,
ARRAY_SIZE(exynos4_epll_save));
@@ -205,7 +205,7 @@ static void exynos4_restore_pll(void)
locktime = 750;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
- __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
+ writel_relaxed(lockcnt, EXYNOS4_VPLL_LOCK);
s3c_pm_do_restore_core(exynos4_vpll_save,
ARRAY_SIZE(exynos4_vpll_save));
@@ -216,13 +216,13 @@ static void exynos4_restore_pll(void)
do {
if (epll_wait) {
- pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
+ pll_con = readl_relaxed(EXYNOS4_EPLL_CON0);
if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
epll_wait = 0;
}
if (vpll_wait) {
- pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
+ pll_con = readl_relaxed(EXYNOS4_VPLL_CON0);
if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
vpll_wait = 0;
}
@@ -247,9 +247,9 @@ static __init int exynos_pm_drvinit(void)
/* All wakeup disable */
- tmp = __raw_readl(S5P_WAKEUP_MASK);
+ tmp = readl_relaxed(S5P_WAKEUP_MASK);
tmp |= ((0xFF << 8) | (0x1F << 1));
- __raw_writel(tmp, S5P_WAKEUP_MASK);
+ writel_relaxed(tmp, S5P_WAKEUP_MASK);
if (!soc_is_exynos5250()) {
pll_base = clk_get(NULL, "xtal");
@@ -270,14 +270,14 @@ static int exynos_pm_suspend(void)
/* Setting Central Sequence Register for power down mode */
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = readl_relaxed(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ writel_relaxed(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* Setting SEQ_OPTION register */
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
- __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+ writel_relaxed(tmp, S5P_CENTRAL_SEQ_OPTION);
if (!soc_is_exynos5250()) {
/* Save Power control register */
@@ -304,12 +304,12 @@ static void exynos_pm_resume(void)
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = readl_relaxed(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ writel_relaxed(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* clear the wakeup state register */
- __raw_writel(0x0, S5P_WAKEUP_STAT);
+ writel_relaxed(0x0, S5P_WAKEUP_STAT);
/* No need to perform below restore code */
goto early_wakeup;
}
@@ -329,13 +329,13 @@ static void exynos_pm_resume(void)
/* For release retention */
- __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_GPIO_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_UART_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_MMCA_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_MMCB_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_EBIA_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_EBIB_OPTION);
if (soc_is_exynos5250())
s3c_pm_do_restore(exynos5_sys_save,
@@ -354,7 +354,7 @@ static void exynos_pm_resume(void)
early_wakeup:
/* Clear SLEEP mode set in INFORM1 */
- __raw_writel(0x0, S5P_INFORM1);
+ writel_relaxed(0x0, S5P_INFORM1);
return;
}
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 8fd24882f0b1..10b14d0dc12f 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -47,12 +47,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
base = pd->base;
pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
- __raw_writel(pwr, base);
+ writel_relaxed(pwr, base);
/* Wait max 1ms */
timeout = 10;
- while ((__raw_readl(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) {
+ while ((readl_relaxed(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) {
if (!timeout) {
op = (power_on) ? "enable" : "disable";
pr_err("Power domain %s %s failed\n", domain->name, op);
@@ -174,7 +174,7 @@ static __init int exynos4_pm_init_power_domain(void)
platform_set_drvdata(pdev, pd);
- on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
+ on = readl_relaxed(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
pm_genpd_init(&pd->pd, NULL, !on);
}
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 05c7ce15322a..d667b15a697f 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -347,27 +347,27 @@ static void exynos5_init_pmu(void)
* Enable both SC_FEEDBACK and SC_COUNTER
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
- tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
+ tmp = readl_relaxed(exynos5_list_both_cnt_feed[i]);
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
EXYNOS5_USE_SC_COUNTER);
- __raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
+ writel_relaxed(tmp, exynos5_list_both_cnt_feed[i]);
}
/*
* SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
*/
- tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
+ tmp = readl_relaxed(EXYNOS5_ARM_COMMON_OPTION);
tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
- __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
+ writel_relaxed(tmp, EXYNOS5_ARM_COMMON_OPTION);
/*
* Disable WFI/WFE on XXX_OPTION
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
- tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
+ tmp = readl_relaxed(exynos5_list_diable_wfi_wfe[i]);
tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
EXYNOS5_OPTION_USE_STANDBYWFI);
- __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
+ writel_relaxed(tmp, exynos5_list_diable_wfi_wfe[i]);
}
}
@@ -379,12 +379,12 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
exynos5_init_pmu();
for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
- __raw_writel(exynos_pmu_config[i].val[mode],
+ writel_relaxed(exynos_pmu_config[i].val[mode],
exynos_pmu_config[i].reg);
if (soc_is_exynos4412()) {
for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
- __raw_writel(exynos4412_pmu_config[i].val[mode],
+ writel_relaxed(exynos4412_pmu_config[i].val[mode],
exynos4412_pmu_config[i].reg);
}
}
@@ -406,13 +406,13 @@ static int __init exynos_pmu_init(void)
* When SYS_WDTRESET is set, watchdog timer reset request
* is ignored by power management unit.
*/
- value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
+ value = readl_relaxed(EXYNOS5_AUTO_WDTRESET_DISABLE);
value &= ~EXYNOS5_SYS_WDTRESET;
- __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
+ writel_relaxed(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
- value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
+ value = readl_relaxed(EXYNOS5_MASK_WDTRESET_REQUEST);
value &= ~EXYNOS5_SYS_WDTRESET;
- __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+ writel_relaxed(value, EXYNOS5_MASK_WDTRESET_REQUEST);
exynos_pmu_config = exynos5250_pmu_config;
pr_info("EXYNOS5250 PMU Initialize\n");
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-09 22:49:46 +0000