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authorAbhimanyu Kapur <abhimany@codeaurora.org>2014-02-06 22:03:02 -0800
committerSrinivas Kandagatla <srinivas.kandagatla@linaro.org>2015-11-17 09:22:20 +0000
commit9e0ff092483113b186e9bfff0e95aa5fbd94e1d5 (patch)
tree3f7fdb48bee374c998a713810874fa4617f64b4d /Documentation
parentde29cbebde4770b22f51d4cc22fb7bbbc91ca3fe (diff)
arm64: qcom: add cpu operations
Add qcom cpu operations for arm-v8 cpus. Implement secondary cpu boot ops As a part of this change update device tree documentation for: 1. Arm cortex-a ACC device which provides percpu reg 2. Armv8 cortex-a compatible string in arm/cpus.txt Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/cpus.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/msm/acc.txt19
2 files changed, 21 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 91e6e5c478d0..259c50f0a720 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -185,6 +185,8 @@ nodes to be present and contain the properties described below.
be one of:
"psci"
"spin-table"
+ "qcom,arm-cortex-acc"
+
# On ARM 32-bit systems this property is optional and
can be one of:
"allwinner,sun6i-a31"
diff --git a/Documentation/devicetree/bindings/arm/msm/acc.txt b/Documentation/devicetree/bindings/arm/msm/acc.txt
new file mode 100644
index 000000000000..ae2d7253b363
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/acc.txt
@@ -0,0 +1,19 @@
+Application Processor Sub-system (APSS) Application Clock Controller (ACC)
+
+The ACC provides clock, power domain, and reset control to a CPU. There is one ACC
+register region per CPU within the APSS remapped region as well as an alias register
+region that remaps accesses to the ACC associated with the CPU accessing the region.
+
+Required properties:
+- compatible: Must be "qcom,arm-cortex-acc"
+- reg: The first element specifies the base address and size of
+ the register region. An optional second element specifies
+ the base address and size of the alias register region.
+
+Example:
+
+ clock-controller@b088000 {
+ compatible = "qcom,arm-cortex-acc";
+ reg = <0x0b088000 0x1000>,
+ <0x0b008000 0x1000>;
+ }