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PCIe support on Neoverse N1 SDP
===============================
.. section-numbering::
:suffix: .
.. contents::
Support for PCIe in Arm's Neoverse N1 SDP software releases
-----------------------------------------------------------
The supplied Neoverse software stack includes support for PCIe. However there are
two issues (detailed below) with the PCIe root port hardware IP present on
Neoverse N1 SDP. These impact generic code in EDK II UEFI and Linux.
Arm is maintaining patches and implementing workarounds in the following Linaro
git repository: http://git.linaro.org/landing-teams/working/arm/n1sdp-pcie-quirk.git/
The patches will be regularly rebased so that they apply cleanly to the relevant
components (SCP-firmware, mainline Linux, and upstream EDK II UEFI).
The git repository also provides a shell script, patch_apply.sh.
The patches are applied automatically as part of the Arm reference platform software
workspace sync process, providing a software stack with full PCIe support. However, note that
it is not possible to use an unmodified Linux distribution release on Neoverse N1SDP,
without patching and rebuilding the kernel shipped with that distribution.
SLVERR on PCIe device and function enumeration
--------------------------------------------------
Linux and EDK II UEFI use standardised PCIe enumeration code based
on the assumption that PCIe compliant root ports must return magic number 0xFFFFFFFF
when either a device is not connected or a function is not implemented.
The PCIe root port hardware IP on Neoverse N1 SDP boards instead asserts
an AXI SLVERR response, triggering a bus fault on the applications processor
performing PCIe enumeration.
A software workaround has been implemented in the System Control Processor (SCP)
that performs minimal PCIe enumeration and generates a bus/device/function (BDF)
table that it places in shared Non-secure SRAM. During this minimal enumeration,
the SCP ignores any bus faults from accessing PCIe configuration space,
effectively suppressing the non-compliant AXI SLVERR responses generated by the
PCIe root port hardware IP. Patches have also been applied to EDK II UEFI and Linux
to use the generated BDF table during their own PCIe enumeration routines.
Non-contiguous configuration space
----------------------------------
Linux and EDK II UEFI use standardised PCIe enumeration code based on the assumption
that the PCIe Enhanced Configuration Access Mechanism (ECAM) base address is the same
as the base address of the root port's configuration space. These assumptions are not
valid for N1SDP leading to issues identifying the root port during PCIe enumeration.
A software workaround has been added to the SCP that inserts the base address of the
PCIe root port's configuration space as the first word in the BDF table in shared
Non-secure SRAM in both EDK II UEFI and Linux. The generic PCIe code has been patched to
read the base address of the PCIe root port configuration space from the BDF table;
this base address is then automatically used whenever a given BDF is all zeroes.
PCIE Root Port config space supports only 32 bits R/W
-----------------------------------------------------
The root port configuration space supports only 32-bit accesses. However, standard UEFI and Linux
drivers may perform 8-bit and 16-bit read/write to this space which will end up in erroneous result.
To avoid this, software workarounds has been added to convert the 8-bit/16-bit access to 32-bit access
using read-modify-write method.
--------------
*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
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