ARM Ashbrook Platform SupportSS-SW-16.2-ashbrook

This patch adds support for the Ashbrook subsystem FVP as released in
the 16.2 Ashbrook software release.

Signed-off-by: James King <james.king@arm.com>

23 files changed, 859 insertions, 19 deletions

diff --git a/include/lib/aarch64/xlat_tables.h b/include/lib/aarch64/xlat_tables.h
index d21100e3f..da40cc238 100644
--- a/include/lib/aarch64/xlat_tables.h
+++ b/include/lib/aarch64/xlat_tables.h
@@ -37,6 +37,11 @@
  * enabling the MMU.
  */
 #define DISABLE_DCACHE		(1 << 0)
+#define TCR_MT_SHIFT		1
+#define TCR_MT_MASK		(0x7 << TCR_MT_SHIFT)
+#define TCR_MT(_flags)		((_flags) & TCR_MT_MASK)
+#define TCR_MT_DEFAULT		(0 << TCR_MT_SHIFT)
+#define TCR_MT_NON_CACHEABLE	(1 << TCR_MT_SHIFT)
 
 #ifndef __ASSEMBLY__
 #include <stdint.h>
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index e9eebaa09..cddfb811b 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -49,7 +49,8 @@
 void arm_configure_mmu_el1(unsigned long total_base,
 			unsigned long total_size,
 			unsigned long ro_start,
-			unsigned long ro_limit
+			unsigned long ro_limit,
+			unsigned int mem_type
 #if USE_COHERENT_MEM
 			, unsigned long coh_start,
 			unsigned long coh_limit
@@ -58,7 +59,8 @@ void arm_configure_mmu_el1(unsigned long total_base,
 void arm_configure_mmu_el3(unsigned long total_base,
 			unsigned long total_size,
 			unsigned long ro_start,
-			unsigned long ro_limit
+			unsigned long ro_limit,
+			unsigned int mem_type
 #if USE_COHERENT_MEM
 			, unsigned long coh_start,
 			unsigned long coh_limit
diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c
index 269743f78..2692f4bb9 100644
--- a/lib/aarch64/xlat_tables.c
+++ b/lib/aarch64/xlat_tables.c
@@ -352,10 +352,20 @@ void init_xlat_tables(void)
 		_tlbi_fct();						\
 									\
 		/* Set TCR bits as well. */				\
-		/* Inner & outer WBWA & shareable + T0SZ = 32 */	\
-		tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA |	\
-			TCR_RGN_INNER_WBA |				\
-			(64 - __builtin_ctzl(ADDR_SPACE_SIZE));		\
+		/* T0SZ = 32 */						\
+		if (TCR_MT(flags) == TCR_MT_DEFAULT) {			\
+			/* Inner & outer WBWA & shareable */		\
+			tcr = TCR_SH_INNER_SHAREABLE |			\
+				TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA |	\
+				(64 - __builtin_ctzl(ADDR_SPACE_SIZE));	\
+		} else {						\
+			/* Inner & outer non-cacheable non-shareable */	\
+			assert(TCR_MT(flags) == TCR_MT_NON_CACHEABLE);	\
+			tcr = TCR_SH_NON_SHAREABLE |			\
+				TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC |	\
+				(64 - __builtin_ctzl(ADDR_SPACE_SIZE));	\
+		}							\
+									\
 		tcr |= _tcr_extra;					\
 		write_tcr_el##_el(tcr);					\
 									\
diff --git a/plat/arm/board/enterprise/ashbrook_2/include/platform_oid.h b/plat/arm/board/enterprise/ashbrook_2/include/platform_oid.h
new file mode 100644
index 000000000..68c7a99a1
--- /dev/null
+++ b/plat/arm/board/enterprise/ashbrook_2/include/platform_oid.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "../../../../../../include/plat/arm/board/common/board_arm_oid.h"
+
+/*
+ * Required platform OIDs
+ * (Provided by included header)
+ */
diff --git a/plat/arm/board/enterprise/ashbrook_2/platform.mk b/plat/arm/board/enterprise/ashbrook_2/platform.mk
new file mode 100644
index 000000000..50d99aa31
--- /dev/null
+++ b/plat/arm/board/enterprise/ashbrook_2/platform.mk
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+include plat/arm/css/enterprise/css_enterprise.mk
+
+ENTERPRISE_BOARD	:=	plat/arm/board/enterprise
+
+PLAT_INCLUDES		+=	-I${ENTERPRISE_BOARD}/include		\
+				-I${ENTERPRISE_BOARD}/ashbrook_2/include
+
+PLAT_BL_COMMON_SOURCES	+=	${ENTERPRISE_BOARD}/board_enterprise_helper.S
+
+$(eval $(call add_define,ASHBROOK_2))
+
diff --git a/plat/arm/board/enterprise/ashbrook_5/include/platform_oid.h b/plat/arm/board/enterprise/ashbrook_5/include/platform_oid.h
new file mode 100644
index 000000000..68c7a99a1
--- /dev/null
+++ b/plat/arm/board/enterprise/ashbrook_5/include/platform_oid.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "../../../../../../include/plat/arm/board/common/board_arm_oid.h"
+
+/*
+ * Required platform OIDs
+ * (Provided by included header)
+ */
diff --git a/plat/arm/board/enterprise/ashbrook_5/platform.mk b/plat/arm/board/enterprise/ashbrook_5/platform.mk
new file mode 100644
index 000000000..f64076d07
--- /dev/null
+++ b/plat/arm/board/enterprise/ashbrook_5/platform.mk
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+include plat/arm/css/enterprise/css_enterprise.mk
+
+ENTERPRISE_BOARD	:=	plat/arm/board/enterprise
+
+PLAT_INCLUDES		+=	-I${ENTERPRISE_BOARD}/include		\
+				-I${ENTERPRISE_BOARD}/ashbrook_5/include
+
+PLAT_BL_COMMON_SOURCES	+=	${ENTERPRISE_BOARD}/board_enterprise_helper.S
+
+$(eval $(call add_define,ASHBROOK_5))
+
diff --git a/plat/arm/board/enterprise/board_enterprise_helper.S b/plat/arm/board/enterprise/board_enterprise_helper.S
new file mode 100644
index 000000000..605801189
--- /dev/null
+++ b/plat/arm/board/enterprise/board_enterprise_helper.S
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <asm_macros.S>
+#include <platform_def.h>
+
+#if defined (ASHBROOK_5)
+	.globl	plat_arm_calc_core_pos
+	/* -----------------------------------------------------
+	 *  unsigned int plat_arm_calc_core_pos(uint64_t mpidr)
+	 *  Helper function to calculate the core position.
+	 *  Ashbrook_5 is the platform with 2 cores per cluster
+	 *  CorePos = (ClusterID * 2 + CoreID)
+	 * -----------------------------------------------------
+	 */
+func plat_arm_calc_core_pos
+	and	x1, x0, #MPIDR_CPU_MASK
+	and	x0, x0, #MPIDR_CLUSTER_MASK
+	add	x0, x1, x0, LSR #7
+	ret
+endfunc plat_arm_calc_core_pos
+#endif
diff --git a/plat/arm/board/enterprise/include/platform_def.h b/plat/arm/board/enterprise/include/platform_def.h
new file mode 100644
index 000000000..1c4b3c6ab
--- /dev/null
+++ b/plat/arm/board/enterprise/include/platform_def.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <arm_def.h>
+#include <board_arm_def.h>
+#include <board_css_def.h>
+#include <common_def.h>
+#include <css_enterprise_def.h>
+#include <css_def.h>
+#include <soc_css_def.h>
+
+#if defined (ASHBROOK_2)
+#define PLAT_MAX_CORES_PER_CLUSTER	4
+#define PLAT_ARM_MAX_BL31_SIZE		0x28000
+#define PLAT_ARM_GICR_BASE		0x30800000
+#elif defined (ASHBROOK_5)
+#define PLAT_MAX_CORES_PER_CLUSTER	2
+#define PLAT_ARM_MAX_BL31_SIZE		0x20000
+#define PLAT_ARM_GICR_BASE		0x30400000
+#else
+#error ERROR: unsupported enterprise platform name!
+#endif
+
+/* CPU topology */
+#define PLAT_ARM_CLUSTER_COUNT		12
+#define PLATFORM_CORE_COUNT		(PLAT_ARM_CLUSTER_COUNT *	\
+					PLAT_MAX_CORES_PER_CLUSTER)
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/arm/common/aarch64/arm_common.c b/plat/arm/common/aarch64/arm_common.c
index c84a65b3a..80bd417ba 100644
--- a/plat/arm/common/aarch64/arm_common.c
+++ b/plat/arm/common/aarch64/arm_common.c
@@ -29,6 +29,7 @@
  */
 #include <arch.h>
 #include <arch_helpers.h>
+#include <assert.h>
 #include <mmio.h>
 #include <plat_arm.h>
 #include <platform_def.h>
@@ -51,40 +52,56 @@ extern const mmap_region_t plat_arm_mmap[];
 				   unsigned long total_size,		\
 				   unsigned long ro_start,		\
 				   unsigned long ro_limit,		\
+				   unsigned int mem_type,		\
 				   unsigned long coh_start,		\
 				   unsigned long coh_limit)		\
 	{								\
+		unsigned int type = MT_TYPE(mem_type);			\
+									\
 		mmap_add_region(total_base, total_base,			\
 				total_size,				\
-				MT_MEMORY | MT_RW | MT_SECURE);		\
+				type | MT_RW | MT_SECURE);		\
 		mmap_add_region(ro_start, ro_start,			\
 				ro_limit - ro_start,			\
-				MT_MEMORY | MT_RO | MT_SECURE);		\
+				type | MT_RO | MT_SECURE);		\
 		mmap_add_region(coh_start, coh_start,			\
 				coh_limit - coh_start,			\
 				MT_DEVICE | MT_RW | MT_SECURE);		\
 		mmap_add(plat_arm_get_mmap());				\
 		init_xlat_tables();					\
 									\
-		enable_mmu_el##_el(0);					\
+		if (type == MT_MEMORY) {				\
+			enable_mmu_el##_el(TCR_MT_DEFAULT);		\
+		} else {						\
+			assert(type == MT_NON_CACHEABLE);		\
+			enable_mmu_el##_el(TCR_MT_NON_CACHEABLE);	\
+		}							\
 	}
 #else
 #define DEFINE_CONFIGURE_MMU_EL(_el)					\
 	void arm_configure_mmu_el##_el(unsigned long total_base,	\
 				   unsigned long total_size,		\
 				   unsigned long ro_start,		\
-				   unsigned long ro_limit)		\
+				   unsigned long ro_limit,		\
+				   unsigned int mem_type)		\
 	{								\
+		unsigned int type = MT_TYPE(mem_type);			\
+									\
 		mmap_add_region(total_base, total_base,			\
 				total_size,				\
-				MT_MEMORY | MT_RW | MT_SECURE);		\
+				type | MT_RW | MT_SECURE);		\
 		mmap_add_region(ro_start, ro_start,			\
 				ro_limit - ro_start,			\
-				MT_MEMORY | MT_RO | MT_SECURE);		\
+				type | MT_RO | MT_SECURE);		\
 		mmap_add(plat_arm_get_mmap());				\
 		init_xlat_tables();					\
 									\
-		enable_mmu_el##_el(0);					\
+		if (type == MT_MEMORY) {				\
+			enable_mmu_el##_el(TCR_MT_DEFAULT);		\
+		} else {						\
+			assert(type == MT_NON_CACHEABLE);		\
+			enable_mmu_el##_el(TCR_MT_NON_CACHEABLE);	\
+		}							\
 	}
 #endif
 
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index 951f48a5b..e64351803 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -121,7 +121,8 @@ void arm_bl1_plat_arch_setup(void)
 	arm_configure_mmu_el3(bl1_tzram_layout.total_base,
 			      bl1_tzram_layout.total_size,
 			      BL1_RO_BASE,
-			      BL1_RO_LIMIT
+			      BL1_RO_LIMIT,
+			      MT_MEMORY
 #if USE_COHERENT_MEM
 			      , BL1_COHERENT_RAM_BASE,
 			      BL1_COHERENT_RAM_LIMIT
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index a528830a6..cf95639bf 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -237,7 +237,8 @@ void arm_bl2_plat_arch_setup(void)
 	arm_configure_mmu_el1(bl2_tzram_layout.total_base,
 			      bl2_tzram_layout.total_size,
 			      BL2_RO_BASE,
-			      BL2_RO_LIMIT
+			      BL2_RO_LIMIT,
+			      MT_MEMORY
 #if USE_COHERENT_MEM
 			      , BL2_COHERENT_RAM_BASE,
 			      BL2_COHERENT_RAM_LIMIT
diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c
index 5b7354b3e..b8daa0f14 100644
--- a/plat/arm/common/arm_bl2u_setup.c
+++ b/plat/arm/common/arm_bl2u_setup.c
@@ -105,7 +105,8 @@ void arm_bl2u_plat_arch_setup(void)
 	arm_configure_mmu_el1(BL2U_RO_LIMIT,
 			      BL31_LIMIT,
 			      BL2U_RO_BASE,
-			      BL2U_RO_LIMIT
+			      BL2U_RO_LIMIT,
+			      MT_MEMORY
 #if USE_COHERENT_MEM
 			      ,
 			      BL2U_COHERENT_RAM_BASE,
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 5cc8bfb1d..aa5af5487 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -252,7 +252,8 @@ void arm_bl31_plat_arch_setup(void)
 	arm_configure_mmu_el3(BL31_RO_BASE,
 			      (BL31_END - BL31_RO_BASE),
 			      BL31_RO_BASE,
-			      BL31_RO_LIMIT
+			      BL31_RO_LIMIT,
+			      MT_MEMORY
 #if USE_COHERENT_MEM
 			      , BL31_COHERENT_RAM_BASE,
 			      BL31_COHERENT_RAM_LIMIT
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index 2a67fd102..19aa4ef37 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -101,7 +101,8 @@ void tsp_plat_arch_setup(void)
 	arm_configure_mmu_el1(BL32_RO_BASE,
 			      (BL32_END - BL32_RO_BASE),
 			      BL32_RO_BASE,
-			      BL32_RO_LIMIT
+			      BL32_RO_LIMIT,
+			      MT_MEMORY
 #if USE_COHERENT_MEM
 			      , BL32_COHERENT_RAM_BASE,
 			      BL32_COHERENT_RAM_LIMIT
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index b6f94ac25..ffddf72f3 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -166,6 +166,18 @@ static void css_power_down_common(const psci_power_state_t *target_state)
 				 system_state);
 }
 
+/* CPU dynamic power off function for Ashbrook */
+static void css_power_down_suspend(const psci_power_state_t *target_state)
+{
+	/* Prevent interrupts from spuriously waking up this cpu */
+	plat_arm_gic_cpuif_disable();
+
+	/* Cluster is to be turned off, so disable coherency */
+	if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
+		plat_arm_interconnect_exit_coherency();
+	}
+}
+
 /*******************************************************************************
  * Handler called when a power domain is about to be turned off. The
  * target_state encodes the power state that each level should transition to.
@@ -190,7 +202,7 @@ void css_pwr_domain_suspend(const psci_power_state_t *target_state)
 		return;
 
 	assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
-	css_power_down_common(target_state);
+	css_power_down_suspend(target_state);
 }
 
 /*******************************************************************************
diff --git a/plat/arm/css/enterprise/css_enterprise.mk b/plat/arm/css/enterprise/css_enterprise.mk
new file mode 100644
index 000000000..f3f2a14da
--- /dev/null
+++ b/plat/arm/css/enterprise/css_enterprise.mk
@@ -0,0 +1,80 @@
+#
+# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+ENABLE_PLAT_COMPAT		:=	0
+
+COMMON_INC			:=	include/plat/arm/css/common
+COMMON_PLAT			:=	plat/arm/css/common
+ENTERPRISE_CSS			:=	plat/arm/css/enterprise
+
+ENTERPRISE_INTERCONNECT_SOURCES	:= 	drivers/arm/ccn/ccn.c		\
+					plat/arm/common/arm_ccn.c
+
+PLAT_INCLUDES		+=	-I${ENTERPRISE_CSS}/include		\
+				-I${COMMON_INC}				\
+				-I${COMMON_INC}/aarch64
+
+PLAT_BL_COMMON_SOURCES	+=	${COMMON_PLAT}/aarch64/css_helpers.S	\
+				${COMMON_INC}/aarch64/css_macros.S	\
+				${ENTERPRISE_CSS}/css_enterprise_plat.c	\
+				${ENTERPRISE_CSS}/css_enterprise_helper.S
+
+BL1_SOURCES		+=	${ENTERPRISE_INTERCONNECT_SOURCES}	\
+				lib/cpus/aarch64/cortex_a72.S		\
+				lib/cpus/aarch64/cortex_a53.S
+
+BL2_SOURCES		+=	${COMMON_PLAT}/css_bl2_setup.c		\
+				${COMMON_PLAT}/css_mhu.c		\
+				${COMMON_PLAT}/css_scpi.c		\
+				${ENTERPRISE_CSS}/css_enterprise_security.c
+
+BL31_SOURCES		+=	${COMMON_PLAT}/css_mhu.c		\
+				${COMMON_PLAT}/css_pm.c			\
+				${COMMON_PLAT}/css_scpi.c		\
+				lib/cpus/aarch64/cortex_a72.S		\
+				lib/cpus/aarch64/cortex_a53.S		\
+				drivers/arm/gic/common/gic_common.c	\
+				drivers/arm/gic/v3/gicv3_main.c		\
+				drivers/arm/gic/v3/gicv3_helpers.c	\
+				plat/common/plat_gicv3.c		\
+				plat/arm/common/arm_gicv3.c		\
+				${ENTERPRISE_INTERCONNECT_SOURCES}	\
+				${ENTERPRISE_CSS}/css_enterprise_topology.c
+
+$(eval $(call add_define,ENTERPRISE_PLAT))
+
+override CSS_LOAD_SCP_IMAGES	:=	0
+override NEED_BL2U		:=	no
+override ERROR_DEPRECATED	:=	1
+override ARM_BL31_IN_DRAM	:=	1
+
+include plat/arm/common/arm_common.mk
+include plat/arm/soc/common/soc_css.mk
+include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/css/enterprise/css_enterprise_helper.S b/plat/arm/css/enterprise/css_enterprise_helper.S
new file mode 100644
index 000000000..a85bf4246
--- /dev/null
+++ b/plat/arm/css/enterprise/css_enterprise_helper.S
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <asm_macros.S>
+#include <platform_def.h>
+
+	.globl	plat_is_my_cpu_primary
+
+	/* -----------------------------------------------------
+	 * unsigned int plat_is_my_cpu_primary (void);
+	 *
+	 * Find out whether the current cpu is the primary
+	 * cpu (applicable ony after a cold boot)
+	 * -----------------------------------------------------
+	 */
+func plat_is_my_cpu_primary
+	mov	x9, x30
+	bl	plat_my_core_pos
+	ldr	x1, =ENTERPRISE_BOOT_CFG_ADDR
+	ldr	x1, [x1]
+	ubfx	x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
+			#PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
+	cmp	x0, x1
+	cset	w0, eq
+	ret	x9
+endfunc plat_is_my_cpu_primary
diff --git a/plat/arm/css/enterprise/css_enterprise_plat.c b/plat/arm/css/enterprise/css_enterprise_plat.c
new file mode 100644
index 000000000..6e20159a1
--- /dev/null
+++ b/plat/arm/css/enterprise/css_enterprise_plat.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm_def.h>
+#include <bl_common.h>
+#include <ccn.h>
+#include <plat_arm.h>
+#include <platform.h>
+
+#if USE_COHERENT_MEM
+/*
+ * The next 2 constants identify the extents of the coherent memory region.
+ * These addresses are used by the MMU setup code and therefore they must be
+ * page-aligned.  It is the responsibility of the linker script to ensure that
+ * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
+ * page-aligned addresses.
+ */
+#define PLAT_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
+#define PLAT_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
+#endif
+
+#define PLAT_RO_BASE (unsigned long)(&__RO_START__)
+#define PLAT_RO_LIMIT (unsigned long)(&__RO_END__)
+#if IMAGE_BL31
+#define PLAT_BL31_END (unsigned long)(&__BL31_END__)
+#endif
+
+#define ENTERPRISE_MAP_FLASH0_RO	MAP_REGION_FLAT(V2M_FLASH0_BASE,\
+						V2M_FLASH0_SIZE,	\
+						MT_DEVICE | MT_RO | MT_SECURE)
+/*
+ * Table of regions for different BL stages to map using the MMU.
+ * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
+ * arm_configure_mmu_elx() will give the available subset of that.
+ *
+ * Replace or extend the below regions as required
+ */
+#if IMAGE_BL1
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	ENTERPRISE_MAP_FLASH0_RO,
+	CSS_ENTERPRISE_MAP_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+	{0}
+};
+#endif
+#if IMAGE_BL2
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	ENTERPRISE_MAP_FLASH0_RO,
+	CSS_ENTERPRISE_MAP_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+	ARM_MAP_NS_DRAM1,
+#if ARM_BL31_IN_DRAM
+	ARM_MAP_BL31_SEC_DRAM,
+#endif
+	{0}
+};
+#endif
+#if IMAGE_BL31
+const mmap_region_t plat_arm_mmap[] = {
+	ARM_MAP_SHARED_RAM,
+	V2M_MAP_IOFPGA,
+	CSS_ENTERPRISE_MAP_DEVICE,
+	SOC_CSS_MAP_DEVICE,
+	{0}
+};
+#endif
+
+ARM_CASSERT_MMAP
+
+#if IMAGE_BL1
+void bl1_plat_arch_setup(void)
+{
+	meminfo_t *bl1_tzram_layout;
+
+	bl1_tzram_layout = bl1_plat_sec_mem_layout();
+	arm_configure_mmu_el3(bl1_tzram_layout->total_base,
+			      bl1_tzram_layout->total_size,
+			      BL1_RO_BASE,
+			      BL1_RO_LIMIT,
+			      MT_NON_CACHEABLE
+#if USE_COHERENT_MEM
+			      , PLAT_COHERENT_RAM_BASE,
+			      PLAT_COHERENT_RAM_LIMIT
+#endif
+			     );
+}
+#endif
+
+#if IMAGE_BL2
+void bl2_plat_arch_setup(void)
+{
+	arm_configure_mmu_el1(BL2_BASE,
+			      BL2_LIMIT - BL2_BASE,
+			      PLAT_RO_BASE,
+			      PLAT_RO_LIMIT,
+			      MT_NON_CACHEABLE
+#if USE_COHERENT_MEM
+			      , PLAT_COHERENT_RAM_BASE,
+			      PLAT_COHERENT_RAM_LIMIT
+#endif
+			      );
+}
+#endif
+
+#if IMAGE_BL31
+void bl31_plat_arch_setup(void)
+{
+	arm_configure_mmu_el3(PLAT_RO_BASE,
+			      (PLAT_BL31_END - PLAT_RO_BASE),
+			      PLAT_RO_BASE,
+			      PLAT_RO_LIMIT,
+			      MT_MEMORY
+#if USE_COHERENT_MEM
+			      , PLAT_COHERENT_RAM_BASE,
+			      PLAT_COHERENT_RAM_LIMIT
+#endif
+			      );
+}
+#endif
diff --git a/plat/arm/css/enterprise/css_enterprise_security.c b/plat/arm/css/enterprise/css_enterprise_security.c
new file mode 100644
index 000000000..e9b3594b8
--- /dev/null
+++ b/plat/arm/css/enterprise/css_enterprise_security.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arm_config.h>
+#include <plat_arm.h>
+
+/*
+ * We assume that all security programming is done by the primary core.
+ */
+void plat_arm_security_setup(void)
+{
+}
diff --git a/plat/arm/css/enterprise/css_enterprise_topology.c b/plat/arm/css/enterprise/css_enterprise_topology.c
new file mode 100644
index 000000000..28791582b
--- /dev/null
+++ b/plat/arm/css/enterprise/css_enterprise_topology.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <plat_arm.h>
+#include <platform_def.h>
+
+/*
+ * The power domain tree descriptor. The cluster power domains are
+ * arranged so that when the PSCI generic code creates the power domain tree,
+ * the indices of the CPU power domain nodes it allocates match the linear
+ * indices returned by plat_core_pos_by_mpidr().
+ */
+unsigned char enterprise_pd_tree_desc[PLAT_ARM_CLUSTER_COUNT + 1];
+
+/******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is
+ * returned in case the MPIDR is invalid.
+ *****************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+	if (arm_check_mpidr(mpidr) == 0)
+		return plat_arm_calc_core_pos(mpidr);
+
+	return -1;
+}
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	int i;
+
+	enterprise_pd_tree_desc[0] = PLAT_ARM_CLUSTER_COUNT;
+
+	for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++)
+		enterprise_pd_tree_desc[i + 1] = PLAT_MAX_CORES_PER_CLUSTER;
+
+	return enterprise_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * This function returns the core count within the cluster corresponding to
+ * `mpidr`.
+ ******************************************************************************/
+unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
+{
+	return PLAT_MAX_CORES_PER_CLUSTER;
+}
diff --git a/plat/arm/css/enterprise/include/css_enterprise_def.h b/plat/arm/css/enterprise/include/css_enterprise_def.h
new file mode 100644
index 000000000..219ac7d9b
--- /dev/null
+++ b/plat/arm/css/enterprise/include/css_enterprise_def.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CSS_ENTERPRISE_DEF_H__
+#define __CSS_ENTERPRISE_DEF_H__
+
+#if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MAX_BL1_RW_SIZE	0xA000
+#else
+# define PLAT_ARM_MAX_BL1_RW_SIZE	0x6000
+#endif
+
+#if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MAX_BL2_SIZE		0x1D000
+#else
+# define PLAT_ARM_MAX_BL2_SIZE		0xC000
+#endif
+
+#define PLAT_ARM_NSTIMER_FRAME_ID	0
+
+#define PLAT_CSS_MHU_BASE		0x45000000
+#define PLAT_ARM_CCN_BASE		0x32000000
+
+#define PLAT_ARM_TRUSTED_ROM_BASE	0x0
+#define PLAT_ARM_TRUSTED_ROM_SIZE	0x00080000	/* 512KB */
+
+#define PLAT_MAX_PWR_LVL		1
+
+#define PLAT_ARM_G1S_IRQS		ARM_G1S_IRQS,			\
+					CSS_IRQ_MHU
+
+#define PLAT_ARM_G0_IRQS		ARM_G0_IRQS
+
+#define CSS_ENTERPRISE_DEVICE_BASE	(0x20000000)
+#define CSS_ENTERPRISE_DEVICE_SIZE	(0x20000000)
+#define CSS_ENTERPRISE_MAP_DEVICE	MAP_REGION_FLAT(		\
+					CSS_ENTERPRISE_DEVICE_BASE,	\
+					CSS_ENTERPRISE_DEVICE_SIZE,	\
+					MT_DEVICE | MT_RW | MT_SECURE)
+
+#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE	0x45400000
+#define ENTERPRISE_BOOT_CFG_ADDR		0x45410000
+#define PLAT_CSS_PRIMARY_CPU_SHIFT		8
+#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH		6
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE		0x30000000
+#define PLAT_ARM_GICC_BASE		0x2C000000
+
+/* Map Ashbrook cluster ID to CCN node ID */
+#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP					\
+					0,	/* Cluster 0 */		\
+					18,	/* Cluster 1 */		\
+					11,	/* Cluster 2 */		\
+					29,	/* Cluster 3 */		\
+					35,	/* Cluster 4 */		\
+					17,	/* Cluster 5 */		\
+					12,	/* Cluster 6 */		\
+					30,	/* Cluster 7 */		\
+					14,	/* Cluster 8 */		\
+					32,	/* Cluster 9 */		\
+					15,	/* Cluster 10 */	\
+					33	/* Cluster 11 */
+#endif /* __CSS_ENTERPRISE_DEF_H__ */
diff --git a/plat/arm/css/enterprise/include/plat_macros.S b/plat/arm/css/enterprise/include/plat_macros.S
new file mode 100644
index 000000000..36d69fe1c
--- /dev/null
+++ b/plat/arm/css/enterprise/include/plat_macros.S
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __PLAT_MACROS_S__
+#define __PLAT_MACROS_S__
+
+#include <css_macros.S>
+
+/*
+ * Print CCN registers
+ */
+	.macro plat_print_interconnect_regs
+	.endm
+#endif /* __PLAT_MACROS_S__ */