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| author | Vishnu Banavath <vishnu.banavath@arm.com> | 2019-10-09 14:43:18 +0100 |
|---|---|---|
| committer | Tushar Khandelwal <tushar.khandelwal@arm.com> | 2020-01-24 15:37:14 +0000 |
| commit | 211f64282cde60e87eb030500cb8ebbd03eba328 (patch) | |
| tree | 32a1820e501148416e6b67a866917347384ccf1b /readme.md | |
| parent | 1823b4070df6fb9fd214d75f08e79ba815a95a33 (diff) | |
pl011: set uart clock to 32MHzCORSTONE-700-2020.02.10
Set UART clock 32MHz to aling with FPGA
Change-Id: I10c394028ecbcda47659dfa2bf602eb4a67f1b5c
Diffstat (limited to 'readme.md')
0 files changed, 0 insertions, 0 deletions