rdn1edge ram firmware referencetopics/mcp_ramfw

This patch has been tested along with the following diff in
model-scripts. The MCP firmware displays a "hello_start" on
the console.

diff --git a/rdinfra/platforms/rdn1edge/run_model.sh b/rdinfra/platforms/rdn1edge/run_model.sh
index 89777f8..5ddc373 100755
--- a/rdinfra/platforms/rdn1edge/run_model.sh
+++ b/rdinfra/platforms/rdn1edge/run_model.sh
@@ -252,6 +252,7 @@ ${MODEL} --version
 PARAMS="-C css.cmn600.mesh_config_file=$PATH_TO_MODEL/RD_N1_E1_cmn600.yml \
        -C css.cmn600.force_on_from_start=1 \
        --data css.scp.armcortexm7ct=$OUTDIR/scp_ramfw.bin@0x0BD80000 \
+       --data css.scp.armcortexm7ct=$OUTDIR/mcp_ramfw.bin@0xAFD80000 \
        -C css.mcp.ROMloader.fname=$OUTDIR/mcp_romfw.bin \
        -C css.scp.ROMloader.fname=$OUTDIR/scp_romfw.bin \
        -C css.trustedBootROMloader.fname=$OUTDIR/$BL1_IMAGE \

Change-Id: If7d645fde9c973bbd8f8ee797a3855db7b4aa969
Signed-off-by: Prabin CA <prabin.ca@arm.com>

15 files changed, 411 insertions, 2 deletions

diff --git a/module/hello/include/mod_hello.h b/module/hello/include/mod_hello.h
new file mode 100644
index 00000000..07f86aac
--- /dev/null
+++ b/module/hello/include/mod_hello.h
@@ -0,0 +1,24 @@
+
+#ifndef MOD_HELLO_H
+#define MOD_HELLO_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <fwk_id.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <mod_log.h>
+
+struct mod_hello_module_config {
+    
+    const struct mod_hello_reg *hello_reg_val;
+
+    bool initialize_init_complete;
+
+    bool initialize_ref_en;
+
+    fwk_id_t clock_id;
+
+};
+
+#endif /* MOD_HELLO_H */
diff --git a/module/hello/src/Makefile b/module/hello/src/Makefile
new file mode 100644
index 00000000..8429c746
--- /dev/null
+++ b/module/hello/src/Makefile
@@ -0,0 +1,11 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_LIB_NAME := HELLO
+BS_LIB_SOURCES += mod_hello.c
+
+include $(BS_DIR)/lib.mk
diff --git a/module/hello/src/mod_hello.c b/module/hello/src/mod_hello.c
new file mode 100644
index 00000000..c7fcd805
--- /dev/null
+++ b/module/hello/src/mod_hello.c
@@ -0,0 +1,44 @@
+#include <fwk_thread.h>
+#include <fwk_assert.h>
+#include <fwk_macros.h>
+#include <fwk_math.h>
+#include <fwk_mm.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <fwk_notification.h>
+#include <fwk_status.h>
+#include <fwk_id.h>
+#include <mod_clock.h>
+#include <mod_hello.h>
+#include <mod_log.h>
+#include <fwk_log.h>
+
+struct mod_hello_module_config *test_config;
+
+struct mod_log_api *log_api;
+
+static int hello_init(fwk_id_t module_id, unsigned int element_count,
+                           const void *config)
+{
+    test_config = (struct mod_hello_module_config *) config;
+    return FWK_SUCCESS;
+}
+
+int hello_start(fwk_id_t id)
+{
+    FWK_LOG_INFO("[HELLO] hello_start\n"); 
+    return FWK_SUCCESS;
+}
+
+static int hello_bind(fwk_id_t id, unsigned int round)
+{
+    return FWK_SUCCESS;
+}
+
+const struct fwk_module module_hello = {
+    .name = "HELLO",
+    .type = FWK_MODULE_TYPE_DRIVER,
+    .init = hello_init,
+    .bind = hello_bind,
+    .start = hello_start,
+};
diff --git a/product/rdn1e1/include/mcp_software_mmap.h b/product/rdn1e1/include/mcp_software_mmap.h
new file mode 100644
index 00000000..2a6ff5de
--- /dev/null
+++ b/product/rdn1e1/include/mcp_software_mmap.h
@@ -0,0 +1,26 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     Software defined memory map shared between MCP and AP cores.
+ */
+
+#ifndef MCP_SOFTWARE_MMAP_H
+#define MCP_SOFTWARE_MMAP_H
+
+#include <fwk_macros.h>
+
+#define MCP_NOR_FLASH_BASE                  0xA8000000
+#define MCP_NOR_BASE                        (MCP_NOR_FLASH_BASE + 0x07D80000) //0xAFD80000
+#define MCP_IMAGE_SIZE                      (256 * FWK_KIB)
+#define MCP_MBOX_SCP_MCP_NS                 0x45610000
+#define MCP_MBOX_SCP_MCP_S                  0x45620000
+
+#define MCP_SCMI_PAYLOAD_SIZE               (128)
+
+// Define MCP_SCP SECURE NON SECURE
+
+#endif /* MCP_SOFTWARE_MMAP_H */
diff --git a/product/rdn1e1/mcp_ramfw/RTX_Config.h b/product/rdn1e1/mcp_ramfw/RTX_Config.h
new file mode 100644
index 00000000..4f4ccd1c
--- /dev/null
+++ b/product/rdn1e1/mcp_ramfw/RTX_Config.h
@@ -0,0 +1,56 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *      RTX2 v5 configuration file.
+ *      The file must be called RTX_Config.h as it is included by an RTX
+ *      file in order to create an object file containing the configuration.
+ */
+
+#ifndef RTX_CONFIG_H_
+#define RTX_CONFIG_H_
+
+/* System */
+#define OS_DYNAMIC_MEM_SIZE        0
+#define OS_TICK_FREQ               1000 /* Hz */
+#define OS_ROBIN_ENABLE            0
+#define OS_ROBIN_TIMEOUT           0
+#define OS_ISR_FIFO_QUEUE          16
+
+/* Thread */
+#define OS_THREAD_OBJ_MEM          0
+#define OS_THREAD_NUM              1
+#define OS_THREAD_DEF_STACK_NUM    0
+#define OS_THREAD_USER_STACK_SIZE  0
+#define OS_STACK_SIZE              200
+#define OS_IDLE_THREAD_STACK_SIZE  200
+#define OS_STACK_CHECK             1
+#define OS_STACK_WATERMARK         0
+#define OS_PRIVILEGE_MODE          1
+
+/* Timer */
+#define OS_TIMER_OBJ_MEM           0
+#define OS_TIMER_NUM               1
+#define OS_TIMER_THREAD_PRIO       40
+#define OS_TIMER_THREAD_STACK_SIZE 200
+#define OS_TIMER_CB_QUEUE          4
+
+/* Event flags */
+#define OS_EVFLAGS_OBJ_MEM         0
+#define OS_EVFLAGS_NUM             1
+
+#define OS_MUTEX_OBJ_MEM           0
+#define OS_MUTEX_NUM               1
+#define OS_SEMAPHORE_OBJ_MEM       0
+#define OS_SEMAPHORE_NUM           1
+#define OS_MEMPOOL_OBJ_MEM         0
+#define OS_MEMPOOL_NUM             1
+#define OS_MEMPOOL_DATA_SIZE       0
+#define OS_MSGQUEUE_OBJ_MEM        0
+#define OS_MSGQUEUE_NUM            1
+#define OS_MSGQUEUE_DATA_SIZE      0
+
+#endif /* RTX_CONFIG_H_ */
diff --git a/product/rdn1e1/mcp_ramfw/config_armv7m_mpu.c b/product/rdn1e1/mcp_ramfw/config_armv7m_mpu.c
new file mode 100644
index 00000000..29ab279a
--- /dev/null
+++ b/product/rdn1e1/mcp_ramfw/config_armv7m_mpu.c
@@ -0,0 +1,37 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <mod_armv7m_mpu.h>
+#include <mcp_rdn1e1_mmap.h>
+#include <mcp_rdn1e1_mmap_mcp.h>
+
+static const ARM_MPU_Region_t regions[] = {
+    { /* 0x0000_0000 - 0xFFFF_FFFF */
+        .RBAR = ARM_MPU_RBAR(0, 0x00000000),
+        .RASR = ARM_MPU_RASR(
+            1, ARM_MPU_AP_PRIV, 0, 1, 0, 1, 0, ARM_MPU_REGION_SIZE_4GB),
+    },
+    { /* 0x0080_0000 - 0x0087_FFFF */
+        .RBAR = ARM_MPU_RBAR(1, MCP_RAM0_BASE),
+        .RASR = ARM_MPU_RASR(
+            0, ARM_MPU_AP_PRO, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB),
+    },
+    { /* 0x2000_0000 - 0x2003_FFFF */
+        .RBAR = ARM_MPU_RBAR(2, MCP_RAM1_BASE),
+        .RASR = ARM_MPU_RASR(
+            1, ARM_MPU_AP_PRIV, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB),
+    },
+};
+
+const struct fwk_module_config config_armv7m_mpu = {
+    .data = &((struct mod_armv7m_mpu_config){
+        .region_count = FWK_ARRAY_SIZE(regions),
+        .regions = regions,
+    }),
+};
diff --git a/product/rdn1e1/mcp_ramfw/config_clock.c b/product/rdn1e1/mcp_ramfw/config_clock.c
new file mode 100644
index 00000000..8e781762
--- /dev/null
+++ b/product/rdn1e1/mcp_ramfw/config_clock.c
@@ -0,0 +1,10 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_module.h>
+
+const struct fwk_module_config config_clock = { 0 };
diff --git a/product/rdn1e1/mcp_ramfw/config_clock.h b/product/rdn1e1/mcp_ramfw/config_clock.h
new file mode 100644
index 00000000..9c132f8e
--- /dev/null
+++ b/product/rdn1e1/mcp_ramfw/config_clock.h
@@ -0,0 +1,28 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CONFIG_CLOCK_H
+#define CONFIG_CLOCK_H
+
+#include <fwk_macros.h>
+
+/*
+ * PIK clock rates.
+ */
+#define PIK_CLK_RATE_MCP_CORECLK  (300 * FWK_MHZ)
+#define PIK_CLK_RATE_MCP_AXICLK   (300 * FWK_MHZ)
+
+/*
+ * PIK clock indexes.
+ */
+enum clock_pik_idx {
+    CLOCK_PIK_IDX_MCP_CORECLK,
+    CLOCK_PIK_IDX_MCP_AXICLK,
+    CLOCK_PIK_IDX_COUNT
+};
+
+#endif /* CONFIG_CLOCK_H */
diff --git a/product/rdn1e1/mcp_ramfw/config_hello.c b/product/rdn1e1/mcp_ramfw/config_hello.c
new file mode 100644
index 00000000..6c167248
--- /dev/null
+++ b/product/rdn1e1/mcp_ramfw/config_hello.c
@@ -0,0 +1,15 @@
+#include <fwk_module_idx.h>
+#include <stdbool.h>
+#include <fwk_element.h>
+#include <fwk_module.h>
+#include <mod_hello.h>
+#include <scp_system_mmap.h>
+
+
+/* Configuration of the DDR PHY500 module. */
+struct fwk_module_config config_hello = {
+    .data = &((struct mod_hello_module_config) {
+            .initialize_init_complete = true,
+            .initialize_ref_en = true,
+        }),
+};
diff --git a/product/rdn1e1/mcp_ramfw/config_log.c b/product/rdn1e1/mcp_ramfw/config_log.c
new file mode 100644
index 00000000..0052c21a
--- /dev/null
+++ b/product/rdn1e1/mcp_ramfw/config_log.c
@@ -0,0 +1,54 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_banner.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_log.h>
+#include <mod_pl011.h>
+#include <mcp_rdn1e1_mmap.h>
+
+/*
+ * PL011 module
+ */
+static const struct fwk_element pl011_element_desc_table[] = {
+    [0] = {
+        .name = "uart0",
+        .data = &((struct mod_pl011_device_config) {
+            .reg_base = MCP_UART0_BASE,
+            .baud_rate_bps = 115200,
+            .clock_rate_hz = 24 * FWK_MHZ,
+            .clock_id = FWK_ID_NONE_INIT,
+            }),
+    },
+    [1] = { 0 },
+};
+
+static const struct fwk_element *get_pl011_table(fwk_id_t module_id)
+{
+    return pl011_element_desc_table;
+}
+
+struct fwk_module_config config_pl011 = {
+    .get_element_table = get_pl011_table,
+};
+
+/*
+ * Log module
+ */
+static const struct mod_log_config log_data = {
+    .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0),
+    .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0),
+    .banner = FWK_BANNER_MCP
+              FWK_BANNER_RAM_FIRMWARE
+              BUILD_VERSION_DESCRIBE_STRING "\n",
+};
+
+struct fwk_module_config config_log = {
+    .data = &log_data,
+};
diff --git a/product/rdn1e1/mcp_ramfw/firmware.mk b/product/rdn1e1/mcp_ramfw/firmware.mk
new file mode 100644
index 00000000..73f771d3
--- /dev/null
+++ b/product/rdn1e1/mcp_ramfw/firmware.mk
@@ -0,0 +1,34 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# The order of the modules in the BS_FIRMWARE_MODULES list is the order in which
+# the modules are initialized, bound, started during the pre-runtime phase.
+#
+
+
+
+BS_FIRMWARE_CPU := cortex-m7
+BS_FIRMWARE_HAS_MULTITHREADING := yes
+BS_FIRMWARE_HAS_NOTIFICATION := yes
+BS_FIRMWARE_MODULE_HEADERS_ONLY := \
+    power_domain \
+    css_clock
+
+BS_FIRMWARE_MODULES := \
+    armv7m_mpu \
+    pl011 \
+    log \
+    clock \
+    hello
+
+BS_FIRMWARE_SOURCES := \
+    rtx_config.c \
+    config_armv7m_mpu.c \
+    config_log.c \
+    config_clock.c \
+    config_hello.c
+
+include $(BS_DIR)/firmware.mk
diff --git a/product/rdn1e1/mcp_ramfw/fmw_memory.h b/product/rdn1e1/mcp_ramfw/fmw_memory.h
new file mode 100644
index 00000000..ccf74ffa
--- /dev/null
+++ b/product/rdn1e1/mcp_ramfw/fmw_memory.h
@@ -0,0 +1,32 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     RAM firmware memory layout for the linker script.
+ */
+
+#ifndef FMW_MEMORY_LD_S
+#define FMW_MEMORY_LD_S
+
+#include <mcp_system_mmap_mcp.h>
+
+#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION
+
+/*
+ * ROM memory
+ */
+#define FIRMWARE_MEM0_SIZE  MCP_RAM0_SIZE
+#define FIRMWARE_MEM0_BASE  MCP_RAM0_BASE
+
+/*
+ * RAM memory
+ */
+#define FIRMWARE_MEM1_SIZE  MCP_RAM1_SIZE
+#define FIRMWARE_MEM1_BASE  MCP_RAM1_BASE
+
+#define FIRMWARE_STACK_SIZE (1 * 1024)
+
+#endif /* FMW_MEMORY_LD_S */
diff --git a/product/rdn1e1/mcp_ramfw/rtx_config.c b/product/rdn1e1/mcp_ramfw/rtx_config.c
new file mode 100644
index 00000000..42cce583
--- /dev/null
+++ b/product/rdn1e1/mcp_ramfw/rtx_config.c
@@ -0,0 +1,35 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <cmsis_compiler.h>
+#include <rtx_lib.c>
+#include <rtx_os.h>
+#include <system_clock.h>
+
+/*
+ * Required by RTX to configure the SysTick timer.
+ */
+uint32_t SystemCoreClock = CLOCK_RATE_REFCLK;
+
+/*
+ * Idle thread
+ */
+__NO_RETURN void osRtxIdleThread(void *argument)
+{
+    while (true)
+        __WFI();
+}
+
+/*
+ * OS error handler
+ */
+uint32_t osRtxErrorNotify(uint32_t code, void *object_id)
+{
+    osRtxIdleThread(object_id);
+}
diff --git a/product/rdn1e1/mcp_romfw/config_rdn1e1_rom.c b/product/rdn1e1/mcp_romfw/config_rdn1e1_rom.c
index 23c688d9..3c135122 100644
--- a/product/rdn1e1/mcp_romfw/config_rdn1e1_rom.c
+++ b/product/rdn1e1/mcp_romfw/config_rdn1e1_rom.c
@@ -11,9 +11,11 @@
 
 #include <fwk_module.h>
 
+#include <mcp_software_mmap.h>
 const struct fwk_module_config config_rdn1e1_rom = {
     .data = &((struct rdn1e1_rom_config) {
         .ramfw_base = MCP_RAM0_BASE,
-        .load_ram_size = 0,
+	.nor_base = MCP_NOR_BASE,
+        .load_ram_size = MCP_IMAGE_SIZE,
     })
 };
diff --git a/product/rdn1e1/product.mk b/product/rdn1e1/product.mk
index 8555ebf9..5c303c29 100644
--- a/product/rdn1e1/product.mk
+++ b/product/rdn1e1/product.mk
@@ -10,4 +10,5 @@
 BS_PRODUCT_NAME := rdn1e1
 BS_FIRMWARE_LIST := scp_romfw \
                     scp_ramfw \
-                    mcp_romfw
+                    mcp_romfw \
+		    mcp_ramfw