rdn1e1: add support for RdE1Edge platform

RdE1Edge is similar to RdN1Edge platform. The major difference between
the platforms are:
RdN1Edge has 2 clusters of 4 Neoverse N1 CPUs with clock speed of 2.6Ghz
RdE1Edge has 2 clusters of 16 Neoverse E1 CPUs with clock speed of 2.3Ghz

Change-Id: Ia8218345b33ddc479200c219c533eaf701cd72a5
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

6 files changed, 642 insertions, 48 deletions

diff --git a/product/rdn1e1/include/rdn1e1_core.h b/product/rdn1e1/include/rdn1e1_core.h
index 38a6c501..05c85b3a 100644
--- a/product/rdn1e1/include/rdn1e1_core.h
+++ b/product/rdn1e1/include/rdn1e1_core.h
@@ -9,11 +9,13 @@
 #define RDN1E1_CORE_H
 
 #include <fwk_assert.h>
+#include <mod_sid.h>
+#include <rdn1e1_sds.h>
 
-#define RDN1E1_CORE_PER_CLUSTER_MAX 8
+#define RDN1E1_CORE_PER_CLUSTER_MAX 16
 
-/* RDN1E1 only has one configuration, hence the constant values */
-#define CORES_PER_CLUSTER   4
+#define CORES_PER_CLUSTER_RDN1   4
+#define CORES_PER_CLUSTER_RDE1   16
 #define NUMBER_OF_CLUSTERS  2
 
 static inline unsigned int rdn1e1_core_get_cluster_count(void)
@@ -24,14 +26,34 @@ static inline unsigned int rdn1e1_core_get_cluster_count(void)
 static inline unsigned int rdn1e1_core_get_core_per_cluster_count(
     unsigned int cluster)
 {
+    int status;
+    const struct mod_sid_info *system_info;
+
+    status = mod_sid_get_system_info(&system_info);
+    if (status != FWK_SUCCESS)
+        return status;
+
     fwk_assert(cluster < rdn1e1_core_get_cluster_count());
 
-    return CORES_PER_CLUSTER;
+    if (system_info->config_number == RDE1EDGE_CONFIG_NUM)
+        return CORES_PER_CLUSTER_RDE1;
+    else
+        return CORES_PER_CLUSTER_RDN1;
 }
 
 static inline unsigned int rdn1e1_core_get_core_count(void)
 {
-    return NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER;
+    int status;
+    const struct mod_sid_info *system_info;
+
+    status = mod_sid_get_system_info(&system_info);
+    if (status != FWK_SUCCESS)
+        return status;
+
+    if (system_info->config_number == RDE1EDGE_CONFIG_NUM)
+       return NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER_RDE1;
+    else
+       return NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER_RDN1;
 }
 
 #endif /* RDN1E1_CORE_H */
diff --git a/product/rdn1e1/include/rdn1e1_sds.h b/product/rdn1e1/include/rdn1e1_sds.h
index 019966b4..7c913ada 100644
--- a/product/rdn1e1/include/rdn1e1_sds.h
+++ b/product/rdn1e1/include/rdn1e1_sds.h
@@ -62,4 +62,9 @@ struct rdn1e1_sds_platid {
 #define RDN1E1_SDS_FEATURE_DMC_POS 1
 #define RDN1E1_SDS_FEATURE_MESSAGING_POS 2
 
+/*
+ * RdE1Edge Platform information
+ */
+#define RDE1EDGE_CONFIG_NUM 2
+
 #endif /* RDN1E1_SDS_H */
diff --git a/product/rdn1e1/scp_ramfw/config_clock.h b/product/rdn1e1/scp_ramfw/config_clock.h
index 2f66c42b..62829dce 100644
--- a/product/rdn1e1/scp_ramfw/config_clock.h
+++ b/product/rdn1e1/scp_ramfw/config_clock.h
@@ -37,6 +37,14 @@ enum clock_pik_idx {
     CLOCK_PIK_IDX_PCLKSCP,
     CLOCK_PIK_IDX_SYSPERCLK,
     CLOCK_PIK_IDX_UARTCLK,
+    CLOCK_PIK_IDX_CLUS0_CPU4,
+    CLOCK_PIK_IDX_CLUS0_CPU5,
+    CLOCK_PIK_IDX_CLUS0_CPU6,
+    CLOCK_PIK_IDX_CLUS0_CPU7,
+    CLOCK_PIK_IDX_CLUS1_CPU4,
+    CLOCK_PIK_IDX_CLUS1_CPU5,
+    CLOCK_PIK_IDX_CLUS1_CPU6,
+    CLOCK_PIK_IDX_CLUS1_CPU7,
     CLOCK_PIK_IDX_COUNT
 };
 
diff --git a/product/rdn1e1/scp_ramfw/config_css_clock.c b/product/rdn1e1/scp_ramfw/config_css_clock.c
index 48386797..7fa54dfa 100644
--- a/product/rdn1e1/scp_ramfw/config_css_clock.c
+++ b/product/rdn1e1/scp_ramfw/config_css_clock.c
@@ -15,8 +15,11 @@
 #include <mod_pik_clock.h>
 #include <scp_rdn1e1_pik.h>
 #include <config_clock.h>
+#include <mod_sid.h>
+#include <rdn1e1_sds.h>
+#include <fwk_assert.h>
 
-static const struct mod_css_clock_rate rate_table_cpu_group_0[] = {
+static const struct mod_css_clock_rate rdn1_rate_table_cpu_group_0[] = {
     {
         /* Super Underdrive */
         .rate = 1313 * FWK_MHZ,
@@ -69,7 +72,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group_0[] = {
     },
 };
 
-static const struct mod_css_clock_rate rate_table_cpu_group_1[] = {
+static const struct mod_css_clock_rate rdn1_rate_table_cpu_group_1[] = {
     {
         /* Super Underdrive */
         .rate = 1313 * FWK_MHZ,
@@ -122,34 +125,162 @@ static const struct mod_css_clock_rate rate_table_cpu_group_1[] = {
     },
 };
 
-static const fwk_id_t member_table_cpu_group_0[] = {
+static const struct mod_css_clock_rate rde1_rate_table_cpu_group_0[] = {
+    {
+        /* Super Underdrive */
+        .rate = 1313 * FWK_MHZ,
+        .pll_rate = 1313 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Underdrive */
+        .rate = 1531 * FWK_MHZ,
+        .pll_rate = 1531 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Nominal */
+        .rate = 1750 * FWK_MHZ,
+        .pll_rate = 1750 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Overdrive */
+        .rate = 2100 * FWK_MHZ,
+        .pll_rate = 2100 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Super Overdrive */
+        .rate = 2300 * FWK_MHZ,
+        .pll_rate = 2300 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+};
+
+static const struct mod_css_clock_rate rde1_rate_table_cpu_group_1[] = {
+    {
+        /* Super Underdrive */
+        .rate = 1313 * FWK_MHZ,
+        .pll_rate = 1313 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Underdrive */
+        .rate = 1531 * FWK_MHZ,
+        .pll_rate = 1531 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Nominal */
+        .rate = 1750 * FWK_MHZ,
+        .pll_rate = 1750 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Overdrive */
+        .rate = 2100 * FWK_MHZ,
+        .pll_rate = 2100 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Super Overdrive */
+        .rate = 2300 * FWK_MHZ,
+        .pll_rate = 2300 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+};
+
+static const fwk_id_t rdn1_member_table_cpu_group_0[] = {
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU3),
+};
+
+static const fwk_id_t rdn1_member_table_cpu_group_1[] = {
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU0),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU1),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU2),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU3),
+};
+
+static const fwk_id_t rde1_member_table_cpu_group_0[] = {
     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0),
     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1),
     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2),
     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU3),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU4),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU5),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU6),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU7),
 };
 
-static const fwk_id_t member_table_cpu_group_1[] = {
+static const fwk_id_t rde1_member_table_cpu_group_1[] = {
     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU0),
     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU1),
     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU2),
     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU3),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU4),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU5),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU6),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS1_CPU7),
 };
 
-static const struct fwk_element css_clock_element_table[] = {
+static const struct fwk_element css_rdn1_clock_element_table[] = {
     [CLOCK_CSS_IDX_CPU_GROUP0] = {
         .name = "CPU_GROUP_0",
         .data = &((struct mod_css_clock_dev_config) {
             .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
-            .rate_table = rate_table_cpu_group_0,
-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0),
+            .rate_table = rdn1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rdn1_rate_table_cpu_group_0),
             .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK,
             .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
                 CLOCK_PLL_IDX_CPU0),
             .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
                 MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
-            .member_table = member_table_cpu_group_0,
-            .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_0),
+            .member_table = rdn1_member_table_cpu_group_0,
+            .member_count = FWK_ARRAY_SIZE(rdn1_member_table_cpu_group_0),
             .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
                 MOD_PIK_CLOCK_API_TYPE_CSS),
             .initial_rate = 2600 * FWK_MHZ,
@@ -160,15 +291,15 @@ static const struct fwk_element css_clock_element_table[] = {
         .name = "CPU_GROUP_1",
         .data = &((struct mod_css_clock_dev_config) {
             .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
-            .rate_table = rate_table_cpu_group_1,
-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1),
+            .rate_table = rdn1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rdn1_rate_table_cpu_group_1),
             .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK,
             .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
                 CLOCK_PLL_IDX_CPU1),
             .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
                 MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
-            .member_table = member_table_cpu_group_1,
-            .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_1),
+            .member_table = rdn1_member_table_cpu_group_1,
+            .member_count = FWK_ARRAY_SIZE(rdn1_member_table_cpu_group_1),
             .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
                 MOD_PIK_CLOCK_API_TYPE_CSS),
             .initial_rate = 2600 * FWK_MHZ,
@@ -178,10 +309,61 @@ static const struct fwk_element css_clock_element_table[] = {
     [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */
 };
 
+static const struct fwk_element css_rde1_clock_element_table[] = {
+    [CLOCK_CSS_IDX_CPU_GROUP0] = {
+        .name = "CPU_GROUP_0",
+        .data = &((struct mod_css_clock_dev_config) {
+            .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
+            .rate_table = rde1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_0),
+            .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK,
+            .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
+                CLOCK_PLL_IDX_CPU0),
+            .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
+                MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
+            .member_table = rde1_member_table_cpu_group_0,
+            .member_count = FWK_ARRAY_SIZE(rde1_member_table_cpu_group_0),
+            .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
+                MOD_PIK_CLOCK_API_TYPE_CSS),
+            .initial_rate = 2300 * FWK_MHZ,
+            .modulation_supported = true,
+        }),
+    },
+    [CLOCK_CSS_IDX_CPU_GROUP1] = {
+        .name = "CPU_GROUP_1",
+        .data = &((struct mod_css_clock_dev_config) {
+            .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
+            .rate_table = rde1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_1),
+            .clock_switching_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK,
+            .pll_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
+                CLOCK_PLL_IDX_CPU1),
+            .pll_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_SYSTEM_PLL,
+                MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
+            .member_table = rde1_member_table_cpu_group_1,
+            .member_count = FWK_ARRAY_SIZE(rde1_member_table_cpu_group_1),
+            .member_api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
+                MOD_PIK_CLOCK_API_TYPE_CSS),
+            .initial_rate = 2300 * FWK_MHZ,
+            .modulation_supported = true,
+        }),
+    },
+    [CLOCK_CSS_IDX_COUNT] = { 0 }, /* Termination description. */
+};
+
 static const struct fwk_element *css_clock_get_element_table
     (fwk_id_t module_id)
 {
-    return css_clock_element_table;
+    int status;
+    const struct mod_sid_info *system_info;
+
+    status = mod_sid_get_system_info(&system_info);
+    fwk_assert(status);
+
+    if (system_info->config_number == RDE1EDGE_CONFIG_NUM)
+        return css_rde1_clock_element_table;
+    else
+        return css_rdn1_clock_element_table;
 }
 
 const struct fwk_module_config config_css_clock = {
diff --git a/product/rdn1e1/scp_ramfw/config_dvfs.c b/product/rdn1e1/scp_ramfw/config_dvfs.c
index 3ef546f6..13fcbc55 100644
--- a/product/rdn1e1/scp_ramfw/config_dvfs.c
+++ b/product/rdn1e1/scp_ramfw/config_dvfs.c
@@ -11,8 +11,11 @@
 #include <fwk_module_idx.h>
 #include <mod_dvfs.h>
 #include <config_clock.h>
+#include <mod_sid.h>
+#include <rdn1e1_sds.h>
+#include <fwk_assert.h>
 
-static struct mod_dvfs_opp opps[] = {
+static struct mod_dvfs_opp rdn1_opps[] = {
         {
             .frequency = 1313 * FWK_MHZ,
             .voltage = 100,
@@ -36,37 +39,98 @@ static struct mod_dvfs_opp opps[] = {
         { 0 }
 };
 
-static const struct mod_dvfs_domain_config cpu_group0 = {
+static struct mod_dvfs_opp rde1_opps[] = {
+        {
+            .frequency = 1313 * FWK_MHZ,
+            .voltage = 100,
+        },
+        {
+            .frequency = 1531 * FWK_MHZ,
+            .voltage = 200,
+        },
+        {
+            .frequency = 1750 * FWK_MHZ,
+            .voltage = 300,
+        },
+        {
+            .frequency = 2100 * FWK_MHZ,
+            .voltage = 400,
+        },
+        {
+            .frequency = 2300 * FWK_MHZ,
+            .voltage = 500,
+        },
+        { 0 }
+};
+
+static const struct mod_dvfs_domain_config rdn1_cpu_group0 = {
     .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 0),
     .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP0),
     .latency = 1200,
     .sustained_idx = 2,
-    .opps = opps,
+    .opps = rdn1_opps,
 };
 
-static const struct mod_dvfs_domain_config cpu_group1 = {
+static const struct mod_dvfs_domain_config rdn1_cpu_group1 = {
     .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 1),
     .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP1),
     .latency = 1200,
     .sustained_idx = 2,
-    .opps = opps,
+    .opps = rdn1_opps,
 };
 
-static const struct fwk_element element_table[] = {
+static const struct mod_dvfs_domain_config rde1_cpu_group0 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 0),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP0),
+    .latency = 1200,
+    .sustained_idx = 2,
+    .opps = rde1_opps,
+};
+
+static const struct mod_dvfs_domain_config rde1_cpu_group1 = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 1),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP1),
+    .latency = 1200,
+    .sustained_idx = 2,
+    .opps = rde1_opps,
+};
+
+static const struct fwk_element rdn1_element_table[] = {
     [0] = {
         .name = "GROUP0",
-        .data = &cpu_group0,
+        .data = &rdn1_cpu_group0,
     },
     [1] = {
         .name = "GROUP1",
-        .data = &cpu_group1,
+        .data = &rdn1_cpu_group1,
+    },
+    { 0 }
+};
+
+static const struct fwk_element rde1_element_table[] = {
+    [0] = {
+        .name = "GROUP0",
+        .data = &rde1_cpu_group0,
+    },
+    [1] = {
+        .name = "GROUP1",
+        .data = &rde1_cpu_group1,
     },
     { 0 }
 };
 
 static const struct fwk_element *dvfs_get_element_table(fwk_id_t module_id)
 {
-    return element_table;
+    int status;
+    const struct mod_sid_info *system_info;
+
+    status = mod_sid_get_system_info(&system_info);
+    fwk_assert(status);
+
+    if (system_info->config_number == RDE1EDGE_CONFIG_NUM)
+        return rde1_element_table;
+    else
+        return rdn1_element_table;
 }
 
 const struct fwk_module_config config_dvfs = {
diff --git a/product/rdn1e1/scp_ramfw/config_pik_clock.c b/product/rdn1e1/scp_ramfw/config_pik_clock.c
index 49e39441..f565e680 100644
--- a/product/rdn1e1/scp_ramfw/config_pik_clock.c
+++ b/product/rdn1e1/scp_ramfw/config_pik_clock.c
@@ -14,12 +14,15 @@
 #include <scp_rdn1e1_pik.h>
 #include <system_clock.h>
 #include <config_clock.h>
+#include <mod_sid.h>
+#include <rdn1e1_sds.h>
+#include <fwk_assert.h>
 
 /*
  * Rate lookup tables
  */
 
-static struct mod_pik_clock_rate rate_table_cpu_group_0[] = {
+static struct mod_pik_clock_rate rdn1_rate_table_cpu_group_0[] = {
     {
         .rate = 2600 * FWK_MHZ,
         .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
@@ -28,7 +31,7 @@ static struct mod_pik_clock_rate rate_table_cpu_group_0[] = {
     },
 };
 
-static struct mod_pik_clock_rate rate_table_cpu_group_1[] = {
+static struct mod_pik_clock_rate rdn1_rate_table_cpu_group_1[] = {
     {
         .rate = 2600 * FWK_MHZ,
         .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
@@ -37,6 +40,24 @@ static struct mod_pik_clock_rate rate_table_cpu_group_1[] = {
     },
 };
 
+static struct mod_pik_clock_rate rde1_rate_table_cpu_group_0[] = {
+    {
+        .rate = 2300 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .divider = 1, /* Rate adjusted via CPU PLL */
+    },
+};
+
+static struct mod_pik_clock_rate rde1_rate_table_cpu_group_1[] = {
+    {
+        .rate = 2300 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL1,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .divider = 1, /* Rate adjusted via CPU PLL */
+    },
+};
+
 static const struct mod_pik_clock_rate rate_table_sys_intclk[] = {
     {
         .rate = 2000 * FWK_MHZ,
@@ -100,7 +121,194 @@ static const struct mod_pik_clock_rate rate_table_uartclk[] = {
     },
 };
 
-static const struct fwk_element pik_clock_element_table[] = {
+static const struct fwk_element rdn1_pik_clock_element_table[] = {
+    /*
+     * Cluster 0 CPUS
+     */
+    [CLOCK_PIK_IDX_CLUS0_CPU0] = {
+        .name = "CLUS0_CPU0",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[0].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[0].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[0].MOD,
+            .rate_table = rdn1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rdn1_rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU1] = {
+        .name = "CLUS0_CPU1",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[1].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[1].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[1].MOD,
+            .rate_table = rdn1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rdn1_rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU2] = {
+        .name = "CLUS0_CPU2",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[2].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[2].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[2].MOD,
+            .rate_table = rdn1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rdn1_rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU3] = {
+        .name = "CLUS0_CPU3",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[3].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[3].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[3].MOD,
+            .rate_table = rdn1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rdn1_rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU0] = {
+        .name = "CLUS1_CPU0",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[0].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[0].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[0].MOD,
+            .rate_table = rdn1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rdn1_rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU1] = {
+        .name = "CLUS1_CPU1",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[1].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[1].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[1].MOD,
+            .rate_table = rdn1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rdn1_rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU2] = {
+        .name = "CLUS1_CPU2",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[2].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[2].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[2].MOD,
+            .rate_table = rdn1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rdn1_rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU3] = {
+        .name = "CLUS1_CPU3",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[3].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[3].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[3].MOD,
+            .rate_table = rdn1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rdn1_rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_DMC] = {
+        .name = "DMC",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->DMCCLK_CTRL,
+            .divext_reg = &PIK_SYSTEM->DMCCLK_DIV1,
+            .rate_table = rate_table_sys_dmcclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_sys_dmcclk),
+            .initial_rate = 1600 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_INTERCONNECT] = {
+        .name = "INTERCONNECT",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->INTCLK_CTRL,
+            .divext_reg = &PIK_SYSTEM->INTCLK_DIV1,
+            .rate_table = rate_table_sys_intclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_sys_intclk),
+            .initial_rate = 2000 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_SCP] = {
+        .name = "SCP",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SCP->CORECLK_CTRL,
+            .divsys_reg = &PIK_SCP->CORECLK_DIV1,
+            .rate_table = rate_table_scp,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_scp),
+            .initial_rate = 250 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_GIC] = {
+        .name = "GIC",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->GICCLK_CTRL,
+            .divsys_reg = &PIK_SYSTEM->GICCLK_DIV1,
+            .rate_table = rate_table_gicclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_gicclk),
+            .initial_rate = 1000 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_PCLKSCP] = {
+        .name = "PCLKSCP",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->PCLKSCP_CTRL,
+            .divsys_reg = &PIK_SYSTEM->PCLKSCP_DIV1,
+            .rate_table = rate_table_pclkscp,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_pclkscp),
+            .initial_rate = 400 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_SYSPERCLK] = {
+        .name = "SYSPERCLK",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->SYSPERCLK_CTRL,
+            .divsys_reg = &PIK_SYSTEM->SYSPERCLK_DIV1,
+            .rate_table = rate_table_sysperclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_sysperclk),
+            .initial_rate = 500 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_UARTCLK] = {
+        .name = "UARTCLK",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_SYSTEM->UARTCLK_CTRL,
+            .divsys_reg = &PIK_SYSTEM->UARTCLK_DIV1,
+            .rate_table = rate_table_uartclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_uartclk),
+            .initial_rate = 250 * FWK_MHZ,
+        }),
+    },
+    [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */
+};
+
+static const struct fwk_element rde1_pik_clock_element_table[] = {
     /*
      * Cluster 0 CPUS
      */
@@ -112,8 +320,8 @@ static const struct fwk_element pik_clock_element_table[] = {
             .control_reg = &PIK_CLUSTER(0)->CORECLK[0].CTRL,
             .divext_reg = &PIK_CLUSTER(0)->CORECLK[0].DIV,
             .modulator_reg = &PIK_CLUSTER(0)->CORECLK[0].MOD,
-            .rate_table = rate_table_cpu_group_0,
-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0),
+            .rate_table = rde1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_0),
         }),
     },
     [CLOCK_PIK_IDX_CLUS0_CPU1] = {
@@ -124,8 +332,8 @@ static const struct fwk_element pik_clock_element_table[] = {
             .control_reg = &PIK_CLUSTER(0)->CORECLK[1].CTRL,
             .divext_reg = &PIK_CLUSTER(0)->CORECLK[1].DIV,
             .modulator_reg = &PIK_CLUSTER(0)->CORECLK[1].MOD,
-            .rate_table = rate_table_cpu_group_0,
-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0),
+            .rate_table = rde1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_0),
         }),
     },
     [CLOCK_PIK_IDX_CLUS0_CPU2] = {
@@ -136,8 +344,8 @@ static const struct fwk_element pik_clock_element_table[] = {
             .control_reg = &PIK_CLUSTER(0)->CORECLK[2].CTRL,
             .divext_reg = &PIK_CLUSTER(0)->CORECLK[2].DIV,
             .modulator_reg = &PIK_CLUSTER(0)->CORECLK[2].MOD,
-            .rate_table = rate_table_cpu_group_0,
-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0),
+            .rate_table = rde1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_0),
         }),
     },
     [CLOCK_PIK_IDX_CLUS0_CPU3] = {
@@ -148,8 +356,56 @@ static const struct fwk_element pik_clock_element_table[] = {
             .control_reg = &PIK_CLUSTER(0)->CORECLK[3].CTRL,
             .divext_reg = &PIK_CLUSTER(0)->CORECLK[3].DIV,
             .modulator_reg = &PIK_CLUSTER(0)->CORECLK[3].MOD,
-            .rate_table = rate_table_cpu_group_0,
-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_0),
+            .rate_table = rde1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU4] = {
+        .name = "CLUS0_CPU4",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[4].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[4].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[4].MOD,
+            .rate_table = rde1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU5] = {
+        .name = "CLUS0_CPU5",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[5].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[5].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[5].MOD,
+            .rate_table = rde1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU6] = {
+        .name = "CLUS0_CPU6",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[6].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[6].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[6].MOD,
+            .rate_table = rde1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_0),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU7] = {
+        .name = "CLUS0_CPU7",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(0)->CORECLK[7].CTRL,
+            .divext_reg = &PIK_CLUSTER(0)->CORECLK[7].DIV,
+            .modulator_reg = &PIK_CLUSTER(0)->CORECLK[7].MOD,
+            .rate_table = rde1_rate_table_cpu_group_0,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_0),
         }),
     },
     [CLOCK_PIK_IDX_CLUS1_CPU0] = {
@@ -160,8 +416,8 @@ static const struct fwk_element pik_clock_element_table[] = {
             .control_reg = &PIK_CLUSTER(1)->CORECLK[0].CTRL,
             .divext_reg = &PIK_CLUSTER(1)->CORECLK[0].DIV,
             .modulator_reg = &PIK_CLUSTER(1)->CORECLK[0].MOD,
-            .rate_table = rate_table_cpu_group_1,
-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1),
+            .rate_table = rde1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_1),
         }),
     },
     [CLOCK_PIK_IDX_CLUS1_CPU1] = {
@@ -172,8 +428,8 @@ static const struct fwk_element pik_clock_element_table[] = {
             .control_reg = &PIK_CLUSTER(1)->CORECLK[1].CTRL,
             .divext_reg = &PIK_CLUSTER(1)->CORECLK[1].DIV,
             .modulator_reg = &PIK_CLUSTER(1)->CORECLK[1].MOD,
-            .rate_table = rate_table_cpu_group_1,
-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1),
+            .rate_table = rde1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_1),
         }),
     },
     [CLOCK_PIK_IDX_CLUS1_CPU2] = {
@@ -184,8 +440,8 @@ static const struct fwk_element pik_clock_element_table[] = {
             .control_reg = &PIK_CLUSTER(1)->CORECLK[2].CTRL,
             .divext_reg = &PIK_CLUSTER(1)->CORECLK[2].DIV,
             .modulator_reg = &PIK_CLUSTER(1)->CORECLK[2].MOD,
-            .rate_table = rate_table_cpu_group_1,
-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1),
+            .rate_table = rde1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_1),
         }),
     },
     [CLOCK_PIK_IDX_CLUS1_CPU3] = {
@@ -196,8 +452,56 @@ static const struct fwk_element pik_clock_element_table[] = {
             .control_reg = &PIK_CLUSTER(1)->CORECLK[3].CTRL,
             .divext_reg = &PIK_CLUSTER(1)->CORECLK[3].DIV,
             .modulator_reg = &PIK_CLUSTER(1)->CORECLK[3].MOD,
-            .rate_table = rate_table_cpu_group_1,
-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_1),
+            .rate_table = rde1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU4] = {
+        .name = "CLUS1_CPU4",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[4].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[4].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[4].MOD,
+            .rate_table = rde1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU5] = {
+        .name = "CLUS1_CPU5",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[5].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[5].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[5].MOD,
+            .rate_table = rde1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU6] = {
+        .name = "CLUS1_CPU6",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[6].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[6].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[6].MOD,
+            .rate_table = rde1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_1),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS1_CPU7] = {
+        .name = "CLUS1_CPU7",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &PIK_CLUSTER(1)->CORECLK[7].CTRL,
+            .divext_reg = &PIK_CLUSTER(1)->CORECLK[7].DIV,
+            .modulator_reg = &PIK_CLUSTER(1)->CORECLK[7].MOD,
+            .rate_table = rde1_rate_table_cpu_group_1,
+            .rate_count = FWK_ARRAY_SIZE(rde1_rate_table_cpu_group_1),
         }),
     },
     [CLOCK_PIK_IDX_DMC] = {
@@ -290,7 +594,16 @@ static const struct fwk_element pik_clock_element_table[] = {
 static const struct fwk_element *pik_clock_get_element_table
     (fwk_id_t module_id)
 {
-    return pik_clock_element_table;
+    int status;
+    const struct mod_sid_info *system_info;
+
+    status = mod_sid_get_system_info(&system_info);
+    fwk_assert(status);
+
+    if (system_info->config_number == RDE1EDGE_CONFIG_NUM)
+        return rde1_pik_clock_element_table;
+    else
+       return rdn1_pik_clock_element_table;
 }
 
 const struct fwk_module_config config_pik_clock = {