brcm: add fmac nvram fileslinaro-20180704-001linaro-mbl

Murata have released the Cypress NVRAM files for the fmac devices on
their github repo under GPLv2:

  https://github.com/murata-wireless/cyw-fmac-nvram.git

I used the repo at this point in time:

ae2c8b2  2018-03-20  Updated NVRAM for 1LV [jameelkareem-murata]

These files are needed to get the fmac devices working. Some devices
contain an option for the NVRAM file, as described in README_NVRAM.

This patch adds the file listed under Default as the .generic.txt file
as a soft link.

This patch also adds the following warning message into the NVRAM files
that doesn't appear in the original file from the Murata repo:

  # WARNING: You should probably be using a board specific NVRAM file.
  # This NVRAM file may not work with your hardware.
  # This file provides a generic config for the IP block, to be used as an
  # example
  # by vendors. It is not customised for specific devices.
  #

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

13 files changed, 1096 insertions, 0 deletions

diff --git a/WHENCE b/WHENCE
index f06f625..b6bfa22 100644
--- a/WHENCE
+++ b/WHENCE
@@ -2281,10 +2281,24 @@ File: brcm/brcmfmac4371-pcie.bin
 
 Licence: Redistributable. See LICENCE.broadcom_bcm43xx for details.
 
+File: brcm/brcmfmac43340-sdio.1BW.txt
 File: brcm/brcmfmac43340-sdio.bin
+File: brcm/brcmfmac43362-sdio.SN8000.txt
 File: brcm/brcmfmac43362-sdio.bin
+File: brcm/brcmfmac4339-sdio.1CK.txt
+File: brcm/brcmfmac4339-sdio.ZP.txt
+File: brcm/brcmfmac4339-sdio.bin
+File: brcm/brcmfmac43430-sdio.1DX.txt
+File: brcm/brcmfmac43430-sdio.1LN.txt
 File: brcm/brcmfmac43430-sdio.bin
+File: brcm/brcmfmac43455-sdio.1HK.txt
+File: brcm/brcmfmac43455-sdio.1LC.txt
+File: brcm/brcmfmac43455-sdio.1MW.txt
+File: brcm/brcmfmac43455-sdio.bin
+File: brcm/brcmfmac43455-sdio.clm_blob
+File: brcm/brcmfmac4354-sdio.1BB.txt
 File: brcm/brcmfmac4354-sdio.bin
+File: brcm/brcmfmac4356-pcie.1CX.txt
 File: brcm/brcmfmac4356-pcie.bin
 File: brcm/brcmfmac4373-sdio.bin
 File: brcm/brcmfmac4373.bin
diff --git a/brcm/README_NVRAM b/brcm/README_NVRAM
new file mode 100644
index 0000000..970af19
--- /dev/null
+++ b/brcm/README_NVRAM
@@ -0,0 +1,15 @@
+Note that the FMAC driver loads a specific NVRAM filename when coming up: "brcmfmac"+<CYW number>+<-sdio or -pcie>+".txt"
+This means that for any Murata modules which share the same chipset, we can only have one NVRAM file present in the default folder: "/lib/firmware/brcm".
+The following module NVRAM default files are included in this folder: 
+
+Cypress Chipset		Default		Options		Notes		
+=============		=======		=======		=====
+CYW4356			1CX		N/A		FMAC driver supports this chipset but not tested on i.MX6/7 Morty release.
+CYW4354			1BB		N/A
+CYW43455		1MW		1LC, 1HK
+CYW43012		1LV		N/A		
+CYW43430/CYW4343W	1DX		1LN
+CYW4339			ZP		1CK
+CYW43340/CYW43341	1BW		N/A
+CYW43362		SN8000		N/A		
+	
diff --git a/brcm/brcmfmac43340-sdio.1BW.txt b/brcm/brcmfmac43340-sdio.1BW.txt
new file mode 100644
index 0000000..f8408f6
--- /dev/null
+++ b/brcm/brcmfmac43340-sdio.1BW.txt
@@ -0,0 +1,127 @@
+# WARNING: You should probably be using a board specific NVRAM file.

+# This NVRAM file may not work with your hardware.

+# This file provides a generic config for the IP block, to be used as an example

+# by vendors. It is not customised for specific devices.

+#

+# Originally NVRAM file for BCM943341WLAGB_2 P203 board

+# For Murata 1BW

+manfid=0x2d0

+prodid=0x0653

+vendid=0x14e4

+devid=0x4386

+boardtype=0x0653

+boardrev=0x1203

+boardnum=22

+macaddr=00:90:4c:c5:12:38

+sromrev=3

+boardflags=0x0080201

+xtalfreq=37400

+nocrc=1

+ag0=255

+aa2g=1

+ccode=ALL

+#PA parameters for 2.4GHz

+pa0b0=6706

+pa0b1=-814

+pa0b2=-191

+tssifloor2g=64

+# rssi params for 2.4GHz

+rssismf2g=0xf

+rssismc2g=0x8

+rssisav2g=0x1

+cckPwrOffset=1

+PwrOffset40mhz2g=8

+# rssi params for 5GHz

+rssismf5g=0xf

+rssismc5g=0x7

+#rssisav5g=0x1

+rssisav5g=0x3

+#PA parameters for lower a-band

+pa1lob0=5785

+pa1lob1=-714

+pa1lob2=-172

+tssifloor5gl=32

+#PA parameters for midband

+pa1b0=5880

+pa1b1=-721

+pa1b2=-174

+tssifloor5gm=34

+#PA paramasdeters for high band

+pa1hib0=6206

+pa1hib1=-722

+pa1hib2=-147

+tssifloor5gh=32

+rxpo5g=0

+

+maxp2ga0=0x4c

+#  19dBm board limit; 18dBm target

+#Per rate power back-offs for g band, in .5 dB steps. Set it once you have the right numbers.

+cck2gpo=0x2222 

+# R6~54 13 dBm

+ofdm2gpo=0xaaaaaaaa

+# M0~M3 16 dBm board limit; 15 dBm target 

+mcs2gpo0=0xcccc

+# M7 16dBm; M6 16 dBm; M5 16 dBm; M4 16 dBm board limit; 15 dBm target 

+mcs2gpo1=0xcccc

+

+# max power for 5G 15 dBm

+maxp5ga0=0x3c

+# 15 dBm board limit; 14 dBm target 

+maxp5gla0=0x3c

+maxp5gha0=0x3c

+#Per rate power back-offs for a band, in .5 dB steps. Set it once you have the right numbers.

+ofdm5gpo=0x22222222

+# R54 15dBm; R48 15 dBm; R6~R36 15 dBm board limit; 14 dBm target 

+ofdm5glpo=0x22222222

+ofdm5ghpo=0x22222222

+mcs5gpo0=0x4444

+# M0~M4 15dBm max ; 14 dBm target

+mcs5gpo1=0x4444

+# M7 15 dBm; M6 15 dBm; M5 15 dBm board limit; 14 dBm target

+mcs5glpo0=0x4444

+mcs5glpo1=0x4444

+mcs5ghpo0=0x4444

+mcs5ghpo1=0x0000

+

+swctrlmap_2g=0x00080008,0x00100010,0x00080008,0x011010,0x11f

+#swctrlmap_5g=0x00020002,0x00040004,0x00020002,0x011010,0x2fe

+## For GN04100

+swctrlmap_5g=0x00040004,0x00020002,0x00040004,0x011010,0x2fe

+gain=32

+triso2g=8

+triso5g=8

+#tx parameters

+loflag=0

+iqlocalidx5g=40

+dlocalidx5g=70

+iqcalidx5g=50

+lpbckmode5g=1 

+txiqlopapu5g=0

+txiqlopapu2g=0

+dlorange_lowlimit=5

+txalpfbyp=1

+txalpfpu=1

+dacrate2xen=1

+papden2g=1

+papden5g=1

+#rx parameters

+gain_settle_dly_2g=4

+gain_settle_dly_5g=4

+noise_cal_po_2g=-1

+noise_cal_po_40_2g=-1

+noise_cal_high_gain_2g=73

+noise_cal_nf_substract_val_2g=346

+noise_cal_po_5g=-1

+noise_cal_po_40_5g=-1

+noise_cal_high_gain_5g=73

+noise_cal_nf_substract_val_5g=346

+cckpapden=1

+aci_detect_en_2g=1

+interference=3

+# OOB IRQ settings -- next 4 "sd" parameters uncommented for OOB IRQ. Edge sensitive interrupt via WL_HOST_WAKE line. 

+sd_gpout=0

+sd_oobonly=1

+sd_gpval=1

+sd_gpdc=0

+Comment out HW_OOB setting -- not used for 1BW

+#mux_enab=0x11

diff --git a/brcm/brcmfmac43362-sdio.SN8000.txt b/brcm/brcmfmac43362-sdio.SN8000.txt
new file mode 100644
index 0000000..98ea594
--- /dev/null
+++ b/brcm/brcmfmac43362-sdio.SN8000.txt
@@ -0,0 +1,54 @@
+# WARNING: You should probably be using a board specific NVRAM file.

+# This NVRAM file may not work with your hardware.

+# This file provides a generic config for the IP block, to be used as an example

+# by vendors. It is not customised for specific devices.

+#

+#SN8000 Wi-Fi Module NVRAM

+manfid=0x2d0

+prodid=0x4336

+vendid=0x14e4

+devid=0x4343

+boardtype=0x0598

+boardrev=0x1207

+boardnum=777

+xtalfreq=26000

+clkreq_conf=1

+boardflags=0xa00

+sromrev=3

+wl0id=0x431b

+macaddr=00:90:4c:07:71:12

+aa2g=1

+ag0=2

+maxp2ga0=78

+ofdm2gpo=0x54321111

+mcs2gpo0=0x4444

+mcs2gpo1=0x8765

+pa0b0=0x14B8

+pa0b1=0xFD5C

+pa0b2=0xFF27

+pa0itssit=62

+pa1itssit=62

+cck2gpo=0

+cckPwrOffset=0

+cckdigfilttype=22

+ccode=0

+rssismf2g=0xa

+rssismc2g=0x3

+rssisav2g=0x7

+rfreg033=0x19

+rfreg033_cck=0x1f

+triso2g=1

+noise_cal_enable_2g=0

+pacalidx2g=10

+swctrlmap_2g=0x0c050c05,0x0a030a03,0x0a030a03,0x0,0x1ff

+RAW1=4a 0b ff ff 20 04 d0 02 62 a9

+logen_mode=0x0,0x2,0x1b,0x0,0x1b

+noise_cal_po_2g=2

+noise_cal_dbg.fab.3=1

+noise_cal_high_gain.fab.3=76

+noise_cal_nf_substract_val.fab.3=356

+noise_cal_po_2g.fab.3=4

+# OOB IRQ settings -- next 3 "sd" parameters uncommented for OOB IRQ. Edge sensitive interrupt via WL_HOST_WAKE line. 

+sd_gpout=1

+sd_oobonly=1

+sd_gpval=1

diff --git a/brcm/brcmfmac4339-sdio.1CK.txt b/brcm/brcmfmac4339-sdio.1CK.txt
new file mode 100644
index 0000000..3f082b1
--- /dev/null
+++ b/brcm/brcmfmac4339-sdio.1CK.txt
@@ -0,0 +1,110 @@
+# WARNING: You should probably be using a board specific NVRAM file.

+# This NVRAM file may not work with your hardware.

+# This file provides a generic config for the IP block, to be used as an example

+# by vendors. It is not customised for specific devices.

+#

+# Sample NVRAM for BCM94339 WLCSP with eTR,iPA, and eLNA. 

+sromrev=11

+boardrev=0x1100

+boardtype=0x06c9

+boardflags=0x10081401

+boardflags2=0x00000000

+boardflags3=0x08001188

+#boardnum=57410 

+macaddr=00:90:4c:c5:12:38

+ccode=0

+regrev=0

+antswitch=0

+pdgain2g=7

+pdgain5g=7

+tworangetssi2g=0

+tworangetssi5g=0

+vendid=0x14e4

+devid=0x43ae

+manfid=0x2d0

+#prodid=0x052e

+nocrc=1

+otpimagesize=502

+xtalfreq=37400

+extpagain2g=2

+pdetrange2g=2

+extpagain5g=2

+pdetrange5g=2

+rxgains2gelnagaina0=2

+rxgains2gtrisoa0=6

+rxgains2gtrelnabypa0=1

+rxgains5gelnagaina0=4

+rxgains5gtrisoa0=4

+rxgains5gtrelnabypa0=1

+rxchain=1

+txchain=1

+aa2g=1

+aa5g=1

+tssipos5g=0

+tssipos2g=0

+pa2ga0=0xff5c,0x1914,0xfd11

+pa2gccka0=0xff78,0x1cf7,0xfcac

+pa5ga0=0xff58,0x16dc,0xfd45,0xff61,0x16dc,0xfd44,0xff5d,0x165d,0xfd49,0xff5b,0x15a6,0xfd69

+pa5gbw40a0=0xff62,0x17aa,0xfd30,0xff65,0x17cf,0xfd2f,0xff64,0x1747,0xfd33,0xff60,0x16b8,0xfd54

+pa5gbw80a0=0xff5e,0x1740,0xfd3f,0xff5b,0x16e8,0xfd3d,0xff54,0x1654,0xfd42,0xff58,0x1614,0xfd60

+#pa5ga0=0xff58,0x16ec,0xfd45,0xff61,0x170c,0xfd44,0xff5d,0x16dd,0xfd49,0xff5b,0x1616,0xfd69

+#pa5gbw40a0=0xff62,0x16ca,0xfd30,0xff65,0x16bf,0xfd2f,0xff64,0x1687,0xfd33,0xff60,0x15d8,0xfd54

+#pa5gbw80a0=0xff5e,0x1640,0xfd3f,0xff5b,0x1638,0xfd3d,0xff54,0x15b4,0xfd42,0xff58,0x1534,0xfd60

+# Default Target Power for 2G -- 17dBm(11)/14dBm(54)/13dBm(MCS7)/12dBm(MCS8)/12dBm(MCS9)

+maxp2ga0=74

+maxp5ga0=74,74,74,74

+cckbw202gpo=0x0000

+cckbw20ul2gpo=0x0000

+mcsbw202gpo=0xaa888888

+mcsbw402gpo=0xaa888888

+dot11agofdmhrbw202gpo=0x6666

+ofdmlrbw202gpo=0x0066

+tssifloor2g=500

+# Default Target Power for 5G -- 14dBm(54)/13dBm(MCS7)/12dBm(MCS8)/12dBm(MCS9)

+mcsbw205glpo=0xaa888888

+mcsbw405glpo=0xaa888888

+mcsbw805glpo=0xaa888888

+mcsbw205gmpo=0xaa888888

+mcsbw405gmpo=0xaa888888

+mcsbw805gmpo=0xaa888888

+mcsbw205ghpo=0xaa888888

+mcsbw405ghpo=0xaa888888

+mcsbw805ghpo=0xaa888888

+mcslr5glpo=0x0000

+mcslr5gmpo=0x0000

+mcslr5ghpo=0x0000

+sb20in40hrpo=0x0

+sb20in80and160hr5glpo=0x0

+sb40and80hr5glpo=0x0

+sb20in80and160hr5gmpo=0x0

+sb40and80hr5gmpo=0x0

+sb20in80and160hr5ghpo=0x0

+sb40and80hr5ghpo=0x0

+sb20in40lrpo=0x0

+sb20in80and160lr5glpo=0x0

+sb40and80lr5glpo=0x0

+sb20in80and160lr5gmpo=0x0

+sb40and80lr5gmpo=0x0

+sb20in80and160lr5ghpo=0x0

+sb40and80lr5ghpo=0x0

+dot11agduphrpo=0x0

+dot11agduplrpo=0x0

+phycal_tempdelta=25

+cckdigfilttype=2

+swctrlmap_5g=0x00080008,0x00500010,0x00100008,0x000000,0x078

+swctrlmap_2g=0x00010001,0x00220002,0x00020001,0x042202,0x1ff

+swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000

+swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000

+#

+# muxenab defined to enable OOB IRQ. Level sensitive interrupt via WL_HOST_WAKE line. 

+muxenab=0x10

+#sd_gpout=0

+#sd_oobonly=1

+#

+rssicorrnorm_c0=-2,0

+rssicorrnorm5g_c0=3,5,2,3,4,2,2,3,1,2,3,1

+## ED threshold level to address the new ETSI requirement - 10/31/2013

+ed_thresh2g=-77

+ed_thresh5g=-77

+#

+paparambwver=1

diff --git a/brcm/brcmfmac4339-sdio.ZP.txt b/brcm/brcmfmac4339-sdio.ZP.txt
new file mode 100644
index 0000000..7f58a98
--- /dev/null
+++ b/brcm/brcmfmac4339-sdio.ZP.txt
@@ -0,0 +1,107 @@
+# WARNING: You should probably be using a board specific NVRAM file.
+# This NVRAM file may not work with your hardware.
+# This file provides a generic config for the IP block, to be used as an example
+# by vendors. It is not customised for specific devices.
+#
+# Sample NVRAM for BCM94339 WLCSP with eTR,iPA, and eLNA. 
+sromrev=11
+boardrev=0x1100
+boardtype=0x06c9
+boardflags=0x10081401
+boardflags2=0x00000000
+boardflags3=0x08001188
+#boardnum=57410 
+macaddr=00:90:4c:c5:12:38
+ccode=0
+regrev=0
+antswitch=0
+pdgain2g=7
+pdgain5g=7
+tworangetssi2g=0
+tworangetssi5g=0
+vendid=0x14e4
+devid=0x43ae
+manfid=0x2d0
+#prodid=0x052e
+nocrc=1
+otpimagesize=502
+xtalfreq=37400
+extpagain2g=2
+pdetrange2g=2
+extpagain5g=2
+pdetrange5g=2
+rxgains2gelnagaina0=2
+rxgains2gtrisoa0=6
+rxgains2gtrelnabypa0=1
+rxgains5gelnagaina0=4
+rxgains5gtrisoa0=4
+rxgains5gtrelnabypa0=1
+rxchain=1
+txchain=1
+aa2g=1
+aa5g=1
+tssipos5g=0
+tssipos2g=0
+pa2ga0=0xFF47,0x17B5,0xFD2B
+pa2gccka0=0xFF5F,0x1B46,0xFCCC
+pa5ga0=0xff54,0x16ec,0xfd45,0xff52,0x16a1,0xfd4d,0xff46,0x15b7,0xfd5a,0xff56,0x156d,0xfd79
+pa5gbw40a0=0xff59,0x17ca,0xfd30,0xff42,0x163d,0xfd4b,0xff31,0x152e,0xfd55,0xff60,0x16d8,0xfd54
+pa5gbw80a0=0xff56,0x1740,0xfd3f,0xff50,0x1738,0xfd3d,0xff4d,0x16b4,0xfd42,0xff58,0x1634,0xfd60
+# Default Target Power for 2G -- 17dBm(11)/14dBm(54)/13dBm(MCS7)/12dBm(MCS8)/12dBm(MCS9)
+maxp2ga0=74
+maxp5ga0=74,74,74,74
+cckbw202gpo=0x0000
+cckbw20ul2gpo=0x0000
+mcsbw202gpo=0xaa888888
+mcsbw402gpo=0xaa888888
+dot11agofdmhrbw202gpo=0x6666
+ofdmlrbw202gpo=0x0066
+tssifloor2g=500
+# Default Target Power for 5G -- 14dBm(54)/13dBm(MCS7)/12dBm(MCS8)/12dBm(MCS9)
+mcsbw205glpo=0xaa866666
+mcsbw405glpo=0xaa866666
+mcsbw805glpo=0xaa866666
+mcsbw205gmpo=0xaa866666
+mcsbw405gmpo=0xaa866666
+mcsbw805gmpo=0xaa866666
+mcsbw205ghpo=0xaa866666
+mcsbw405ghpo=0xaa866666
+mcsbw805ghpo=0xaa866666
+mcslr5glpo=0x0000
+mcslr5gmpo=0x0000
+mcslr5ghpo=0x0000
+sb20in40hrpo=0x0
+sb20in80and160hr5glpo=0x0
+sb40and80hr5glpo=0x0
+sb20in80and160hr5gmpo=0x0
+sb40and80hr5gmpo=0x0
+sb20in80and160hr5ghpo=0x0
+sb40and80hr5ghpo=0x0
+sb20in40lrpo=0x0
+sb20in80and160lr5glpo=0x0
+sb40and80lr5glpo=0x0
+sb20in80and160lr5gmpo=0x0
+sb40and80lr5gmpo=0x0
+sb20in80and160lr5ghpo=0x0
+sb40and80lr5ghpo=0x0
+dot11agduphrpo=0x0
+dot11agduplrpo=0x0
+phycal_tempdelta=25
+cckdigfilttype=2
+swctrlmap_5g=0x00080008,0x00500010,0x00100008,0x000000,0x078
+swctrlmap_2g=0x00010001,0x00220002,0x00020001,0x042202,0x1ff
+swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000
+swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000
+#
+# muxenab defined to enable OOB IRQ. Level sensitive interrupt via WL_HOST_WAKE line. 
+muxenab=0x10
+#sd_gpout=0
+#sd_oobonly=1
+#
+rssicorrnorm_c0=-2,0
+rssicorrnorm5g_c0=3,5,2,3,4,2,2,3,1,2,3,1
+## ED threshold level to address the new ETSI requirement - 10/31/2013
+ed_thresh2g=-77
+ed_thresh5g=-77
+#
+paparambwver=1
diff --git a/brcm/brcmfmac43430-sdio.1DX.txt b/brcm/brcmfmac43430-sdio.1DX.txt
new file mode 100644
index 0000000..3d665d8
--- /dev/null
+++ b/brcm/brcmfmac43430-sdio.1DX.txt
@@ -0,0 +1,48 @@
+# WARNING: You should probably be using a board specific NVRAM file.
+# This NVRAM file may not work with your hardware.
+# This file provides a generic config for the IP block, to be used as an example
+# by vendors. It is not customised for specific devices.
+#
+# 2.4 GHz, 20 MHz BW mode
+manfid=0x2d0
+prodid=0x0726
+vendid=0x14e4
+devid=0x43e2
+boardtype=0x0726
+boardrev=0x1202
+boardnum=22
+macaddr=00:90:4c:c5:12:38
+sromrev=11
+boardflags=0x00404201
+boardflags3=0x08000000
+xtalfreq=37400
+nocrc=1
+ag0=0
+aa2g=1
+ccode=ALL
+#pa0itssit=0x20
+extpagain2g=0
+pa2ga0=-145,6667,-751
+AvVmid_c0=0x0,0xc8
+cckpwroffset0=2
+maxp2ga0=74
+#txpwrbckof=6
+cckbw202gpo=0
+legofdmbw202gpo=0x88888888
+mcsbw202gpo=0xaaaaaaaa
+propbw202gpo=0xdd
+ofdmdigfilttype=18
+ofdmdigfilttypebe=18
+papdmode=1
+papdvalidtest=1
+pacalidx2g=48
+papdepsoffset=-22
+papdendidx=58
+il0macaddr=00:90:4c:c5:12:38
+wl0id=0x431b
+# muxenab defined to enable OOB IRQ. Level sensitive interrupt via WL_HOST_WAKE line. 
+muxenab=0x10
+#BT COEX deferral limit setting
+#btc_params 8 45000
+#btc_params 10 20000
+#spurconfig=0x3
diff --git a/brcm/brcmfmac43430-sdio.1LN.txt b/brcm/brcmfmac43430-sdio.1LN.txt
new file mode 120000
index 0000000..b1e3c8f
--- /dev/null
+++ b/brcm/brcmfmac43430-sdio.1LN.txt
@@ -0,0 +1 @@
+brcmfmac43430-sdio.1DX.txt
\ No newline at end of file
diff --git a/brcm/brcmfmac43455-sdio.1HK.txt b/brcm/brcmfmac43455-sdio.1HK.txt
new file mode 100644
index 0000000..d7f382b
--- /dev/null
+++ b/brcm/brcmfmac43455-sdio.1HK.txt
@@ -0,0 +1,126 @@
+# WARNING: You should probably be using a board specific NVRAM file.

+# This NVRAM file may not work with your hardware.

+# This file provides a generic config for the IP block, to be used as an example

+# by vendors. It is not customised for specific devices.

+#

+# Cloned from bcm94345wlpagb.txt 

+NVRAMRev=$Rev: 498373 $

+sromrev=11

+vendid=0x14e4

+devid=0x43ab

+manfid=0x2d0

+prodid=0x06e4

+macaddr=00:90:4c:c5:12:38

+nocrc=1

+boardtype=0x6e4

+##boardrev - superseded by the one in OTP

+boardrev=0x1100

+xtalfreq=37400

+## tune where necessary

+#xtal_swcapio=0x6644

+boardflags=0x00080201

+boardflags2=0x40000000

+boardflags3=0x48200100

+rxchain=1

+txchain=1

+aa2g=1

+aa5g=1

+tssipos5g=1

+tssipos2g=1

+AvVmid_c0=0,157,1,126,1,126,1,126,1,126

+pa2ga0=-152,5813,-647

+pa2ga1=0xff70,0xfec,0xfddd

+pa5ga0=-165,5678,-678,-169,5682,-681,-171,5685,-677,-173,5576,-667

+#pa5ga1=-161,3544,-499,-166,3543,-497,-169,3569,-497,-171,3598,-498

+itrsw=1

+pdoffset40ma0=0x9999

+pdoffset80ma0=0x8888

+extpagain5g=2

+extpagain2g=2

+maxp2ga0=80

+cckbw202gpo=0x2222

+ofdmlrbw202gpo=0x0055

+dot11agofdmhrbw202gpo=0x7555

+mcsbw202gpo=0x77777775

+maxp5ga0=80,80,80,80

+mcsbw205glpo=0xD9774444

+mcsbw205gmpo=0xB7774442

+mcsbw205ghpo=0xD9774442

+mcsbw405glpo=0xDB777774

+mcsbw405gmpo=0xB9777774

+mcsbw405ghpo=0xDB777774

+mcsbw805glpo=0xDBBBBBBB

+mcsbw805gmpo=0xBBBBBBBB

+mcsbw805ghpo=0xDBBBBBBB

+swctrlmap_2g=0x00040004,0x00020002,0x00040004,0x010a02,0x1ff

+swctrlmap_5g=0x00100010,0x00200020,0x00200020,0x010a02,0x2f4

+swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000

+swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000

+vcodivmode=1

+##filter parameters -- tune where necessary

+cckdigfilttype=6

+fdss_level_2g=2

+fdss_level_5g=2

+## added by apps

+aga0=0x1

+agbg0=0x1

+ccode=0

+regrev=0

+ed_thresh2g=-65

+ed_thresh5g=-65

+ltecxmux=0

+ltecxpadnum=0x0504

+ltecxfnsel=0x22

+ltecxgcigpio=0x32

+# muxenab defined to enable OOB IRQ. Level sensitive interrupt via WL_HOST_WAKE line. 

+muxenab=0x10

+pdoffsetcckma0=0x0000

+powoffs2gtna0=0,0,0,0,0,0,0,0,0,0,0,0,0,0

+rssi_delta_2g_c0=0,-2,0,0

+rssi_delta_5gl_c0=1,0,0,0,0,0

+rssi_delta_5gml_c0=1,0,0,0,1,0

+rssi_delta_5gmu_c0=1,0,1,0,1,0

+rssi_delta_5gh_c0=1,0,1,0,1,0

+tempthresh=120

+temps_hysteresis=15

+tempoffset=255

+rawtempsense=0x1ff

+tworangetssi2g=1

+tworangetssi5g=0

+lowpowerrange2g=0

+lowpowerrange5g=0

+ag0=1

+ag1=1

+#subband5gver=0x4

+mcslr5glpo=0x0000

+mcslr5gmpo=0x0000

+mcslr5ghpo=0x0000

+sb20in40hrpo=0x0

+sb20in80and160hr5glpo=0x0

+sb40and80hr5glpo=0x0

+sb20in80and160hr5gmpo=0x0

+sb40and80hr5gmpo=0x0

+sb20in80and160hr5ghpo=0x0

+sb40and80hr5ghpo=0x0

+sb20in40lrpo=0x0

+sb20in80and160lr5glpo=0x0

+sb40and80lr5glpo=0x0

+sb20in80and160lr5gmpo=0x0

+sb40and80lr5gmpo=0x0

+sb20in80and160lr5ghpo=0x0

+sb40and80lr5ghpo=0x0

+dot11agduphrpo=0x0

+dot11agduplrpo=0x0

+phycal_tempdelta=25

+temps_period=15

+btc_mode=1

+sbpowoffs5g20mtna0=0,0,0,0

+sbpowoffs5g40mtna0=0,0,0,0

+sbpowoffs5g80mtna0=0,0,0,0 

+powoffs5g20mtna0=0,0,0,0,0,0,0

+powoffs5g40mtna0=0,0,0,0,0

+powoffs5g80mtna0=0,0,0,0,0

+ldo1=5

+cbfilttype=2

+xtal_swcapio=0x8855

+fdss_level_ch13=1,1

diff --git a/brcm/brcmfmac43455-sdio.1LC.txt b/brcm/brcmfmac43455-sdio.1LC.txt
new file mode 100644
index 0000000..d8bc46a
--- /dev/null
+++ b/brcm/brcmfmac43455-sdio.1LC.txt
@@ -0,0 +1,78 @@
+# WARNING: You should probably be using a board specific NVRAM file.

+# This NVRAM file may not work with your hardware.

+# This file provides a generic config for the IP block, to be used as an example

+# by vendors. It is not customised for specific devices.

+#

+# Cloned from bcm94345wlpagb_p2xx.txt 

+NVRAMRev=$Rev: 498373 $

+sromrev=11

+vendid=0x14e4

+devid=0x43ab

+manfid=0x2d0

+prodid=0x06e4

+macaddr=00:90:4c:c5:12:38

+nocrc=1

+boardtype=0x6e4

+boardrev=0x1304

+xtalfreq=37400

+#boardflags: 5GHz eTR switch by default

+#            2.4GHz eTR switch by default

+#            bit1 for btcoex

+boardflags=0x00080201

+boardflags2=0x40000000

+boardflags3=0x48200100

+tworangetssi2g=1

+tworangetssi5g=0

+lowpowerrange2g=0

+lowpowerrange5g=0

+aga0=0x1

+agbg0=0x1

+ccode=0

+regrev=0

+rxchain=1

+txchain=1

+aa2g=1

+aa5g=1

+tssipos5g=1

+tssipos2g=1

+AvVmid_c0=0,157,1,126,1,126,1,126,1,126

+pa2ga0=-152,5783,-647

+pa2ga1=0xff70,0xfec,0xfddd

+pa5ga0=-165,5618,-678,-169,5652,-681,-171,5655,-677,-173,5526,-667

+#pa5ga0=-165,5778,-678,-169,5782,-681,-171,5785,-677,-173,5676,-667

+itrsw=1

+pdoffset40ma0=0x8888

+pdoffset80ma0=0x8888

+extpagain5g=2

+extpagain2g=2

+

+maxp2ga0=76

+cckbw202gpo=0x3333

+ofdmlrbw202gpo=0x0088

+dot11agofdmhrbw202gpo=0xB888

+mcsbw202gpo=0xDDDDAAAA

+

+maxp5ga0=64,64,64,64

+mcsbw205glpo=0x44444444

+mcsbw205gmpo=0x44444444

+mcsbw205ghpo=0x44444444

+mcsbw405glpo=0x77444444

+mcsbw405gmpo=0x77444444

+mcsbw405ghpo=0x77444444

+mcsbw805glpo=0xDD999999

+mcsbw805gmpo=0xDD999999

+mcsbw805ghpo=0xDD999999

+swctrlmap_2g=0x00040004,0x00020002,0x00040004,0x010a02,0x1ff

+swctrlmap_5g=0x00100010,0x00200020,0x00200020,0x010a02,0x2f4

+swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000

+swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000

+vcodivmode=1

+##filter parameters -- tune where necessary

+cckdigfilttype=6

+fdss_level_2g=2

+fdss_level_5g=2

+cbfilttype=2

+xtal_swcapio=0x8855

+fdss_level_ch13=1,1

+# muxenab defined to enable OOB IRQ. Level sensitive interrupt via WL_HOST_WAKE line. 

+muxenab=0x10

diff --git a/brcm/brcmfmac43455-sdio.1MW.txt b/brcm/brcmfmac43455-sdio.1MW.txt
new file mode 100644
index 0000000..4616be1
--- /dev/null
+++ b/brcm/brcmfmac43455-sdio.1MW.txt
@@ -0,0 +1,119 @@
+# WARNING: You should probably be using a board specific NVRAM file.

+# This NVRAM file may not work with your hardware.

+# This file provides a generic config for the IP block, to be used as an example

+# by vendors. It is not customised for specific devices.

+#

+# Cloned from bcm94345wlpagb.txt 

+NVRAMRev=$Rev: 498373 $

+sromrev=11

+vendid=0x14e4

+devid=0x43ab

+manfid=0x2d0

+prodid=0x06e4

+macaddr=00:90:4c:c5:12:38

+nocrc=1

+boardtype=0x6e4

+##boardrev - superseded by the one in OTP

+boardrev=0x1100

+xtalfreq=37400

+## tune where necessary

+#xtal_swcapio=0x6644

+boardflags=0x00080201

+boardflags2=0x40000000

+boardflags3=0x48200100

+rxchain=1

+txchain=1

+aa2g=1

+aa5g=1

+tssipos5g=1

+tssipos2g=1

+AvVmid_c0=0,157,1,126,1,126,1,126,1,126

+pa2ga0=-152,5813,-647

+pa2ga1=0xff70,0xfec,0xfddd

+pa5ga0=-165,5528,-678,-169,5532,-681,-171,5535,-677,-173,5426,-667

+#pa5ga1=-161,3544,-499,-166,3543,-497,-169,3569,-497,-171,3598,-498

+itrsw=1

+pdoffset40ma0=0x9999

+pdoffset80ma0=0x8888

+extpagain5g=2

+extpagain2g=2

+maxp2ga0=74

+cckbw202gpo=0x0000

+ofdmlrbw202gpo=0x0022

+dot11agofdmhrbw202gpo=0x6222

+mcsbw202gpo=0x86666666

+maxp5ga0=76,76,76,76

+mcsbw205glpo=0x55555555

+mcsbw205gmpo=0x55555555

+mcsbw205ghpo=0x55555555

+mcsbw405glpo=0x55555555

+mcsbw405gmpo=0x55555555

+mcsbw405ghpo=0x55555555

+mcsbw805glpo=0xbbbbbbbb

+mcsbw805gmpo=0xbbbbbbbb

+mcsbw805ghpo=0xbbbbbbbb

+swctrlmap_2g=0x00040004,0x00020002,0x00040004,0x010a02,0x1ff

+swctrlmap_5g=0x00100010,0x00200020,0x00200020,0x010a02,0x2f4

+swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000

+swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000

+vcodivmode=1

+##filter parameters -- tune where necessary

+cckdigfilttype=6

+fdss_level_2g=2

+fdss_level_5g=2

+## added by apps

+aga0=0x1

+agbg0=0x1

+ccode=0

+ed_thresh2g=-65

+ed_thresh5g=-65

+ltecxmux=0

+ltecxpadnum=0x0504

+ltecxfnsel=0x22

+ltecxgcigpio=0x32

+pdoffsetcckma0=0x0000

+powoffs2gtna0=0,0,0,0,0,0,0,0,0,0,0,0,0,0

+tempthresh=120

+temps_hysteresis=15

+rawtempsense=0x1ff

+tworangetssi2g=1

+tworangetssi5g=0

+lowpowerrange2g=0

+lowpowerrange5g=0

+ag0=1

+ag1=1

+#subband5gver=0x4

+mcslr5glpo=0x0000

+mcslr5gmpo=0x0000

+mcslr5ghpo=0x0000

+sb20in40hrpo=0x0

+sb20in80and160hr5glpo=0x0

+sb40and80hr5glpo=0x0

+sb20in80and160hr5gmpo=0x0

+sb40and80hr5gmpo=0x0

+sb20in80and160hr5ghpo=0x0

+sb40and80hr5ghpo=0x0

+sb20in40lrpo=0x0

+sb20in80and160lr5glpo=0x0

+sb40and80lr5glpo=0x0

+sb20in80and160lr5gmpo=0x0

+sb40and80lr5gmpo=0x0

+sb20in80and160lr5ghpo=0x0

+sb40and80lr5ghpo=0x0

+dot11agduphrpo=0x0

+dot11agduplrpo=0x0

+phycal_tempdelta=25

+temps_period=15

+btc_mode=1

+sbpowoffs5g20mtna0=0,0,0,0

+sbpowoffs5g40mtna0=0,0,0,0

+sbpowoffs5g80mtna0=0,0,0,0 

+powoffs5g20mtna0=0,0,0,0,0,0,0

+powoffs5g40mtna0=0,0,0,0,0

+powoffs5g80mtna0=0,0,0,0,0

+ldo1=5

+cbfilttype=2

+xtal_swcapio=0x8855

+fdss_level_ch13=1,1

+# muxenab defined to enable OOB IRQ. Level sensitive interrupt via WL_HOST_WAKE line. 

+muxenab=0x10

diff --git a/brcm/brcmfmac4354-sdio.1BB.txt b/brcm/brcmfmac4354-sdio.1BB.txt
new file mode 100644
index 0000000..f6afb06
--- /dev/null
+++ b/brcm/brcmfmac4354-sdio.1BB.txt
@@ -0,0 +1,145 @@
+# WARNING: You should probably be using a board specific NVRAM file.
+# This NVRAM file may not work with your hardware.
+# This file provides a generic config for the IP block, to be used as an example
+# by vendors. It is not customised for specific devices.
+#
+# bcm94354wlcspMS_MP_A1_7_10_82_21_12052013.txt -- 12/5/2013 by Broadcom Corporation
+# Use with 7_10_82_21 -- Murata 1BB BCM4354 WLCSP 11AC Module ES1.5
+#BCM4354 WLCSP module for iPA, eLNA board with SDIO for production package
+NVRAMRev=$Rev: 373428 $
+sromrev=11
+boardrev=0x1105
+## boardtype is subject to change
+boardtype=0x070c
+boardflags=0x12401001
+#enable eLNA both 2G/5G
+boardflags2=0x00802000
+boardflags3=0x40000108
+#boardnum=57410 
+macaddr=00:90:4c:16:70:01
+ccode=0
+regrev=0
+antswitch=0
+pdgain5g=4
+pdgain2g=4
+tworangetssi2g=0
+tworangetssi5g=0
+femctrl=10
+vendid=0x14e4
+#devid=0x43a3
+## for 4354a1
+devid=0x43df
+manfid=0x2d0
+#prodid=0x052e
+nocrc=1
+otpimagesize=502
+xtalfreq=37400
+rxgains2gelnagaina0=3
+rxgains2gtrisoa0=5
+rxgains2gtrelnabypa0=1
+rxgains5gelnagaina0=3
+rxgains5gtrisoa0=5
+rxgains5gtrelnabypa0=1
+rxgains5gmelnagaina0=3
+rxgains5gmtrisoa0=5
+rxgains5gmtrelnabypa0=1
+rxgains5ghelnagaina0=3
+rxgains5ghtrisoa0=5
+rxgains5ghtrelnabypa0=1
+rxgains2gelnagaina1=3
+rxgains2gtrisoa1=5
+rxgains2gtrelnabypa1=1
+rxgains5gelnagaina1=3
+rxgains5gtrisoa1=5
+rxgains5gtrelnabypa1=1
+rxgains5gmelnagaina1=3
+rxgains5gmtrisoa1=5
+rxgains5gmtrelnabypa1=1
+rxgains5ghelnagaina1=3
+rxgains5ghtrisoa1=5
+rxgains5ghtrelnabypa1=1
+rxchain=3
+txchain=3
+aa2g=3
+aa5g=3
+agbg0=2
+agbg1=2
+aga0=2
+aga1=2
+tssipos2g=1
+extpagain2g=2
+tssipos5g=1
+extpagain5g=2
+tempthresh=255
+tempoffset=255
+rawtempsense=0x1ff
+pa2ga0=-139,6041,-707
+pa2ga1=-150,5970,-707
+pa5ga0=-194,6069,-739,-188,6137,-743,-185,5931,-725,-171,5898,-715
+pa5ga1=-190,6248,-757,-190,6275,-759,-190,6225,-757,-184,6131,-746
+#pa5ga0=-222,5110,-638,-223,5044,-632,-200,5349,-666,-212,4807,-606
+#pa5ga1=-219,5232,-646,-219,5124,-632,-215,5364,-670,-223,4895,-614
+## Target power CASE#735433
+# 2G: 17dBm - CCK, 16dBm - OFDM 6-18, MCS0-2, 14dBm - OFDM 24-54, MCS3-6, 13dBm - MCS7-8
+# 5G 20M: 16dBm - OFDM 6-18, MCS0-2, 14dBm - OFDM 24-54, MCS3-6, 13dBm - MCS7-8
+# 5G 40M: 15dBm - MCS 0-2, 13dBm - MCS3-6, 12dBm - MCS7-9
+# 5G 80M: 14dBm - MCS 0-2, 12dBm - MCS3-6, 11dBm - MCS7-9
+maxp2ga0=74
+maxp5ga0=74,74,74,74
+maxp2ga1=74
+maxp5ga1=74,74,74,74
+subband5gver=0x4
+pdoffsetcckma0=0x4
+pdoffsetcckma1=0x4
+pdoffset40ma0=0x0000
+pdoffset80ma0=0x0000
+pdoffset40ma1=0x0000
+pdoffset80ma1=0x0000
+cckbw202gpo=0x0000
+cckbw20ul2gpo=0x0000
+mcsbw202gpo=0x88866662
+#mcsbw402gpo=0x99644422
+dot11agofdmhrbw202gpo=0x6666
+ofdmlrbw202gpo=0x0022
+mcsbw205glpo=0x88866662
+mcsbw405glpo=0xaaa88884
+mcsbw805glpo=0xcccaaaa6
+mcsbw205gmpo=0x88866662
+mcsbw405gmpo=0xaaa88884
+mcsbw805gmpo=0xcccaaaa6
+mcsbw205ghpo=0x88866662
+mcsbw405ghpo=0xaaa88884
+mcsbw805ghpo=0xcccaaaa6
+mcslr5glpo=0x0000
+mcslr5gmpo=0x0000
+mcslr5ghpo=0x0000
+sb20in40hrpo=0x0
+sb20in80and160hr5glpo=0x0
+sb40and80hr5glpo=0x0
+sb20in80and160hr5gmpo=0x0
+sb40and80hr5gmpo=0x0
+sb20in80and160hr5ghpo=0x0
+sb40and80hr5ghpo=0x0
+sb20in40lrpo=0x0
+sb20in80and160lr5glpo=0x0
+sb40and80lr5glpo=0x0
+sb20in80and160lr5gmpo=0x0
+sb40and80lr5gmpo=0x0
+sb20in80and160lr5ghpo=0x0
+sb40and80lr5ghpo=0x0
+dot11agduphrpo=0x0
+dot11agduplrpo=0x0
+phycal_tempdelta=255
+temps_period=15
+temps_hysteresis=15
+AvVmid_c0=2,140,2,145,2,145,2,145,2,145
+AvVmid_c1=2,140,2,145,2,145,2,145,2,145
+rssicorrnorm_c0=4,4
+rssicorrnorm_c1=4,4
+rssicorrnorm5g_c0=4,6,6,4,6,6,3,5,6,4,6,6
+rssicorrnorm5g_c1=4,5,7,4,5,7,3,5,7,3,5,6
+## SWCTRLMAP using AN29223K and AN29222K
+swctrlmap_5g=0x02020202,0x05050404,0x04040000,0x000000,0x047
+swctrlmap_2g=0x10081008,0x28300820,0x08200000,0x803020,0x0ff
+# muxenab defined to enable OOB IRQ. Level sensitive interrupt via WL_HOST_WAKE line. 
+muxenab=0x11
diff --git a/brcm/brcmfmac4356-pcie.1CX.txt b/brcm/brcmfmac4356-pcie.1CX.txt
new file mode 100644
index 0000000..39fefac
--- /dev/null
+++ b/brcm/brcmfmac4356-pcie.1CX.txt
@@ -0,0 +1,152 @@
+# WARNING: You should probably be using a board specific NVRAM file.
+# This NVRAM file may not work with your hardware.
+# This file provides a generic config for the IP block, to be used as an example
+# by vendors. It is not customised for specific devices.
+#
+#CYW4356 1CX WLCSP module for iPA, eLNA board with PCIE for production package
+NVRAMRev=$Rev: 373428 $
+sromrev=11
+boardrev=0x1202
+## boardtype is subject to change
+boardtype=0x0735
+boardflags=0x12401001
+#enable eLNA both 2G/5G
+boardflags2=0x00802000
+boardflags3=0x48000189
+#boardnum=57410 
+macaddr=00:90:4c:16:70:01
+ccode=0
+regrev=0
+antswitch=0
+pdgain5g=4
+pdgain2g=4
+tworangetssi2g=0
+tworangetssi5g=0
+femctrl=10
+vendid=0x14e4
+devid=0x43ec
+manfid=0x2d0
+#prodid=0x052e
+nocrc=1
+otpimagesize=484
+xtalfreq=37400
+rxgains2gelnagaina0=2
+rxgains2gtrisoa0=6
+rxgains2gtrelnabypa0=1
+rxgains5gelnagaina0=2
+rxgains5gtrisoa0=6
+rxgains5gtrelnabypa0=1
+rxgains5gmelnagaina0=2
+rxgains5gmtrisoa0=6
+rxgains5gmtrelnabypa0=1
+rxgains5ghelnagaina0=2
+rxgains5ghtrisoa0=6
+rxgains5ghtrelnabypa0=1
+rxgains2gelnagaina1=2
+rxgains2gtrisoa1=6
+rxgains2gtrelnabypa1=1
+rxgains5gelnagaina1=2
+rxgains5gtrisoa1=6
+rxgains5gtrelnabypa1=1
+rxgains5gmelnagaina1=2
+rxgains5gmtrisoa1=6
+rxgains5gmtrelnabypa1=1
+rxgains5ghelnagaina1=2
+rxgains5ghtrisoa1=6
+rxgains5ghtrelnabypa1=1
+rxchain=3
+txchain=3
+ag0=1
+ag1=1
+## aa2g/aa5g should be set to 3
+aa2g=3
+aa5g=3
+agbg0=2
+agbg1=2
+aga0=2
+aga1=2
+tssipos2g=1
+extpagain2g=2
+tssipos5g=1
+extpagain5g=2
+tempthresh=120
+temps_hysteresis=15
+tempoffset=255
+rawtempsense=0x1ff
+pa2gccka0=-122,7046,-772
+pa2gccka1=-139,6542,-744
+pa2ga0=-155,6342,-721
+pa2ga1=-120,6288,-674
+pa5ga0=-183,5892,-714,-181,5916,-712,-196,5769,-706,-191,5880,-714
+pa5ga1=-193,5954,-725,-194,5958,-728,-194,6078,-742,-199,5913,-727
+maxp2ga0=78
+maxp5ga0=74,74,74,74
+maxp2ga1=78
+maxp5ga1=74,74,74,74
+subband5gver=0x4
+pdoffsetcckma0=0x0
+pdoffsetcckma1=0x0
+#pdoffsetcckma0=0x4
+#pdoffsetcckma1=0x4
+pdoffset40ma0=0x0000
+pdoffset80ma0=0x0000
+pdoffset40ma1=0x0000
+pdoffset80ma1=0x0000
+cckbw202gpo=0x0000
+cckbw20ul2gpo=0x0000
+mcsbw202gpo=0xccaaaaaa
+mcsbw402gpo=0xaaaaaaaa
+dot11agofdmhrbw202gpo=0x6666
+ofdmlrbw202gpo=0xaa66
+mcsbw205glpo=0xca888888
+mcsbw405glpo=0xca888888
+mcsbw805glpo=0xcccccccc
+mcsbw205gmpo=0xca888888
+mcsbw405gmpo=0xca888888
+mcsbw805gmpo=0xcccccccc
+mcsbw205ghpo=0xca888888
+mcsbw405ghpo=0xca888888
+mcsbw805ghpo=0xcccccccc
+mcslr5glpo=0x0000
+mcslr5gmpo=0x0000
+mcslr5ghpo=0x0000
+sb20in40hrpo=0x0
+sb20in80and160hr5glpo=0x0
+sb40and80hr5glpo=0x0
+sb20in80and160hr5gmpo=0x0
+sb40and80hr5gmpo=0x0
+sb20in80and160hr5ghpo=0x0
+sb40and80hr5ghpo=0x0
+sb20in40lrpo=0x0
+sb20in80and160lr5glpo=0x0
+sb40and80lr5glpo=0x0
+sb20in80and160lr5gmpo=0x0
+sb40and80lr5gmpo=0x0
+sb20in80and160lr5ghpo=0x0
+sb40and80lr5ghpo=0x0
+dot11agduphrpo=0x0
+dot11agduplrpo=0x0
+phycal_tempdelta=25
+temps_period=15
+AvVmid_c0=2,140,2,145,2,145,2,145,2,145
+AvVmid_c1=2,140,2,145,2,145,2,145,2,145
+rssicorrnorm_c0=0,0
+rssicorrnorm_c1=0,0
+rssicorrnorm5g_c0=1,2,2,1,2,2,1,2,3,1,2,3
+rssicorrnorm5g_c1=2,3,4,2,3,4,0,1,2,0,1,2
+epsdelta2g0=0
+epsdelta2g1=0
+ofdmfilttype=1
+##cckfilttype
+#cckdigfilttype=2
+cckdigfilttype=5
+phy4350_ss_opt=1
+## SWCTRL map changed - 8/29
+swctrlmap_5g=0x02020202,0x05050404,0x04040000,0x000000,0x047
+swctrlmap_2g=0x140c140c,0x28300820,0x08200000,0x803020,0x0ff
+## muxenab to enable OOB signal - needed for final board
+#muxenab=0x11
+## to improve ACPR for low rates in 2GHz
+papdwar=4
+## to improve current consumption in tx
+tssisleep_en=0x1f