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Diffstat (limited to 'plat/nxp/board/warp7/include/platform_def.h')
| -rw-r--r-- | plat/nxp/board/warp7/include/platform_def.h | 203 |
1 files changed, 203 insertions, 0 deletions
diff --git a/plat/nxp/board/warp7/include/platform_def.h b/plat/nxp/board/warp7/include/platform_def.h new file mode 100644 index 0000000..a6077b6 --- /dev/null +++ b/plat/nxp/board/warp7/include/platform_def.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include "../warp7_def.h" + +/******************************************************************************* + * Platform definitions used by common code + ******************************************************************************/ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#ifndef AARCH32 +#error "Error: AARCH32 should be defined for Warp7" +#else +#define PLATFORM_LINKER_FORMAT "elf32-littlearm" +#define PLATFORM_LINKER_ARCH arm +#endif + +/******************************************************************************* + * Run-time address of the TFTF image. + * It has to match the location where the trusted firmware loads the BL3-3 + * image. + ******************************************************************************/ +#define TFTF_BASE 0x9f000000 + +#define DRAM_BASE 0x80000000 +#define DRAM_SIZE 0x20000000 + +/* Base address of non-trusted watchdog */ +#define IMX7S_WDOG_BASE 0x30280000 + +/* general timer1 */ +#define GPT1_BASE_ADDR (AIPS1_BASE + 0x2d0000) +#define IRQ_GPT1 87 + +/* Memory mapped Generic timer(system counter) interfaces. */ +#define SYS_CNT_BASE1 (AIPS2_BASE + 0x2c0000) + +/* Size of a block as mapped by a second-level translation table */ +#define L2_BLOCK_SIZE 0x80000 + +/* + * Size of memory region configured as secure DRAM by the trusted firmware + * through the TrustZone Controller. + * TODO: Get rid of this constant once tsp_crash_reporting_test1() function has + * been fixed. + */ +#define DRAM_TZ_SIZE 0x01000000ull + +/******************************************************************************* + * Base address and size for non-trusted SRAM. + ******************************************************************************/ +#define NSRAM_BASE (0x2e000000) +#define NSRAM_SIZE (0x00008000) + +/******************************************************************************* + * Corresponds to the function ID of the BL1 SMC handler for FWU process. + ******************************************************************************/ +#define BL1_SMC_CALL_COUNT 0x0 +#define BL1_SMC_UID 0x1 +/* SMC #0x2 reserved */ +#define BL1_SMC_VERSION 0x3 +#define FWU_SMC_IMAGE_COPY 0x10 +#define FWU_SMC_IMAGE_AUTH 0x11 +#define FWU_SMC_IMAGE_EXECUTE 0x12 +#define FWU_SMC_IMAGE_RESUME 0x13 +#define FWU_SMC_SEC_IMAGE_DONE 0x14 +#define FWU_SMC_UPDATE_DONE 0x15 +#define FWU_SMC_IMAGE_RESET 0x16 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +#define PLATFORM_STACK_SIZE 0xb80 + +/* Size of coherent stacks for debug and release builds */ +#if DEBUG +#define PCPU_DV_MEM_STACK_SIZE 0x400 +#else +#define PCPU_DV_MEM_STACK_SIZE 0x300 +#endif + +#define IRQ_STACK_SIZE 0x800 + +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_CLUSTER1_CORE_COUNT 1 +#define PLATFORM_CORE_COUNT 1 +#define PLATFORM_MAX_CPUS_PER_CLUSTER 1 + +#ifdef MPIDR_MAX_AFFLVL +#undef MPIDR_MAX_AFFLVL +#endif +#define MPIDR_MAX_AFFLVL 1 +#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1 +#define PLAT_MAX_PWR_LEVEL PLATFORM_MAX_AFFLVL +#define PLAT_MAX_PWR_STATES_PER_LVL 2 + +/* Local state bit width for each level in the state-ID field of power state */ +#define PLAT_LOCAL_PSTATE_WIDTH 4 + +#define MAX_IO_DEVICES 1 +#define MAX_IO_HANDLES 1 + +/* + * If you want to run without support for non-volatile memory (due to e.g. + * unavailability of a flash driver), DRAM can be used instead as workaround. + * The TFTF binary itself is loaded at 0xE0000000 so we have plenty of free + * memory at the beginning of the DRAM. Let's use the first 128MB. + * + * Please note that this won't be suitable for all test scenarios and + * for this reason some tests will be disabled in this configuration. + */ +#define TFTF_NVM_OFFSET 0x0 +#define TFTF_NVM_SIZE 0x8000000 /* 128 MB */ + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 4 +#define MAX_MMAP_REGIONS 16 + +/******************************************************************************* + * Used to align variables on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/******************************************************************************* + * Non-Secure Software Generated Interupts IDs + ******************************************************************************/ +#define IRQ_NS_SGI_0 0 +#define IRQ_NS_SGI_1 1 +#define IRQ_NS_SGI_2 2 +#define IRQ_NS_SGI_3 3 +#define IRQ_NS_SGI_4 4 +#define IRQ_NS_SGI_5 5 +#define IRQ_NS_SGI_6 6 +#define IRQ_NS_SGI_7 7 + +/* Per Table 7-1 of iMX7S reference manual */ +#define PLAT_MAX_SPI_OFFSET_ID 127 + +#define IRQ_CNTPSIRQ1 92 +/* Per-CPU Hypervisor Timer Interrupt ID */ +#define IRQ_PCPU_HP_TIMER 26 +/* Per-CPU Non-Secure Timer Interrupt ID */ +#define IRQ_PCPU_NS_TIMER 30 + +/* + * Times(in ms) used by test code for completion of different events. + * Suspend entry time for debug build is high due to the time taken + * by the VERBOSE/INFO prints. The value considers the worst case scenario + * where all CPUs are going and coming out of suspend continuously. + */ +#if DEBUG +#define PLAT_SUSPEND_ENTRY_TIME 0x100 +#define PLAT_SUSPEND_ENTRY_EXIT_TIME 0x200 +#else +#define PLAT_SUSPEND_ENTRY_TIME 10 +#define PLAT_SUSPEND_ENTRY_EXIT_TIME 20 +#endif + + +#endif /* __PLATFORM_DEF_H__ */ |